WO2021079735A1 - 半導体装置及びそれを用いた整流素子、オルタネータ - Google Patents

半導体装置及びそれを用いた整流素子、オルタネータ Download PDF

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WO2021079735A1
WO2021079735A1 PCT/JP2020/037858 JP2020037858W WO2021079735A1 WO 2021079735 A1 WO2021079735 A1 WO 2021079735A1 JP 2020037858 W JP2020037858 W JP 2020037858W WO 2021079735 A1 WO2021079735 A1 WO 2021079735A1
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region
semiconductor device
semiconductor layer
withstand voltage
zener diode
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PCT/JP2020/037858
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English (en)
French (fr)
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正樹 白石
順一 坂野
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株式会社日立パワーデバイス
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Priority to US17/766,613 priority Critical patent/US20240055423A1/en
Priority to CN202080073752.4A priority patent/CN114586178A/zh
Priority to EP20879597.1A priority patent/EP4050648A4/en
Publication of WO2021079735A1 publication Critical patent/WO2021079735A1/ja

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Definitions

  • the present invention relates to the structure of a semiconductor device, and particularly relates to a technique that is effective when applied to a power control semiconductor device that is mounted on an in-vehicle alternator (alternator) or the like and requires high reliability.
  • the alternator (alternator) that generates electricity in an automobile is equipped with a rectifier circuit that rectifies the generated AC voltage, converts it to DC voltage, and charges the battery.
  • a diode has been used as a rectifying element used in this rectifying circuit.
  • the terminal on the upper surface of the diode chip is connected to the lead electrode, and the terminal on the lower surface of the diode chip is connected to the base electrode.
  • the outer shape of the package composed of the base electrodes is circular, and the circular package is fixed to the electrode plate of the alternator by soldering or press-fitting.
  • the diode can be fixed to the electrode plate of the alternator without aligning the position of the electrode in the rotation axis direction, and the rectifying part of the alternator can be easily assembled. It is necessary to fix as many as 6 or 12 rectifying elements to the electrode plate of the alternator per alternator, and being able to easily fix the rectifying elements to the alternator is important for simplifying the alternator assembly process and reducing costs. Is.
  • a MOSFET, a control IC for controlling the MOSFET, and a capacitor for supplying power to the control IC are mounted in a conventional two-terminal circular package, and the MOSFET is turned on by a voltage between the source and drain of the MOSFET.
  • -A rectifying element for alternators that can autonomously determine off and reduce loss while using the same type of package as before is shown.
  • Patent Document 2 also discloses a rectifying element in which a Zener diode is mounted in parallel with a MOSFET and the surge energy generated at the time of load dump is consumed by the Zener diode.
  • a Zener diode is mounted in parallel with a MOSFET in order to consume surge energy, the mounting area of the MOSFET will be reduced accordingly, which limits the high output of the alternator. Therefore, for example, in Patent Document 3, a MOSFET with a built-in Zener diode, which is provided with a Zener diode having a lower breakdown voltage than a MOSFET that avalanche when a surge occurs, is mounted in the active region of the MOSFET to ensure surge withstand capability. It is shown that the output of the alternator can be increased.
  • Patent Document 4 states that a semiconductor device including a Schottky junction and a pn junction can secure a surge resistance by lowering the yield voltage of the pn junction to be lower than that of the Schottky junction and the pn junction of the guard ring portion. It is shown.
  • Japanese Unexamined Patent Publication No. 10-215552 Japanese Unexamined Patent Publication No. 2015-116053 Japanese Unexamined Patent Publication No. 2019-033144 Japanese Unexamined Patent Publication No. 2012-174878
  • 11 and 12 show the cross-sectional structure of a typical conventional MOSFET with a built-in Zener diode and the avalanche current when a surge occurs.
  • Patent Documents 3 and 4 show a structure in which a surge withstand capability can be secured by providing a structure having a low breakdown voltage in the active region, but in the actual structure, as shown in FIG. 11, the active region is shown. Is provided up to the lower part of the protective film 242 in the peripheral region, and when a surge occurs, an avalanche current is also generated in the active region under the protective film 242 as shown in FIG.
  • the avalanche current flows through the plating layer 240, the solder layer 241 and the copper block 250 connected to the opening of the protective film 242, the avalanche current concentrates around the opening of the protective film 242, and the temperature rises and breaks. There is a problem to do.
  • FIG. 3 shows the planar structure of the MOSFET with a built-in Zener diode of the present invention, which will be described later.
  • FIG. 3 shows the planar structure of the MOSFET with a built-in Zener diode of the present invention, which will be described later.
  • the openings of the copper block 250 and the protective film 242 have a rectangular shape due to processing restrictions of the copper block 250 to be mounted, particularly when the pads (gate pad 261 and source sense pad 262) are formed. ).
  • the active region under the protective film 242 becomes large, and the problems of current concentration and increase in on-resistance when the active region under the protective film is deleted become more remarkable.
  • an object of the present invention is to provide a semiconductor device including a MOSFET with a built-in Zener diode, which can achieve both improved surge withstand capability and low on-resistance.
  • the present invention relates to an active region in which a MOSFET operates in a semiconductor device including a MOSFET with a built-in Zener diode, and a peripheral region that is arranged outside the active region and maintains a withstand voltage in the peripheral portion of the chip.
  • the active region includes a first region including a chip center portion and a second region arranged outside the first region, and the withstand voltage of the first region is provided. Is lower than the withstand voltage of the second region and the withstand voltage of the peripheral region.
  • a rectifying element used for an alternator a first external electrode having a substantially circular outer peripheral portion and a substantially circular pedestal that fits within the outer peripheral portion when viewed from above, and a resin seal arranged on the pedestal
  • a stopped internal package and a second external electrode arranged on the side opposite to the first external electrode with the internal package interposed therebetween are provided, and a semiconductor device and the semiconductor device are contained in the internal package.
  • the voltage or current of the drain electrode and the source electrode of the above is input, and based on the input voltage or current, the control IC chip that drives the gate of the semiconductor device, the capacitor that supplies power to the control IC chip, and the capacitor.
  • drain frame connected to the drain electrode and a copper block connected to the source electrode, and the surfaces of the drain frame and the copper block are not sealed with the resin, and the surface of the inner package is not sealed.
  • the drain frame and the other of the copper blocks and the first external electrode are electrically connected to each other by using a bonding material, and the drain frame and the other of the copper blocks and the second external electrode are electrically connected to each other.
  • the external electrode is electrically connected to the external electrode of the above using a bonding material, and the semiconductor device is the above-mentioned semiconductor device.
  • the present invention is an alternator characterized by including the above-mentioned rectifying element.
  • a semiconductor device including a MOSFET with a built-in Zener diode, it is possible to realize a semiconductor device capable of achieving both improved surge resistance and low on-resistance.
  • FIG. 6 is a cross-sectional view taken along the line BB'in FIG.
  • FIG. 6 is a cross-sectional view taken along the line CC'of FIG.
  • It is a circuit diagram of the alternator rectifying element which concerns on Example 3 of this invention.
  • It is a circuit diagram of the alternator which concerns on Example 3 of this invention.
  • It is a figure which shows the cross-sectional structure of the conventional MOSFET with a built-in Zener diode.
  • FIG. 1 shows a cross-sectional structure of the MOSFET with a built-in Zener diode of this embodiment.
  • FIG. 2 shows the avalanche current when a surge occurs.
  • FIG. 3 shows a chip plan view of the MOSFET with a built-in Zener diode of this embodiment, and FIGS. 1 and 2 correspond to a cross-sectional view taken along the line AA'of FIG.
  • the MOSFET with a built-in Zener diode of this embodiment has an active region of the MOSFET and a peripheral region outside the active region of the MOSFET.
  • the active region has an n + substrate 201 and an n-epi layer 202 on the drain electrode 221 and a p-type channel layer 203 formed on the n-epi layer 202.
  • a trench gate 210 is formed which penetrates the p-type channel layer 203 from the semiconductor surface and reaches the n-epi layer 202 layer, and the trench gate 210 is formed of a gate oxide film 211 and a polysilicon electrode 212 filled in the trench. It is composed of.
  • n + source layer 204 is formed on the semiconductor surface, and a contact trench 213 that penetrates the n + source layer 204 and reaches the channel layer 203 is formed, and a p + contact is formed directly under the trench 213.
  • Layer 205 is formed.
  • a source electrode 220 is provided on the surface of the semiconductor layer via a trench 213 and an interlayer insulating film 214.
  • the active area has an inner peripheral portion of the active region and an outer peripheral portion of the active region outside the active region.
  • a Zener diode 230 is provided in the lower portion of the trench 213 in the inner peripheral portion of the active region, and a Zener diode is not provided in the lower portion of the trench 213 in the outer peripheral portion of the active region.
  • a plating layer 240 is provided on the source electrode 220, and a copper block 250 is connected via a solder layer 241.
  • a protective film 242 extending (extending) to the peripheral region is provided on the source electrode 220.
  • the Zener diode 230 provided in the inner peripheral portion of the active region is composed of a junction of a p layer 206 having a higher concentration than the p-type channel layer 203 and an n layer 207 having a higher concentration than the n-epi layer 202, and the Zener diode 230 is provided.
  • the withstand voltage of the inner peripheral portion of the active region is lower than the withstand voltage of the outer peripheral portion of the active region and the peripheral region where the Zener diode is not provided.
  • the Zener diode 230 is provided at the lower part of the trench 213 and at the center of the p-type channel layer 203, the current flowing when the Zener diode avalanche easily flows to the p + contact layer 205. Since the current passing through the lower part of the n + source layer 204 can be reduced, the operation of the parasitic npn transistor can be prevented and a high avalanche withstand voltage can be realized.
  • the depletion layer can be expanded to the outer circumference to ensure withstand voltage.
  • the source electrode 220 extends (extends) to a position covering the deep p-layer 208, serves as a field plate, and relaxes the electric field at the end of the deep p-layer 208.
  • the chip end has an n + field stop layer (channel stopper layer) 209 and a guard ring 222 to prevent the depletion layer from reaching the chip end with many defects and a short lifetime, and maintain the withstand voltage.
  • the withstand voltage of the Zener diode 230 in the inner peripheral portion of the active region is set lower than the withstand voltage of the outer peripheral portion of the active region and the peripheral region.
  • the withstand voltage of the Zener diode 230 increases.
  • the temperature rise is smaller than that in the inner peripheral portion of the active region. Even when the temperature rises, the withstand voltage of the Zener diode 230 is set to be lower than that of the outer peripheral portion of the active region and the peripheral region.
  • the Zener diode 230 in order to provide the Zener diode 230 only on the inner peripheral portion of the active region, after forming the trench 213 for contact, the p layer 206 and the n layer 207 constituting the Zener diode 230 are formed by ion driving. At that time, by covering the outer peripheral portion of the active region and the peripheral region with a photomask, the Zener diode 230 can be selectively formed only in the inner peripheral portion of the active region.
  • the MOSFET with a built-in Zener diode of the present embodiment described above includes an active region in which the MOSFET operates and a peripheral region that is arranged outside the active region and maintains the withstand voltage of the chip peripheral portion.
  • the active region includes a first region including the center of the chip (inner circumference of the active region) and a second region (outer circumference of the active region) arranged outside the first region (inner circumference of the active region).
  • the withstand voltage of the first region (inner peripheral portion of the active region) is formed to be lower than the withstand voltage of the second region (outer peripheral portion of the active region) and the withstand voltage of the peripheral region.
  • the withstand voltage of the first region (inner circumference of the active region)
  • a surge occurs in the MOSFET (semiconductor device) with a built-in Zener diode
  • the temperature of the first region rises
  • the second Even when the temperature is higher than the temperature of the region (outer peripheral portion of the active region) it is formed so as to be lower than the withstand voltage of the second region (outer peripheral portion of the active region) and the withstand voltage of the peripheral region.
  • a plurality of unit cells are arranged in the first region (inner circumference of the active region) and the second region (outer circumference of the active region), and the first region (inner circumference of the active region) is arranged.
  • a Zener diode 230 is provided in each of the unit cells (trench gate 210) of the unit), and the withstand voltage of the Zener diode 230 is lower than the withstand voltage of the second region (outer peripheral portion of the active region) and the withstand voltage of the peripheral region. It is formed to be.
  • FIG. 2 conceptually shows the avalanche current when a surge occurs in the structure of the MOSFET with a built-in Zener diode shown in FIG.
  • the Zener diode 230 is provided in the inner peripheral portion (protective film opening) of the active region, the withstand voltage is lower than that of the outer peripheral portion and the peripheral region of the active region, and the avalanche current is within the active region. It flows only around the circumference.
  • the avalanche current flows to the plating layer 240, the solder layer 241 and the copper block 250 without being concentrated at the end of the protective film opening. Since there is no current concentration, the temperature rise due to current concentration can be suppressed and the surge resistance can be secured. On the other hand, during normal operation, the outer peripheral portion of the active region also operates as the active region, so that the on-resistance does not increase.
  • FIG. 3 shows a chip plan view of the MOSFET with a built-in Zener diode of this embodiment.
  • the Zener diode built-in MOSFET chip 103 has a rectangular shape having a gate pad 261 and a source sense pad 262.
  • a copper block 250 that is electrically connected to the source electrode 220 is connected to the opening of the protective film 242 via a solder layer 241. Due to the ease of processing the copper block 25, the openings of the copper block 250 and the protective film 242 have a rectangular shape as shown in the figure.
  • the active region 260 is arranged as shown by the dotted line in FIG. 3, and particularly in the region beside the pads (gate pad 261 and source sense pad 262), the active region under the protective film 242 is wide, and the current at the time of avalanche Is concentrated on the end of the opening of the protective film 242, but in this embodiment, since the Zener diode is not provided on the outer peripheral portion of the active region under the protective film 242, current concentration can be prevented.
  • FIG. 4 shows a cross-sectional structure of the MOSFET with a built-in Zener diode of this embodiment.
  • FIG. 5 shows the avalanche current when a surge occurs.
  • the feature of the MOSFET with a built-in Zener diode of this embodiment is that the inner peripheral portion of the active region in which the Zener diode 230 is provided is provided in the lower part of the copper block 250. That is, the first region (inner peripheral portion of the active region) is arranged only directly under the copper terminal (copper block 250) for wiring provided in the opening of the protective film 242.
  • the Zener diode 230 is provided at the opening of the protective film 242 and also in the region where the copper block 250 is not provided, but in the present embodiment (FIG. 4). In the case, the Zener diode 230 is not provided in the region where the copper block 250 is not provided in the opening of the protective film 242.
  • the avalanche current flows linearly toward the copper block 250, so that current concentration at the end of the solder layer 241 and the end of the copper block 250 can be suppressed, and the surge withstand capacity can be reduced. Can be improved.
  • alternator rectifying element and the alternator (alternator) according to the third embodiment of the present invention will be described with reference to FIGS. 6 to 10.
  • FIG. 6 shows a top view of the alternator rectifying element 100 equipped with the MOSFET with a built-in Zener diode of the present invention described in the first or second embodiment.
  • FIG. 7 shows a BB'cross section of the rectifying element 100
  • FIG. 8 shows a CC' cross section of the rectifying element 100.
  • FIG. 9 shows a circuit diagram of the rectifying element 100
  • FIG. 10 shows a circuit diagram of an alternator (alternator) on which the rectifying element 100 is mounted.
  • the rectifying element 100 of this embodiment has a base electrode 101 having a circular outer peripheral portion, a pedestal 102 provided on the base electrode 101, and a rectangle (rectangle) provided on the pedestal 102. ) Has an internal package 300.
  • the internal package 300 includes a MOSFET chip 103 with a built-in Zener diode, a control IC chip 104, a capacitor 105, a copper block 250 mounted on the MOSFET chip 103 with a built-in Zener diode, and a MOSFET chip 103 with a built-in Zener diode. It has a drain frame 302, and lead frames 303 and 304 on which a control IC chip 104 and a capacitor 105 are mounted, and all of them are covered with a resin 305.
  • the upper surface of the copper block 250 and the lower surface of the drain frame 302 are exposed on the surface of the inner package 300 without being covered with the resin 305.
  • the upper surface of the copper block 250 is connected to the lead electrode 107 via the bonding material 306, and the lower surface of the drain frame 302 is connected to the pedestal 102 via the bonding material 306. Further, the low voltage side of the control IC chip 104 and the capacitor 105 is connected to the same lead frame 303, and the high voltage side of the capacitor 105 is connected to the lead frame 304.
  • the alternator rectifying element has a seiza structure and an inverted seat structure in which the current directions are different, and the rectifying element 100 shown in FIG. 6 has a seiza structure.
  • the inverted seat structure is not shown, the internal package 300 has a common configuration, in which the copper block 250 is connected to the pedestal 102 and the drain frame 302 is connected to the lead electrode 107.
  • FIG. 9 shows the circuit configuration of the rectifying element 100.
  • the L terminal is the base electrode 101 and the H terminal is the lead electrode 107.
  • the MOSFET chip 103 with a built-in Zener diode, the control IC chip 104, and the capacitor 105 are wired with the connection as shown in FIG.
  • the control IC chip 104 is composed of a comparator 116, a gate driver 117, and a diode 118.
  • One input terminal of the comparator 116 is connected to the H terminal, the other input terminal of the comparator 116 is connected to the L terminal, the output terminal of the comparator 116 is connected to the input terminal of the gate driver 117, and the output terminal of the gate driver 117.
  • the high voltage side terminal 110 (see FIG. 8) of the capacitor 105 is connected to the power supply terminal of the comparator 116 and the power supply terminal of the gate driver 117, and the low voltage side terminal 111 (see FIG. 8) of the capacitor 105 is an L terminal. Connected to. Further, a diode 118 for preventing backflow of electric charges of the capacitor 105 is inserted between the capacitor 105 and the H terminal.
  • the circuit shown in FIG. 9 operates as follows. When the voltage of the H terminal becomes lower than the voltage of the L terminal, the comparator 116 outputs a high voltage (or low voltage) signal, and the gate driver 117 to which the signal is input is the voltage of the gate electrode of the MOSFET chip 103 with a built-in Zener diode. Turns on the MOSFET chip 103 with a built-in Zener diode.
  • the comparator 116 outputs a low voltage (or high voltage) signal, and the gate driver 117 to which the signal is input is the gate of the MOSFET chip 103 with a built-in Zener diode.
  • the voltage of the electrode is lowered to turn off the MOSFET chip 103 with a built-in Zener diode.
  • the MOSFET chip 103 with a built-in Zener diode is autonomously turned on and off depending on the magnitude relationship between the voltages of the H terminal and the L terminal.
  • the capacitor 105 supplies the power supply voltage to the comparator 116 and the gate driver 117.
  • FIG. 10 shows an example in which the rectifying element 100 equipped with the MOSFET 103 with a built-in Zener diode of the present invention is applied to an alternator (alternator).
  • the alternator generates AC power (voltage) from a generator, rectifies the AC power (voltage) with a rectifier, and generates and outputs DC power (voltage).
  • FIG. 10 shows a circuit configuration (400) of three-phase full-wave rectification using six rectifying elements 100. It is provided with three front-seat rectifying elements 100, three upside-down rectifying elements (not shown), and a battery 401.
  • the rectifying element in the normal seat and the rectifying element in the reverse seat are connected in series, and the connection points are connected to the U-phase, V-phase, and W-phase of three-phase alternating current, and are connected from the generator. It converts alternating current to direct current and outputs direct current power (voltage) to the battery 401.
  • the present invention is not limited to the above-described embodiment, and includes various modifications.
  • the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations.
  • it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.
  • Rectifier element 101 ... Base electrode, 102 ... Pedestal, 103 ... MOSFET chip with built-in Zener diode, 104 ... Control IC chip, 105 ... Capacitor, 107 ... Lead electrode, 108 ... Resin, 109 ... Bonding material, 110 ... high voltage side terminal of capacitor, 111 ... low voltage side terminal of capacitor, 115 ... bonding wire, 116 ... comparator, 117 ... gate driver, 118 ... diode, 201 ... n + substrate, 202 ... n-epi layer, 203 ... p-type channel layer, 204 ... n + source layer, 205 ... p + contact layer, 206 ...

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Abstract

ツェナーダイオード内蔵ＭＯＳＦＥＴを備える半導体装置において、サージ耐量向上と低オン抵抗を両立可能な半導体装置を提供する。ツェナーダイオード内蔵ＭＯＳＦＥＴを備える半導体装置において、ＭＯＳＦＥＴが動作するアクティブ領域と、前記アクティブ領域よりも外側に配置され、チップ周辺部の耐圧を保持する周辺領域と、を備え、前記アクティブ領域は、チップ中心部を含む第１の領域と、前記第１の領域よりも外側に配置される第２の領域と、を有し、前記第１の領域の耐圧は、前記第２の領域の耐圧及び前記周辺領域の耐圧よりも低いことを特徴とする。

Description

半導体装置及びそれを用いた整流素子、オルタネータ
　本発明は、半導体装置の構造に係り、特に、車載用オルタネータ（交流発電機）などに搭載され、高い信頼性が要求される電力制御用半導体装置に適用して有効な技術に関する。
　自動車にて発電を行うオルタネータ（交流発電機）には、発電した交流電圧を整流して直流電圧に変換し、バッテリを充電する整流回路が設けられている。この整流回路に用いられる整流素子としては、これまでダイオードが用いられてきた。
　ダイオードを用いた整流素子は、例えば、特許文献１に示されるように、ダイオードチップの上面の端子をリード電極に接続し、ダイオードチップの下面の端子をベース電極に接続する。ベース電極から成るパッケージの外形は円形をしており、その円形のパッケージをオルタネータの電極板に半田もしくは圧入によって固定して用いる。
　円形のパッケージを用いることで、電極の回転軸方向の位置を合わせることなしにダイオードをオルタネータの電極板に固定することができ、オルタネータの整流部の組み立てが容易になる。オルタネータ一台当たり６個もしくは１２個もの多数の整流素子をオルタネータの電極板に固定する必要があり、容易に整流素子をオルタネータに固定できることは、オルタネータの組み立て工程の簡素化、低コスト化に重要である。
　しかしながら、ダイオードは安価ではあるが、順方向電圧降下があり、損失が大きい。
これに対して、近年ではダイオードに代わり、ＭＯＳＦＥＴがオルタネータ用の整流素子として使われ始めている。ＭＯＳＦＥＴを同期整流することにより、順方向電圧降下がなく０Ｖから順方向電流が立ち上がり、損失が少ない整流素子を実現可能である。
　例えば、特許文献２には、従来の２端子である円形パッケージにＭＯＳＦＥＴとそれを制御する制御ＩＣ、制御ＩＣに電源を供給するコンデンサを搭載し、ＭＯＳＦＥＴのソース・ドレイン間の電圧でＭＯＳＦＥＴのオン・オフを自律的に判定して、従来と同形のパッケージを用いたまま、低損失化できるオルタネータ向け整流素子が示されている。
　また、オルタネータでは、発電動作時にオルタネータの出力端子やバッテリの端子が外れるロードダンプと呼ばれる現象が生じたときに、発電で生じるエネルギーを内部で消費して、オルタネータの出力端子に高電圧が出力しないようにする必要がある。そのため、特許文献２には、ＭＯＳＦＥＴと並列にツェナーダイオードを搭載し、ロードダンプ時に発生するサージエネルギーをツェナーダイオードで消費する整流素子も示されている。
　サージエネルギーを消費するためにツェナーダイオードをＭＯＳＦＥＴと並列に搭載すると、その分ＭＯＳＦＥＴの搭載面積が小さくなるため、オルタネータの高出力化が制限される。そこで、例えば、特許文献３には、ＭＯＳＦＥＴのアクティブ領域内に、サージ発生時にアバランシェするＭＯＳＦＥＴより降伏電圧の低いツェナーダイオードを設けた、ツェナーダイオード内蔵ＭＯＳＦＥＴを搭載することでサージ耐量を確保しつつ、オルタネータの高出力化ができると示されている。
　また、特許文献４には、ショットキ接合とｐｎ接合を備える半導体装置であって、ｐｎ接合部の降伏電圧を、ショットキ接合及びガードリング部のｐｎ接合より低くすることで、サージ耐量を確保できると示されている。
特開平１０－２１５５５２号公報 特開２０１５－１１６０５３号公報 特開２０１９－０３３１４４号公報 特開２０１２－１７４８７８号公報
　図１１および図１２に、従来の代表的なツェナーダイオード内蔵ＭＯＳＦＥＴの断面構造とサージ発生時のアバランシェ電流を示す。
　上記特許文献３や特許文献４では、アクティブ領域内に降伏電圧の低い構造を設けることで、サージ耐量を確保できる構造を示しているが、実際の構造においては、図１１に示すようにアクティブ領域は周辺領域の保護膜２４２の下部にまで設けられており、サージが発生した際には、図１２に示すように保護膜２４２の下部にあるアクティブ領域でもアバランシェ電流が発生する。
　アバランシェ電流は、保護膜２４２の開口部に接続されたメッキ層２４０や半田層２４１、銅ブロック２５０を介して流れるため、保護膜２４２の開口部周辺にアバランシェ電流が集中し、温度が上昇し破壊するという課題がある。
　一方、保護膜２４２の開口部の下部にのみアクティブ領域を設ける構造にすると、アクティブ領域の面積が小さくなるためＭＯＳＦＥＴのオン抵抗が高くなるという課題がある。
　図３に、後述する本発明のツェナーダイオード内蔵ＭＯＳＦＥＴの平面構造を示す。図３に示すように、搭載する銅ブロック２５０の加工上の制約から銅ブロック２５０並びに保護膜２４２の開口部が長方形（矩形）の形状である場合、特にパッド（ゲートパッド２６１及びソースセンスパッド２６２）の横の部分で保護膜２４２の下部にあるアクティブ領域が大きくなり、電流集中や保護膜下のアクティブ領域を削除した際のオン抵抗増大の課題がより顕著になる。
　そこで、本発明の目的は、ツェナーダイオード内蔵ＭＯＳＦＥＴを備える半導体装置において、サージ耐量向上と低オン抵抗を両立可能な半導体装置を提供することにある。
　上記課題を解決するために、本発明は、ツェナーダイオード内蔵ＭＯＳＦＥＴを備える半導体装置において、ＭＯＳＦＥＴが動作するアクティブ領域と、前記アクティブ領域よりも外側に配置され、チップ周辺部の耐圧を保持する周辺領域と、を備え、前記アクティブ領域は、チップ中心部を含む第１の領域と、前記第１の領域よりも外側に配置される第２の領域と、を有し、前記第１の領域の耐圧は、前記第２の領域の耐圧及び前記周辺領域の耐圧よりも低いことを特徴とする。
　また、本発明は、オルタネータに用いられる整流素子において、上面視で略円形の外周部と前記外周部内に収まる略円形の台座を有する第１の外部電極と、前記台座上に配置され、樹脂封止された内部パッケージと、前記内部パッケージを挟んで前記第１の外部電極とは反対側に配置された第２の外部電極と、を備え、前記内部パッケージ内に、半導体装置と、前記半導体装置のドレイン電極とソース電極の電圧または電流が入力され、当該入力された電圧または電流に基づいて、前記半導体装置のゲートを駆動する制御ＩＣチップと、前記制御ＩＣチップに電源を供給するコンデンサと、前記ドレイン電極と接続されたドレインフレームと、前記ソース電極と接続された銅ブロックと、を有し、前記ドレインフレーム及び前記銅ブロックの表面は前記樹脂に封止されることなく、前記内部パッケージ表面に露出しており、前記ドレインフレーム及び前記銅ブロックのいずれか一方と前記第１の外部電極とが接合材を用いて電気的に接続され、前記ドレインフレーム及び前記銅ブロックの他方と前記第２の外部電極とが接合材を用いて電気的に接続されており、前記半導体装置は、上記の半導体装置であることを特徴とする。
　また、本発明は、上記の整流素子を備えることを特徴とするオルタネータである。
　本発明によれば、ツェナーダイオード内蔵ＭＯＳＦＥＴを備える半導体装置において、サージ耐量向上と低オン抵抗を両立可能な半導体装置を実現することができる。
　これにより、ツェナーダイオード内蔵ＭＯＳＦＥＴを備える半導体装置、及びそれを用いた整流素子やオルタネータ（交流発電機）の信頼性向上と高性能化（低損失化）が図れる。
　上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。
本発明の実施例１に係るツェナーダイオード内蔵ＭＯＳＦＥＴの断面構造を示す図である。 本発明の実施例１に係るツェナーダイオード内蔵ＭＯＳＦＥＴのサージ発生時のアバランシェ電流を示す図である。 本発明の実施例１に係るツェナーダイオード内蔵ＭＯＳＦＥＴの平面構造を示す図である。 本発明の実施例２に係るツェナーダイオード内蔵ＭＯＳＦＥＴの断面構造を示す図である。 本発明の実施例２に係るツェナーダイオード内蔵ＭＯＳＦＥＴのサージ発生時のアバランシェ電流を示す図である。 本発明の実施例３に係るオルタネータ用整流素子の上面図である。 図６のＢ－Ｂ’断面図である。 図６のＣ－Ｃ’断面図である。 本発明の実施例３に係るオルタネータ用整流素子の回路図である。 本発明の実施例３に係るオルタネータの回路図である。 従来のツェナーダイオード内蔵ＭＯＳＦＥＴの断面構造を示す図である。 従来のツェナーダイオード内蔵ＭＯＳＦＥＴのサージ発生時のアバランシェ電流を示す図である。
　以下、図面を用いて本発明の実施例を説明する。なお、各図面において同一の構成については同一の符号を付し、重複する部分についてはその詳細な説明は省略する。
　図１から図３を参照して、本発明の実施例１に係るツェナーダイオード内蔵ＭＯＳＦＥＴについて説明する。図１は、本実施例のツェナーダイオード内蔵ＭＯＳＦＥＴの断面構造を示す。図２は、サージが発生した際のアバランシェ電流を示す。図３は、本実施例のツェナーダイオード内蔵ＭＯＳＦＥＴのチップ平面図を示しており、図１及び図２は、図３のＡ－Ａ’断面図に相当する。
　図１に示すように、本実施例のツェナーダイオード内蔵ＭＯＳＦＥＴは、ＭＯＳＦＥＴのアクティブ領域とその外側に周辺領域を有している。アクティブ領域は、ドレイン電極２２１上にｎ+基板２０１、ｎ－エピ層２０２があり、ｎ-エピ層２０２上にｐ型チャネル層２０３が形成されている。さらに、半導体表面からｐ型チャネル層２０３を貫き、ｎ-エピ層２０２層に到達するトレンチゲート２１０が形成されており、トレンチゲート２１０はゲート酸化膜２１１とトレンチ内に充填されたポリシリコン電極２１２で構成されている。
　半導体表面には、ｎ+ソース層２０４が形成されており、ｎ+ソース層２０４を貫きチャネル層２０３に到達するコンタクト用のトレンチ２１３が形成されており、トレンチ２１３の直下には、ｐ+コンタクト層２０５が形成されている。半導体層の表面には、トレンチ２１３及び層間絶縁膜２１４を介してソース電極２２０が設けられている。
　アクティブ領域には、アクティブ領域内周部とその外側にアクティブ領域外周部がある。アクティブ領域内周部には、トレンチ２１３の下部にツェナーダイオード２３０が設けられており、アクティブ領域外周部には、トレンチ２１３の下部にツェナーダイオードが設けられていない。アクティブ領域内周部では、ソース電極２２０の上にメッキ層２４０があり、半田層２４１を介して銅ブロック２５０が接続されている。一方、アクティブ領域外周部では、ソース電極２２０の上に周辺領域にまで延伸（延在）する保護膜２４２が設けられている。
　アクティブ領域内周部に設けられているツェナーダイオード２３０は、ｐ型チャネル層２０３より高濃度のｐ層２０６とｎ－エピ層２０２より高濃度のｎ層２０７の接合からなり、ツェナーダイオード２３０が設けられているアクティブ領域内周部の耐圧は、ツェナーダイオードが設けられていないアクティブ領域外周部や周辺領域の耐圧に比べて低くなっている。
　また、ツェナーダイオード２３０は、トレンチ２１３の下部で、なおかつ、ｐ型チャネル層２０３の中央部に設けられているため、ツェナーダイオードがアバランシェした際に流れる電流が、ｐ+コンタクト層２０５に流れやすく、ｎ+ソース層２０４の下部を通る電流を少なくすることができるため、寄生ｎｐｎトランジスタの動作を防止でき、高いアバランシェ耐量を実現できる。
　また、周辺領域には、深いｐ層２０８があり、電圧印可時に空乏層を外周へ広げ耐圧を確保することができる。また、深いｐ層２０８を覆う位置までソース電極２２０が延伸（延在）しており、フィールドプレートの役割を果たし、深いｐ層２０８端部での電界を緩和する。
　チップ端部にはｎ+のフィールドストップ層（チャネルストッパ層）２０９及びガードリング２２２があり、欠陥が多くライフタイムが短いチップ端部まで空乏層が到達するのを防止し、耐圧を保持する。
　アクティブ領域内周部のツェナーダイオード２３０の耐圧は、アクティブ領域外周部や周辺領域の耐圧よりも低く設定するが、サージ発生時は、ツェナーダイオード２３０がアバランシェし電流が流れることで温度が上昇し、ツェナーダイオード２３０の耐圧が上昇する。
　一方、アクティブ領域外周部や周辺領域はアバランシェ電流が流れないため、アクティブ領域内周部よりも温度上昇が小さくなるが、その際でも確実にツェナーダイオード２３０でサージエネルギーを吸収できるように、温度が上昇した際でも、アクティブ領域外周部や周辺領域よりツェナーダイオード２３０の耐圧が低くなるように設定する。
　図１に示すように、アクティブ領域内周部のみにツェナーダイオード２３０を設けるには、コンタクト用のトレンチ２１３を形成後、ツェナーダイオード２３０を構成するｐ層２０６とｎ層２０７をイオン打ち込みで形成する際に、アクティブ領域外周部や周辺領域をホトマスクで覆うことで、アクティブ領域内周部のみに選択的にツェナーダイオード２３０を形成することができる。
　以上説明した本実施例のツェナーダイオード内蔵ＭＯＳＦＥＴは、言い換えると、ＭＯＳＦＥＴが動作するアクティブ領域と、アクティブ領域よりも外側に配置され、チップ周辺部の耐圧を保持する周辺領域と、を備えており、アクティブ領域は、チップ中心部を含む第１の領域（アクティブ領域内周部）と、第１の領域（アクティブ領域内周部）よりも外側に配置される第２の領域（アクティブ領域外周部）と、を有し、第１の領域（アクティブ領域内周部）の耐圧は、第２の領域（アクティブ領域外周部）の耐圧及び周辺領域の耐圧よりも低くなるように形成されている。
　また、第１の領域（アクティブ領域内周部）の耐圧は、ツェナーダイオード内蔵ＭＯＳＦＥＴ（半導体装置）にサージが発生し、第１の領域（アクティブ領域内周部）の温度が上昇し、第２の領域（アクティブ領域外周部）の温度よりも高くなった場合であっても、第２の領域（アクティブ領域外周部）の耐圧及び周辺領域の耐圧よりも低くなるように形成されている。
　また、第１の領域（アクティブ領域内周部）及び第２の領域（アクティブ領域外周部）には複数の単位セル（トレンチゲート２１０）が配列されており、第１の領域（アクティブ領域内周部）の単位セル（トレンチゲート２１０）の各々にはツェナーダイオード２３０が設けられており、ツェナーダイオード２３０の耐圧は、第２の領域（アクティブ領域外周部）の耐圧及び周辺領域の耐圧よりも低くなるように形成されている。
　本実施例によるサージ耐量向上の効果を図２で説明する。図２は、図１に示すツェナーダイオード内蔵ＭＯＳＦＥＴの構造において、サージが発生した際のアバランシェ電流を概念的に示している。上述したように、アクティブ領域内周部（保護膜開口部）には、ツェナーダイオード２３０が設けられているため、アクティブ領域外周部や周辺領域に対して耐圧が低くなり、アバランシェ電流はアクティブ領域内周部にのみ流れる。
　アクティブ領域内周部の上部には保護膜２４２がないため、アバランシェ電流は保護膜開口部端部に集中することなく、メッキ層２４０や半田層２４１、銅ブロック２５０に流れる。電流集中が無いため、電流集中による温度上昇が抑制できサージ耐量を確保できる。一方、通常動作時には、アクティブ領域外周部もアクティブ領域として動作するため、オン抵抗が増大することもない。
　図３は、本実施例のツェナーダイオード内蔵ＭＯＳＦＥＴのチップ平面図を示す。ツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３は、ゲートパッド２６１及びソースセンスパッド２６２を有する長方形（矩形）の形状をしている。ソース電極２２０と電気的に接続する銅ブロック２５０が保護膜２４２の開口部に半田層２４１を介して接続されている。銅ブロック２５の加工の容易性から、銅ブロック２５０や保護膜２４２の開口部は図のような長方形（矩形）の形状をしている。
　アクティブ領域２６０は、図３の点線で示すように配置されており、特にパッド（ゲートパッド２６１及びソースセンスパッド２６２）の横の領域では、保護膜２４２下のアクティブ領域が広く、アバランシェ時の電流が保護膜２４２の開口部の端部に集中するが、本実施例では、保護膜２４２下のアクティブ領域外周部にはツェナーダイオードを設けていないので、電流集中を防止することができる。
　図４及び図５を参照して、本発明の実施例２に係るツェナーダイオード内蔵ＭＯＳＦＥＴについて説明する。図４は、本実施例のツェナーダイオード内蔵ＭＯＳＦＥＴの断面構造を示す。図５は、サージが発生した際のアバランシェ電流を示す。
　図４に示すように、本実施例のツェナーダイオード内蔵ＭＯＳＦＥＴの特徴は、ツェナーダイオード２３０が設けられているアクティブ領域内周部が銅ブロック２５０の下部に設けられている点である。つまり、第１の領域（アクティブ領域内周部）は、保護膜２４２の開口部内に設けられた配線用の銅端子（銅ブロック２５０）の直下にのみ配置されている。
　言い換えると、実施例１（図１）では、保護膜２４２の開口部で、なおかつ、銅ブロック２５０が設けられていない領域にもツェナーダイオード２３０が設けられているが、本実施例（図４）では、保護膜２４２の開口部で、なおかつ、銅ブロック２５０が設けられていない領域にはツェナーダイオード２３０が設けられていない。
　図５に示すように、サージが発生するとアバランシェ電流が銅ブロック２５０に向けて直線的に流れることでより半田層２４１の端部や銅ブロック２５０の端部での電流集中を抑制でき、サージ耐量の向上ができる。
　図６から図１０を参照して、本発明の実施例３に係るオルタネータ用整流素子とオルタネータ（交流発電機）について説明する。
　図６は、実施例１或いは実施例２で説明した本発明のツェナーダイオード内蔵ＭＯＳＦＥＴを搭載するオルタネータ用整流素子１００の上面図を示す。図７は整流素子１００のＢ－Ｂ’断面、図８は整流素子１００のＣ－Ｃ’断面をそれぞれ示す。また、図９は、整流素子１００の回路図を示し、図１０は、整流素子１００を搭載するオルタネータ（交流発電機）の回路図を示す。
　本実施例の整流素子１００は、図６から図８に示すように、円形の外周部を有するベース電極１０１、ベース電極１０１上に設けられた台座１０２、台座１０２上に設けられた長方形（矩形）の内部パッケージ３００を有している。
　内部パッケージ３００は、ツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３と、制御ＩＣチップ１０４と、コンデンサ１０５と、ツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３の上に載せられた銅ブロック２５０と、ツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３を載せているドレインフレーム３０２と、制御ＩＣチップ１０４とコンデンサ１０５を載せているリードフレーム３０３及び３０４を有しており、それら全体は樹脂３０５で覆われている。
　銅ブロック２５０の上面、及びドレインフレーム３０２の下面は樹脂３０５で覆われることなく内部パッケージ３００の表面に露出している。銅ブロック２５０の上面は、接合材３０６を介してリード電極１０７に接続され、ドレインフレーム３０２の下面は、接合材３０６を介して台座１０２に接続される。また、制御ＩＣチップ１０４とコンデンサ１０５の低電圧側が同じリードフレーム３０３に接続され、コンデンサ１０５の高電圧側はリードフレーム３０４に接続される。
　なお、オルタネータ用整流素子には、電流方向が異なる正座構造と逆座構造があり、図６で示した整流素子１００は正座構造である。逆座構造は、図示はしないが、内部パッケージ３００の構成は共通で、銅ブロック２５０が台座１０２に、ドレインフレーム３０２がリード電極１０７にそれぞれ接続される。
　図９は、整流素子１００の回路構成を示す。図９に示す回路では、Ｌ端子がベース電極１０１、Ｈ端子がリード電極１０７である。ツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３、制御ＩＣチップ１０４、コンデンサ１０５が、図９のような接続で配線される。
　制御ＩＣチップ１０４は、コンパレータ１１６、ゲートドライバ１１７、ダイオード１１８で構成される。コンパレータ１１６の一方の入力端子はＨ端子に接続され、コンパレータ１１６の他方の入力端子はＬ端子に接続され、コンパレータ１１６の出力端子はゲートドライバ１１７の入力端子に接続され、ゲートドライバ１１７の出力端子はツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３のゲート電極に接続される。
　また、コンデンサ１０５の高電圧側端子１１０（図８参照）は、コンパレータ１１６の電源端子とゲートドライバ１１７の電源端子に接続され、コンデンサ１０５の低電圧側端子１１１（図８参照）は、Ｌ端子に接続される。更に、コンデンサ１０５とＨ端子の間にコンデンサ１０５の電荷の逆流防止用のダイオード１１８が挿入される。
　図９に図示した回路は、次のように動作する。Ｈ端子の電圧がＬ端子の電圧より低くなると、コンパレータ１１６は高電圧（若しくは低電圧）の信号を出力し、その信号が入力されたゲートドライバ１１７がツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３のゲート電極の電圧を上げてツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３をオン状態にする。
　逆に、Ｈ端子の電圧がＬ端子の電圧より高くなると、コンパレータ１１６は低電圧（若しくは高電圧）の信号を出力し、その信号が入力されたゲートドライバ１１７がツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３のゲート電極の電圧を下げてツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３をオフ状態にする。
　すなわち、Ｈ端子とＬ端子の電圧の大小関係から、ツェナーダイオード内蔵ＭＯＳＦＥＴチップ１０３を自律的にオン・オフする。コンデンサ１０５はコンパレータ１１６とゲートドライバ１１７に電源電圧を供給する。
　図１０は、本発明のツェナーダイオード内蔵ＭＯＳＦＥＴ１０３を搭載した整流素子１００をオルタネータ（交流発電機）に適用した例を示す。オルタネータは、発電機で交流電力（電圧）を発生し、その交流電力（電圧）を整流装置で整流し、直流電力（電圧）を生成して出力するものである。
　図１０では、整流素子１００を６個用いた３相全波整流の回路構成（４００）を示す。
正座の整流素子１００が３個と、図示はしていないが逆座の整流素子３個と、バッテリ４０１が備えられている。
　図１０に示すように、正座の整流素子と逆座の整流素子が直列に接続され、それぞれの接続点が３相交流のＵ相、Ｖ相、Ｗ相に接続されており、発電機からの交流を直流に変換し、バッテリ４０１に直流電力（電圧）を出力する。
　なお、本発明は上記した実施例に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施例は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施例の構成の一部を他の実施例の構成に置き換えることが可能であり、また、ある実施例の構成に他の実施例の構成を加えることも可能である。また、各実施例の構成の一部について、他の構成の追加・削除・置換をすることが可能である。
　１００…（オルタネータ用）整流素子、１０１…ベース電極、１０２…台座、１０３…ツェナーダイオード内蔵ＭＯＳＦＥＴチップ、１０４…制御ＩＣチップ、１０５…コンデンサ、１０７…リード電極、１０８…樹脂、１０９…接合材、１１０…コンデンサの高電圧側端子、１１１…コンデンサの低電圧側端子、１１５…ボンディングワイヤ、１１６…コンパレータ、１１７…ゲートドライバ、１１８…ダイオード、２０１…ｎ＋基板、２０２…ｎ－エピ層、２０３…ｐ型チャネル層、２０４…ｎ+ソース層、２０５…ｐ+コンタクト層、２０６…ｐ層、２０７…ｎ層、２０８…深いｐ層、２０９…フィールドストップ層（チャネルストッパ層）、２１０…トレンチゲート、２１１…ゲート酸化膜、２１２…ポリシリコン電極、２１３…トレンチ、２１４…層間絶縁膜、２２０…ソース電極、２２１…ドレイン電極、２２２…ガードリング、２３０…ツェナーダイオード（ＺＤ）、２４０…メッキ層、２４１…半田層、２４２…保護膜、２５０…銅ブロック、２６０…アクティブ領域、２６１…ゲートパッド、２６２…ソースセンスパッド、３００…内部パッケージ、３０２…ドレインフレーム、３０３，３０４…リードフレーム、３０５…樹脂、３０６…接合材、４００…３相全波整流回路、４０１…バッテリ

Claims (10)

  1. 　ツェナーダイオード内蔵ＭＯＳＦＥＴを備える半導体装置において、
    　ＭＯＳＦＥＴが動作するアクティブ領域と、
    　前記アクティブ領域よりも外側に配置され、チップ周辺部の耐圧を保持する周辺領域と、を備え、
    　前記アクティブ領域は、チップ中心部を含む第１の領域と、前記第１の領域よりも外側に配置される第２の領域と、を有し、
    　前記第１の領域の耐圧は、前記第２の領域の耐圧及び前記周辺領域の耐圧よりも低いことを特徴とする半導体装置。
  2. 　請求項１に記載の半導体装置において、
    　前記第１の領域の耐圧は、前記半導体装置にサージが発生し、前記第１の領域の温度が上昇し、前記第２の領域の温度よりも高くなった場合であっても、前記第２の領域の耐圧及び前記周辺領域の耐圧よりも低いことを特徴とする半導体装置。
  3. 　請求項１に記載の半導体装置において、
    　前記第１の領域及び前記第２の領域には複数の単位セルが配列されており、
    　前記第１の領域の単位セルの各々にはツェナーダイオードが設けられており、
    　前記ツェナーダイオードの耐圧は、前記第２の領域の耐圧及び前記周辺領域の耐圧よりも低いことを特徴とする半導体装置。
  4. 　請求項３に記載の半導体装置において、
    　第１導電型の第１半導体層と、
    　前記第１半導体層上に形成され、前記第１半導体層より不純物濃度の低い第１導電型の第２半導体層と、
    　前記第２半導体層上に形成された第２導電型の第３半導体層と、
    　前記第３半導体層を貫通し、前記第２半導体層に到達するトレンチゲートと、
    　前記第３半導体層上に形成された第１導電型の第４半導体層と、
    　前記第４半導体層を貫通し、前記第３半導体層に到達するコンタクトと、を有し、
    　前記ツェナーダイオードは、前記第２半導体層と前記第３半導体層の接合部の中心部に設けられることを特徴とする半導体装置。
  5. 　請求項４に記載の半導体装置において、
    　前記第２半導体層と第３半導体層の接合部の中心部近傍の前記第２半導体層内に、第１半導体型の第５半導体層を有し、
    　前記第２半導体層と第３半導体層の接合部の中心部近傍の前記第３半導体層内に、第２導電型の第６半導体層を有することを特徴とする半導体装置。
  6. 　請求項５に記載の半導体装置において、

    　前記第５半導体層の不純物濃度は前記第２半導体層の不純物濃度よりも高く、前記第６半導体層の不純物濃度は前記第３半導体層の不純物濃度よりも高いことを特徴とする半導体装置。
  7. 　請求項１に記載の半導体装置において、
    　前記半導体装置を覆う保護膜を有し、
    　前記第１の領域は、前記保護膜に設けられた開口部内に配置されることを特徴とする半導体装置。
  8. 　請求項７に記載の半導体装置において、
    　前記第１の領域は、前記開口部内に設けられた配線用の銅端子の直下にのみ配置されることを特徴とする半導体装置。
  9. 　オルタネータに用いられる整流素子において、
    　上面視で略円形の外周部と前記外周部内に収まる略円形の台座を有する第１の外部電極と、
    　前記台座上に配置され、樹脂封止された内部パッケージと、
    　前記内部パッケージを挟んで前記第１の外部電極とは反対側に配置された第２の外部電極と、
    を備え、
    　前記内部パッケージ内に、半導体装置と、
    　前記半導体装置のドレイン電極とソース電極の電圧または電流が入力され、当該入力された電圧または電流に基づいて、前記半導体装置のゲートを駆動する制御ＩＣチップと、　前記制御ＩＣチップに電源を供給するコンデンサと、
    　前記ドレイン電極と接続されたドレインフレームと、
    　前記ソース電極と接続された銅ブロックと、を有し、
    　前記ドレインフレーム及び前記銅ブロックの表面は前記樹脂に封止されることなく、前記内部パッケージ表面に露出しており、
    　前記ドレインフレーム及び前記銅ブロックのいずれか一方と前記第１の外部電極とが接合材を用いて電気的に接続され、
    　前記ドレインフレーム及び前記銅ブロックの他方と前記第２の外部電極とが接合材を用いて電気的に接続されており、
    　前記半導体装置は、請求項１から８のいずれか１項に記載の半導体装置であることを特徴とする整流素子。
  10. 　請求項９に記載の整流素子を備えることを特徴とするオルタネータ。
PCT/JP2020/037858 2019-10-24 2020-10-06 半導体装置及びそれを用いた整流素子、オルタネータ WO2021079735A1 (ja)

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