JP2015106609A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2015106609A JP2015106609A JP2013247145A JP2013247145A JP2015106609A JP 2015106609 A JP2015106609 A JP 2015106609A JP 2013247145 A JP2013247145 A JP 2013247145A JP 2013247145 A JP2013247145 A JP 2013247145A JP 2015106609 A JP2015106609 A JP 2015106609A
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- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor chip
- semiconductor device
- central region
- slit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】半導体チップと、半導体チップが配置される中央領域及び中央領域の周囲に隣接する外周領域を有するリードフレームと、リードフレームと半導体チップを固着するダイアタッチ材と、半導体チップを覆ってリードフレーム上に配置される封止樹脂とを備え、リードフレームの外周領域に、中央領域と外周領域との境界から外周領域の外縁に向かって旋回しながら放射状に延伸する複数のスリットが形成され、スリットの幅が中央領域から遠ざかるにつれて広くなるように形成されている。
【選択図】図1
Description
また、弾性率の低い封止樹脂40を使用することによって、リードフレーム20に生じた変位量に応じて封止樹脂40が変形しやすいようにする。これにより、半導体装置1の特性変動を更に抑制することができる。
上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
10…半導体チップ
11…電極
20…リードフレーム
21…搭載部
22…インナーリード
30…ダイアタッチ材
40…封止樹脂
50…スリット
60…ボンディングワイヤ
70…絶縁膜
80…ヒートシンク
200…搭載面
201…中央領域
202…外周領域
210…境界線
Claims (4)
- 半導体チップと、
前記半導体チップが配置される中央領域及び前記中央領域の周囲に隣接する外周領域を有するリードフレームと、
前記リードフレームと前記半導体チップを固着するダイアタッチ材と、
前記半導体チップを覆って前記リードフレーム上に配置される封止樹脂と
を備え、
前記リードフレームの前記外周領域に、前記中央領域と前記外周領域との境界から前記外周領域の外縁に向かって旋回しながら放射状に延伸する複数のスリットが形成され、前記スリットの幅が前記中央領域から遠ざかるにつれて広くなることを特徴とする半導体装置。 - 前記スリットが屈曲部を有することを特徴とする請求項1に記載の半導体装置。
- 前記スリットが曲線状であることを特徴とする請求項1に記載の半導体装置。
- 前記封止樹脂のヤング率が14Gpa以下であることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013247145A JP6081903B2 (ja) | 2013-11-29 | 2013-11-29 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013247145A JP6081903B2 (ja) | 2013-11-29 | 2013-11-29 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015106609A true JP2015106609A (ja) | 2015-06-08 |
JP6081903B2 JP6081903B2 (ja) | 2017-02-15 |
Family
ID=53436579
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013247145A Expired - Fee Related JP6081903B2 (ja) | 2013-11-29 | 2013-11-29 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP6081903B2 (ja) |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5834931A (ja) * | 1981-08-26 | 1983-03-01 | Toshiba Corp | 半導体装置 |
JPS60118252U (ja) * | 1984-01-18 | 1985-08-09 | 沖電気工業株式会社 | 樹脂封止半導体装置用リ−ドフレ−ム |
JPS63249341A (ja) * | 1987-04-06 | 1988-10-17 | Tomoegawa Paper Co Ltd | 半導体装置 |
JPH01147836A (ja) * | 1987-12-03 | 1989-06-09 | Shinko Electric Ind Co Ltd | 半導体装置 |
JPH01227462A (ja) * | 1988-03-08 | 1989-09-11 | Matsushita Electron Corp | リードフレーム |
JPH05114688A (ja) * | 1991-10-23 | 1993-05-07 | Hitachi Ltd | 半導体装置およびその製造方法並びにそれに使用されるリードフレーム |
JPH0878605A (ja) * | 1994-09-01 | 1996-03-22 | Hitachi Ltd | リードフレームおよびそれを用いた半導体集積回路装置 |
JPH08204106A (ja) * | 1995-01-25 | 1996-08-09 | Nec Corp | 樹脂封止型半導体装置 |
JPH09289269A (ja) * | 1996-04-19 | 1997-11-04 | Hitachi Ltd | 半導体装置 |
JPH10313090A (ja) * | 1997-05-14 | 1998-11-24 | Hitachi Ltd | リードフレームおよびそれを用いた半導体装置 |
JP2002198486A (ja) * | 2000-12-25 | 2002-07-12 | Kyocera Corp | 半導体装置 |
JP2002217358A (ja) * | 2001-01-12 | 2002-08-02 | Kyocera Corp | 半導体装置 |
JP2004312053A (ja) * | 2004-08-09 | 2004-11-04 | Renesas Technology Corp | 半導体装置 |
JP2007311579A (ja) * | 2006-05-19 | 2007-11-29 | Matsushita Electric Ind Co Ltd | リードフレームおよびこれを使用した半導体装置 |
-
2013
- 2013-11-29 JP JP2013247145A patent/JP6081903B2/ja not_active Expired - Fee Related
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5834931A (ja) * | 1981-08-26 | 1983-03-01 | Toshiba Corp | 半導体装置 |
JPS60118252U (ja) * | 1984-01-18 | 1985-08-09 | 沖電気工業株式会社 | 樹脂封止半導体装置用リ−ドフレ−ム |
JPS63249341A (ja) * | 1987-04-06 | 1988-10-17 | Tomoegawa Paper Co Ltd | 半導体装置 |
JPH01147836A (ja) * | 1987-12-03 | 1989-06-09 | Shinko Electric Ind Co Ltd | 半導体装置 |
JPH01227462A (ja) * | 1988-03-08 | 1989-09-11 | Matsushita Electron Corp | リードフレーム |
JPH05114688A (ja) * | 1991-10-23 | 1993-05-07 | Hitachi Ltd | 半導体装置およびその製造方法並びにそれに使用されるリードフレーム |
US5874773A (en) * | 1994-09-01 | 1999-02-23 | Hitachi, Ltd. | Lead frame having a supporting pad with a plurality of slits arranged to permit the flow of resin so as to prevent the occurrence of voids |
JPH0878605A (ja) * | 1994-09-01 | 1996-03-22 | Hitachi Ltd | リードフレームおよびそれを用いた半導体集積回路装置 |
JPH08204106A (ja) * | 1995-01-25 | 1996-08-09 | Nec Corp | 樹脂封止型半導体装置 |
US5712507A (en) * | 1995-01-25 | 1998-01-27 | Nec Corporation | Semiconductor device mounted on die pad having central slit pattern and peripheral slit pattern for absorbing |
JPH09289269A (ja) * | 1996-04-19 | 1997-11-04 | Hitachi Ltd | 半導体装置 |
JPH10313090A (ja) * | 1997-05-14 | 1998-11-24 | Hitachi Ltd | リードフレームおよびそれを用いた半導体装置 |
JP2002198486A (ja) * | 2000-12-25 | 2002-07-12 | Kyocera Corp | 半導体装置 |
JP2002217358A (ja) * | 2001-01-12 | 2002-08-02 | Kyocera Corp | 半導体装置 |
JP2004312053A (ja) * | 2004-08-09 | 2004-11-04 | Renesas Technology Corp | 半導体装置 |
JP2007311579A (ja) * | 2006-05-19 | 2007-11-29 | Matsushita Electric Ind Co Ltd | リードフレームおよびこれを使用した半導体装置 |
Also Published As
Publication number | Publication date |
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JP6081903B2 (ja) | 2017-02-15 |
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