JP2015095482A - 半導体部品上へのマイクロバンプの作製方法 - Google Patents

半導体部品上へのマイクロバンプの作製方法 Download PDF

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JP2015095482A
JP2015095482A JP2013232359A JP2013232359A JP2015095482A JP 2015095482 A JP2015095482 A JP 2015095482A JP 2013232359 A JP2013232359 A JP 2013232359A JP 2013232359 A JP2013232359 A JP 2013232359A JP 2015095482 A JP2015095482 A JP 2015095482A
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openings
layer
passivation layer
opening
contact
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JP2013232359A
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JP2015095482A5 (enExample
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ミカエル・ドゥタル
Detalle Mikael
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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Priority to JP2013232359A priority Critical patent/JP2015095482A/ja
Priority to US14/092,796 priority patent/US9263408B2/en
Publication of JP2015095482A publication Critical patent/JP2015095482A/ja
Publication of JP2015095482A5 publication Critical patent/JP2015095482A5/ja
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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TWI599276B (zh) * 2015-06-26 2017-09-11 矽創電子股份有限公司 電子元件與製造方法
CN108206140B (zh) * 2016-12-19 2020-11-24 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法、电子装置
US10566300B2 (en) * 2018-01-22 2020-02-18 Globalfoundries Inc. Bond pads with surrounding fill lines
US10834818B2 (en) * 2018-11-05 2020-11-10 Ngk Spark Plug Co., Ltd. Wiring board
US11955423B2 (en) * 2020-09-29 2024-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11855028B2 (en) * 2021-01-21 2023-12-26 Taiwan Semiconductor Manufacturing Hybrid micro-bump integration with redistribution layer
KR20250065844A (ko) * 2022-09-02 2025-05-13 에스케이 하이닉스 낸드 프로덕트 솔루션즈 코포레이션 다이에서 응력을 감소시키고 표면 접착을 개선하기 위한 시스템들 및 방법들

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