JP2015095482A5 - - Google Patents

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Publication number
JP2015095482A5
JP2015095482A5 JP2013232359A JP2013232359A JP2015095482A5 JP 2015095482 A5 JP2015095482 A5 JP 2015095482A5 JP 2013232359 A JP2013232359 A JP 2013232359A JP 2013232359 A JP2013232359 A JP 2013232359A JP 2015095482 A5 JP2015095482 A5 JP 2015095482A5
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JP
Japan
Prior art keywords
openings
passivation layer
layer
semiconductor package
microbump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2013232359A
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English (en)
Japanese (ja)
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JP2015095482A (ja
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Publication date
Application filed filed Critical
Priority to JP2013232359A priority Critical patent/JP2015095482A/ja
Priority claimed from JP2013232359A external-priority patent/JP2015095482A/ja
Priority to US14/092,796 priority patent/US9263408B2/en
Publication of JP2015095482A publication Critical patent/JP2015095482A/ja
Publication of JP2015095482A5 publication Critical patent/JP2015095482A5/ja
Pending legal-status Critical Current

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JP2013232359A 2013-11-08 2013-11-08 半導体部品上へのマイクロバンプの作製方法 Pending JP2015095482A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013232359A JP2015095482A (ja) 2013-11-08 2013-11-08 半導体部品上へのマイクロバンプの作製方法
US14/092,796 US9263408B2 (en) 2013-11-08 2013-11-27 Method for producing microbumps on a semiconductor component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013232359A JP2015095482A (ja) 2013-11-08 2013-11-08 半導体部品上へのマイクロバンプの作製方法

Publications (2)

Publication Number Publication Date
JP2015095482A JP2015095482A (ja) 2015-05-18
JP2015095482A5 true JP2015095482A5 (enExample) 2016-12-22

Family

ID=53043082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013232359A Pending JP2015095482A (ja) 2013-11-08 2013-11-08 半導体部品上へのマイクロバンプの作製方法

Country Status (2)

Country Link
US (1) US9263408B2 (enExample)
JP (1) JP2015095482A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520333B1 (en) * 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof
TWI599276B (zh) * 2015-06-26 2017-09-11 矽創電子股份有限公司 電子元件與製造方法
CN108206140B (zh) * 2016-12-19 2020-11-24 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法、电子装置
US10566300B2 (en) * 2018-01-22 2020-02-18 Globalfoundries Inc. Bond pads with surrounding fill lines
US10834818B2 (en) * 2018-11-05 2020-11-10 Ngk Spark Plug Co., Ltd. Wiring board
US11955423B2 (en) * 2020-09-29 2024-04-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11855028B2 (en) * 2021-01-21 2023-12-26 Taiwan Semiconductor Manufacturing Hybrid micro-bump integration with redistribution layer
KR20250065844A (ko) * 2022-09-02 2025-05-13 에스케이 하이닉스 낸드 프로덕트 솔루션즈 코포레이션 다이에서 응력을 감소시키고 표면 접착을 개선하기 위한 시스템들 및 방법들

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06177136A (ja) * 1992-10-09 1994-06-24 Nippondenso Co Ltd バンプ電極をもつ回路装置
JP2697592B2 (ja) * 1993-12-03 1998-01-14 日本電気株式会社 半導体装置のパッド構造
TW448524B (en) 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
KR20010004529A (ko) 1999-06-29 2001-01-15 김영환 웨이퍼 레벨 패키지 및 그의 제조 방법
JP2002217225A (ja) * 2001-01-17 2002-08-02 Sanyo Electric Co Ltd バンプ電極の形成方法
JP2003318211A (ja) * 2002-04-24 2003-11-07 Sharp Corp 半導体装置
US6825541B2 (en) 2002-10-09 2004-11-30 Taiwan Semiconductor Manufacturing Co., Ltd Bump pad design for flip chip bumping
US8405220B1 (en) 2005-03-23 2013-03-26 Marvell International Ltd. Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types
US20080284009A1 (en) * 2007-05-16 2008-11-20 Heikyung Min Dimple free gold bump for drive IC
US7767496B2 (en) * 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
JP2009302340A (ja) * 2008-06-13 2009-12-24 Nec Electronics Corp 半導体装置の製造方法
KR100979497B1 (ko) 2008-06-17 2010-09-01 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
KR101534682B1 (ko) 2009-03-13 2015-07-08 삼성전자주식회사 범프에 스틱을 구비하는 반도체 장치
US8405211B2 (en) 2009-05-08 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Bump pad structure

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