CN107026138A - 晶圆级芯片级封装及其形成方法 - Google Patents

晶圆级芯片级封装及其形成方法 Download PDF

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Publication number
CN107026138A
CN107026138A CN201611091100.5A CN201611091100A CN107026138A CN 107026138 A CN107026138 A CN 107026138A CN 201611091100 A CN201611091100 A CN 201611091100A CN 107026138 A CN107026138 A CN 107026138A
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China
Prior art keywords
layer
pad
protective layer
wafer stage
conductive
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CN201611091100.5A
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Inventor
季彦良
熊明仁
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MediaTek Inc
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MediaTek Inc
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Publication of CN107026138A publication Critical patent/CN107026138A/zh
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Abstract

本发明公开了晶圆级芯片级封装及其形成方法，其中，所述晶圆级芯片级封装包括：半导体结构；在所述半导体结构上形成的第一焊盘；在所述半导体结构和所述第一焊盘上形成的保护层，其中，所述保护层暴露所述第一焊盘的多个部分；在所述保护层和所述第一焊盘被所述保护层所暴露的部分上形成的导电再分布层；在所述保护层和所述导电再分布层上形成的平面层，所述平面层暴露所述导电再分布层的一部分；在所述平面层和所述导电再分布层被所述平面层所暴露的部分上形成的凸块下金属层；以及在所述凸块下金属层上形成的导电凸块。本发明提供的晶圆级芯片级封装具有较小的尺寸。

Description

晶圆级芯片级封装及其形成方法
【技术领域】
本发明涉及半导体技术领域，尤其涉及晶圆级芯片级封装及其形成方法。
【背景技术】
使电子产品小、轻和具有高性能的愿望已经发展为使电子部件小、轻以及具有高性能。这样的愿望使得各种封装技术的制程的发展、以及半导体设计和制造相关的技术的发展。封装技术的代表性实施例包括球栅阵列(Ball Grid Array，BGA)、倒装芯片(flip-chip)、基于区域阵列和表面贴装(surface-mount)封装的芯片级封装(Chip ScalePackage，CSP)。
在上述的封装技术中，芯片级封装为可使封装小到与研发的真实芯片一样的大小的封装技术。特别地，晶圆级芯片级封装(Wafer-Level Chip Scale Package，WLCSP)中，在晶圆级执行封装以便每个芯片的成本可显著降低。特别地，WLCSP包括再分布层(Redistribution Layer，RDL)布线痕迹、凸块下金属(Under Bump Metallurgy，UBM)层用于形成凸块，以及保护层用于保护电路。
【发明内容】
本发明提供在晶圆级芯片级封装及其形成方法。可提供具有较小尺寸的晶圆级芯片级封装。
本发明实施例所提供的晶圆级芯片级封装包括：半导体结构；在所述半导体结构上形成的第一焊盘；在所述半导体结构和所述第一焊盘上形成的保护层，其中，所述保护层暴露所述第一焊盘的多个部分；在所述保护层和所述第一焊盘被所述保护层所暴露的部分上形成的导电再分布层；在所述保护层和所述导电再分布层上形成的平面层，所述平面层暴露所述导电再分布层的一部分；在所述平面层和所述导电再分布层被所述平面层所暴露的部分上形成的凸块下金属层；以及在所述凸块下金属层上形成的导电凸块。
本发明实施例所提供的用于形成晶圆级芯片级封装的方法，包括：提供上面形成有第一焊盘的半导体结构；在所述半导体结构和所述第一焊盘上形成保护层，其中，所述保护层暴露所述第一焊盘的多个部分；在所述保护层和所述第一焊盘被所述保护层所暴露的多个部分上形成导电再分布层；在所述保护层和所述导电再分布层上形成平面层，所述平面层暴露所述导电再分布层的一部分；在所述导电再分布层被所述平面层所暴露的部分上形成凸块下金属层；以及在所述凸块下金属层上形成导电凸块。
基于上述技术方案，本发明实施例可提供具有较小尺寸的晶圆级芯片级封装。
【附图说明】
本发明可通过阅读随后的细节描述和参考附图所举的实施例被更全面地理解，其中：
图1为根据本发明的一个实施例的晶圆级芯片级封装(WLCSP)的截面示意图。
图2-图8为依据本发明的一个实施例的形成晶圆级芯片级封装的方法截面示意图。
图9为本发明的另一个实施例的WLCSP的截面示意图。
图10为本发明的另一个实施例的WLCSP的截面示意图。
【具体实施方式】
在说明书及后续的权利要求当中使用了某些术语来指称特定的组件。本领域技术人员应可理解，硬件制造商可能会用不同的名称来称呼同一个组件。本文件并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在接下来的说明书及权利要求中，术语“包含”及“包括”为一开放式的用语，故应解释成“包含但不限制于”。此外，“耦接”一词在此包含直接及间接的电性互连接手段。因此，如果一个装置耦接于另一个装置，则代表该一个装置可直接电性互连接于该另一个装置，或通过其它装置或互连接手段间接地电性互连接至该另一个装置。
图1为根据本发明的一个实施例的晶圆级芯片级封装(WLCSP)的截面示意图。如图1所示，WLCSP包括半导体结构100、焊盘102、保护层104、第一平面层106、第二平面层112、导电再分布层110、凸块下金属层116以及导电凸块118。
此处，为简化图示，将半导体结构100表示为包括第一平坦的上表面的结构。请注意，半导体结构100可为上面形成有多个半导体装置和互连接结构(均未图示)的晶圆级半导体结构。半导体结构100上形成的半导体装置例如可为：主动装置，例如晶体管或二极管；或者，被动装置，例如电容器、电阻器和导体。半导体结构100中的互连接结构可包括由多个层间介电层支持和隔离的多层金属结构。在本实施例中，半导体结构100的一部分图示为WLCSP。
请参考图1，在半导体结构100的一部分上形成焊盘102，且焊盘102可与半导体结构100中形成的电路的一个互连接结构(未图示)电连接。在半导体结构100上先后形成保护层104和第一平面层106，保护层104和第一平面层106分别部分覆盖焊盘102的一些部分。在第一平面层106中形成开口108以暴露焊盘102的一部分，在第一平面层106的一些部分和所述开口中一致地形成导电再分布层110以覆盖焊盘102被开口108暴露的那一部分。在第一平面层106和导电再分布层110上形成第二平面层112，在第二平面层112中形成开口114以暴露导电再分布层110的一部分。在第二平面层112的一部分和第二平面层112暴露的导电再分布层110上形成凸块下金属层116，在凸块下金属层116上形成导电凸块118。
在本实施例中，焊盘102可包括导电材料，例如，铝，保护层104可包括介电材料，例如，二氧化硅、氧化硅，或者它们的组合物。第一平面层106和第二平面层112可包括介电材料，例如，氧化硅、二氧化硅、或聚合物。在一个实施例中，适合作为第一平面层106和第二平面层112的聚合物可为，例如，聚酰亚胺，聚苯并恶唑，或苯并环丁烯。导电再分布层110可包括导电材料例如，铜、镍或铝。凸块下金属层116可包括导电材料，例如，金属或金属合金，例如，镍层，银层，铝层，铜层或它们的合金，或者掺杂多晶硅，单晶硅或导电玻璃的材料。此外，难溶金属材料，例如，钛，钼，铬或钛钨层可单独用于形成凸块下金属层，或者可与其他金属层一起形成凸块下金属层。通常，第一平面层106的厚度C约为5微米-7.5微米，且位于焊盘102上的第一平面层的阶高太高，以至于第一平面层106上形成的开口108为较大尺寸(例如，约22微米-30微米)的单个开口。因此，在第一平面层106的一部分和开口108暴露的那部分焊盘102上所形成的导电再分布层110包括靠近开口108的台阶状的台阶部A和从开口114延伸出且覆盖第一平面层106的平面状的平面部B。此外，第二平面层112中形成的开口114暴露导电再分布层110的平面部B的一部分，以至于凸块下金属层116可一致地设置在第二平面层112的一部分和开口114所暴露的导电再分布层110的平面部B上。
图1中示出的WLCSP中，由于提供第一平面层106，且第一平面层106的厚度C约为5微米-7.5微米，因此靠近开口108的第一平面层106的台阶高度太大而不能使开口108很小。因此，导电再分布层110靠近开口108的部分形成为台阶状，且凸块下金属层116及凸块下金属层116上所形成的焊接凸块118仅能位于至开口108延伸出的且位于第一平面层106上的导电再分布层110的平面部B上。因此，图1中示出的WLCSP占据的空间非常大，由于当前的趋势是朝着进一步减小WLCSP内部的集成电路的尺寸，因此，这样的空间不是所期望的。
因此，图2-图8为根据本发明的另一个实施例的截面示意图，这些截面示意图示出具有减小的尺寸的WLCSP的形成方法。
请参考图2，提供一个半导体结构200，在半导体结构200的一部分上形成有焊盘202。接着，通过化学气相沉积工艺(未图示)在半导体结构200和第一焊盘204上一致地形成保护层204。由于在半导体结构200和第一焊盘202上一致地形成保护层204，因此，保护层204具有一个非平面的上表面位于半导体结构200上。在一个实施例中，保护层204位于半导体结构200上的部分的厚度T约为1微米-6微米。
在一个实施例中，半导体结构200与图1所示的半导体结构100相同，且保护层204和焊盘202分别与图1中所示的保护层104和焊盘102相同。
请参考图3，执行平面化过程206将保护层204的上表面弄平，并减小保护层204的厚度，因此，在半导体结构200和焊盘202上留下具有平的上表面的保护层204a。此时，位于半导体结构200上的保护层204a具有减小后的厚度T’，T’约为1微米-6微米。作为举例，平面化步骤206可为气相沉积工艺，或回蚀刻工艺。
请参考图4，接着在图3所示的保护层204a上执行图案化过程208以仅在保护层204a位于焊盘202之上的部分形成多个开口210。因此，焊盘202的多个部分通过开口210暴露。每一个开口210具有维度W，例如，宽度，W约大于或等于2微米，在俯视图中(未图示)，开口210可为圆形、条形或多边形。在一个实施例中，图案化过程208可包括光刻和蚀刻步骤(未图示)，其中，蚀刻步骤使用适宜的图案面罩(未图示)作为蚀刻面罩。
请参考图5，在保护层204a位于焊盘202上的部分上接着形成图案化的导电再分布层212。图案化的导电再分布层212包括多个填充在保护层204a中形成的开口210的中的第一部分212a和形成于保护层204a的平的上表面上和开口210上的第二部分212b。因此，如图5所示，图案化的导电再分布层212也具有几乎平的上表面。形成图案化的导电再分布层212时，可首先在保护层204a和开口210中形成导电再分布层212，然后通过包括光刻和蚀刻步骤(包含适宜的图案面罩(未图示)作为蚀刻面罩)的图案化过程(未图示)对导电再分布层212进行图案化。用于形成图案化的导电再分布层212的导电材料可与用于形成图1中所示的导电再分布层110的材料相同，导电再分布层212位于保护层204a上的厚度约为4微米-9微米。
请参考图6，在图5所示的结构的上表面上形成平面层214，然后在平面层214的一部分上形成开口216以暴露图案化的导电再分布层212的一部分。可通过化学气相沉积工艺或旋涂法工艺形成平面层214，并可使用包括光刻和蚀刻步骤(包含适宜的图案面罩(未图示)作为蚀刻面罩)的图案化过程(未图示)进行图案化。用于形成平面层214的材料可与用于形成图1中所示的第一平面层106的材料相同，平面层214的厚度可约为7.5微米-10微米，比图案化的导电再分布层212的厚度大。
请参考图7，在图案化的导电再分布层212被开口216暴露的那部分和平面层214邻近开口216的部分上接着形成凸块下金属层218。形成凸块下金属层218时，可通过化学气相沉积工艺或电镀工艺在图6所示的结构上形成导电材料层，然后通过包括光刻和蚀刻步骤(包含适宜的图案面罩(未图示)作为蚀刻面罩)的图案化过程(未图示)进行图案化。用于形成凸块下金属层218的材料可与用于形成图1所示的凸块下金属层116的材料相同，且凸块下金属层218的厚度约为4微米-9微米。
请参考图8，通过传统的焊球凸块形成工艺在凸块下金属层218上形成导电凸块220。由于图案化的导电再分布层212现在提供为几乎平的上表面而不是台阶状的配置，凸块下金属层218和导电凸块220也可一致地和稳固地设置在图案化的导电再分布层212上。此外，由于图案化的导电再分布层212直接设置在焊盘202上，导电凸块220和凸块下金属层218也可直接设置在焊盘202上，以便获得具有减小的尺寸的WLCSP结合结构。
此外，由于图8所示的WLCSP仅使用一个平面层214，因此图8中的WLCSP相较于图1中使用两个平面层的WLCSP更容易制造。
除图8所示的典型的实施例之外，图9为本发明的另一个实施例的WLCSP的截面示意图。此处，图9所示的WLCSP是由图8所示的WLCSP改变而形成的，在图9中相似的组件用图8中相同的参考符号进行表示，下面将仅讨论图8和图9中的WLCSP的不同之处。
请参考图9，具有平的上表面的图案化的导电再分布层212的第二部分212b不再如图8所示那样仅形成于焊盘202上，而是进一步延伸至未覆盖焊盘202的保护层204a的一部分上，以提供布线功能(line-routing function)，以便凸块下金属层218和导电凸块220可形成于图案化的导电再分布层212未覆盖焊盘202的第二部分212b的一部分上。类似地，由于图9中所示的WLCSP仅使用一个平面层214，图9中的WLCSP相较于图1中使用两个平面层的WLCSP更容易制造。
除图9所示的典型实施例之外，图10为本发明的另一个实施例的WLCSP的截面示意图。此处，图10所示的WLCSP是由图9所示的WLCSP改变而形成的，在图10中相似的组件用相同的参考符号进行表示，下面将仅讨论图9和图10中的WLCSP的不同之处。
请参考图10，本实施例所提供的半导体结构200包括设置在其上的两个隔离的焊盘202，且保护层204a和保护层204a中形成的开口210位于每一个焊盘202上的相同位置处。在本实施例中，图案化的导电再分布层212包括形成于开口210中的第一部分212a，其中，开口210位于每一个202上的保护层204a上，图案化的导电再分布层212还包括位于焊盘202之间的平的保护层204上的第二部分212b。凸块下金属层218和导电凸块220形成于其中一个焊盘202上的图案化的导电再分布层212的第二部分212b的一部分上。
类似地，当前提供的图案化的导电再分布层212几乎具有平的上表面，因此，凸块下金属层218和导电凸块220可稳固地形成于图案化的导电再分布层212上。此外，由于图案化的导电再分布层212上直接形成于焊盘202上，凸块下金属层218和导电凸块220也可直接形成于其中一个焊盘202上，以便获得具有减小的尺寸的WLCSP结合结构。
进一步，由于图10中所示的WLCSP仅使用一个平面层214，图10中的WLCSP相较于图1中使用两个平面层的WLCSP更容易制造。
权利要求书中用以修饰元件的“第一”、“第二”等序数词的使用本身未暗示任何优先权、优先次序、各元件之间的先后次序、或所执行方法的时间次序，而仅用作标识来区分具有相同名称(具有不同序数词)的不同元件。
本发明虽以较佳实施例揭露如上，然其并非用以限定本发明的范围，任何本领域技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰，因此本发明的保护范围当视权利要求所界定者为准。

Claims (25)

1.一种晶圆级芯片级封装，其特征在于，包括：
半导体结构；
在所述半导体结构上形成的第一焊盘；
在所述半导体结构和所述第一焊盘上形成的保护层，其中，所述保护层暴露所述第一焊盘的多个部分；
在所述保护层和所述第一焊盘被所述保护层所暴露的部分上形成的导电再分布层；
在所述保护层和所述导电再分布层上形成的平面层，所述平面层暴露所述导电再分布层的一部分；
在所述平面层和所述导电再分布层被所述平面层所暴露的部分上形成的凸块下金属层；以及
在所述凸块下金属层上形成的导电凸块。
2.如权利要求1所述的晶圆级芯片级封装，其特征在于，所述半导体结构和所述第一焊盘上形成的所述保护层具有平的上表面。
3.如权利要求1所述的晶圆级芯片级封装，其特征在于，在所述第一焊盘被所述保护层暴露的部分上所形成的所述导电再分布层具有几乎平的上表面。
4.如权利要求1所述的晶圆级芯片级封装，其特征在于，所述保护层包括介电材料。
5.如权利要求1所述的晶圆级芯片级封装，其特征在于，所述平面层包括聚酰亚胺，聚苯并恶唑，或苯并环丁烯。
6.如权利要求1所述的晶圆级芯片级封装，其特征在于，所述凸块下金属层形成于所述导电再分布层一部分上，所述导电再分布层的所述一部分位于所述第一焊盘被所述保护层暴露的部分上。
7.如权利要求1所述的晶圆级芯片级封装，其特征在于，所述凸块下金属层形成于所述导电再分布层一部分上，所述导电再分布层的所述一部分位于所述第一焊盘未被所述保护层暴露的部分上。
8.如权利要求1所述的晶圆级芯片级封装，其特征在于，从俯视图观察，所述第一焊盘被所述保护层暴露的多个部分分别具有大于或等于2微米的宽度。
9.如权利要求1所述的晶圆级芯片级封装，其特征在于，所述第一焊盘被所述保护层暴露的多个部分分别为圆形、条形或多边形。
10.如权利要求1所述的晶圆级芯片级封装，其特征在于，还包括形成于所述半导体结构的另一部分上的第二焊盘。
11.如权利要求10所述的晶圆级芯片级封装，其特征在于，所述保护层形成于所述第二焊盘上且暴露所述第二焊盘的多个部分。
12.如权利要求11所述的晶圆级芯片级封装，其特征在于，所述导电再分布层形成于所述第二焊盘被所述保护层暴露的多个部分上，且所述导电再分布层包括几乎平的上表面。
13.如权利要求12所述的晶圆级芯片级封装，其特征在于，所述凸块下金属层形成于所述导电再分布层一部分上，所述导电再分布层的所述一部分位于所述第一焊盘被所述保护层暴露的部分上或所述第二焊盘被所述保护层暴露的部分上。
14.一种用于形成晶圆级芯片级封装的方法，其特征在于，包括
提供上面形成有第一焊盘的半导体结构；
在所述半导体结构和所述第一焊盘上形成保护层，其中，所述保护层暴露所述第一焊盘的多个部分；
在所述保护层和所述第一焊盘被所述保护层所暴露的多个部分上形成导电再分布层；
在所述保护层和所述导电再分布层上形成平面层，所述平面层暴露所述导电再分布层的一部分；
在所述导电再分布层被所述平面层所暴露的部分上形成凸块下金属层；以及
在所述凸块下金属层上形成导电凸块。
15.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，所述在所述半导体结构和所述第一焊盘上形成保护层的步骤，包括：
在所述半导体结构和所述第一焊盘上一致地形成所述保护层；
执行平面化的过程以将所述保护层位于所述第一焊盘上的一部分移除，以便平面化所述半导体结构和所述第一焊盘上的所述保护层的上表面；以及
在所述平面化的过程之后，在所述保护层中形成多个第一开口以暴露所述第一焊盘的多个部分。
16.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，所述在所述保护层和所述导电再分布层上形成所述平面层以暴露所述导电再分布层的一部分的步骤，包括：
在所述保护层和所述导电再分布层上形成所述平面层；以及
在所述平面层的一部中形成开口以暴露所述导电再分布层的所述一部分。
17.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，所述半导体结构和所述第一焊盘上所形成的所述保护层具有平的上表面。
18.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，在所述第一焊盘上形成且被所述保护层所暴露的导电再分布层具有几乎平的上表面。
19.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，从俯视图观察，所述第一焊盘被所述保护层暴露的多个部分分别具有大于或等于2微米的宽度。
20.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，所述第一焊盘被所述保护层暴露的多个部分分别为圆形、条形或多边形。
21.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，还包括形成于所述半导体结构的另一部分上的第二焊盘。
22.如权利要求14所述的形成晶圆级芯片级封装的方法，其特征在于，所述保护层形成于所述第二焊盘上且暴露所述第二焊盘的多个部分。
23.如权利要求22所述的形成晶圆级芯片级封装的方法，其特征在于，所述导电再分布层形成于所述第二焊盘被所述保护层暴露的多个部分上，且所述导电再分布层包括几乎平的上表面。
24.如权利要求22所述的形成晶圆级芯片级封装的方法，其特征在于，所述凸块下金属层形成于所述导电再分布层一部分上，所述导电再分布层的所述一部分位于所述第一焊盘被所述保护层暴露的部分上或所述第二焊盘被所述保护层暴露的部分上。
25.如权利要求22所述的形成晶圆级芯片级封装的方法，其特征在于，所述平面层包括介电材料，且所述平面层包括聚酰亚胺，聚苯并恶唑，或苯并环丁烯。
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