JP2014521229A - Iii−vエピタキシャル層を成長させるための方法 - Google Patents
Iii−vエピタキシャル層を成長させるための方法 Download PDFInfo
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Abstract
Description
基板(例えば、Si、SiGe、Ge、基板およびそれらの組み合わせ、好ましくはSi基板(例えば<111>Si基板))を準備すること、
上記基板上にエピタキシャルな半導体のバッファ層(例えばIII−Vバッファ層(例えばIII−窒化物層))を設けて、当該エピタキシャルな半導体のバッファ層および基板の間に(例えば導電性の)界面を形成すること、または当該バッファ層を設けることによって当該界面を得ること、ならびに、
上記界面における電流を遮断するために、当該界面にある基板に1つ以上の局所的な電気絶縁を形成することを包含している。そのような絶縁は、シャロートレンチアイソレーション(STI)、LOCOS、不純物インプランテーション、ディープトレンチエッチングおよびこれらの組み合わせであり得る。上記基板における上記1つ以上の局所的な絶縁は、規則的なパターンに形成され得る。
基板(例えば、Si、SiGe、Ge、絶縁体上のSi、絶縁体上のGe基板およびそれらの組み合わせ、好ましくはSi基板(例えば<111>Si基板))を準備すること;
上記基板上にエピタキシャルな半導体のバッファ層(例えばIII−Vバッファ層(例えばIII−窒化物層))を設けることによって、当該バッファ層および上記基板の間に導電性界面を得ること;
上記導電性界面における電流を遮断するために、上記導電性界面および部分的に上記基板に、1つ以上の局所的な電気絶縁を形成すること;ならびに、
上記1つ以上の局所的な電気絶縁を、少なくとも1つの上記局所的な電気絶縁が当該素子の高圧の端子および低圧の端子の間に配置されるように、素子と位置合わせすることを包含している。
基板(例えば、Si、SiGe、Ge、基板およびそれらの組み合わせ、好ましくはSi基板(例えば<111>Si基板))、
上記基板上にあるバッファ層(例えばIII−Vバッファ層(例えばIII−窒化物層))を備えており、
上記バッファ層は、当該バッファおよび上記基板の間に界面を有しており、
導電性パスは、1つ以上の電気絶縁(例えば、シャロートレンチアイソレーション(STI)、LOCOS、不純物インプランテーション、ディープトレンチエッチングおよびこれらの組み合わせ)によって遮断されていることを特徴とし、上記基板およびバッファ層の間の上記界面に存在している。
(b)上記1つ以上の局所的な電気絶縁の間の間隙は、0.2μm〜20μmの幅、より好ましくは0.5μm〜10μmの幅、より一層好ましくは1μm〜5μmの幅であるか、および/または、
(c)上記1つ以上の局所的な電気絶縁の規則的なパターンの周期は、ゲートからドレインまでの距離より小さく、当該周期および距離は、同一平面にあり、好ましくは実質的に同一方向にある、ことが好ましい。
基板(例えば、Si、SiGe、Ge、基板およびそれらの組み合わせ、好ましくはSi基板(例えば<111>Si基板))を準備すること、
上記基板上にエピタキシャルな半導体のバッファ層(例えばIII−Vバッファ層(例えばIII−窒化物層))を設け、このようにして界面を形成すること;および、
上記界面にある基板に1つ以上の局所的な電気絶縁(例えば、シャロートレンチアイソレーション(STI)、LOCOS、不純物インプランテーション、ディープトレンチエッチングおよびこれらの組み合わせ)を形成することを包含している。基板における1つ以上の局所的な絶縁は、規則的なパターンに形成され得る。
基板(例えば、Si、SiGe、Ge、基板およびそれらの組み合わせ、好ましくはSi基板(例えば<111>Si基板))、
上記基板上にあるバッファ層(例えばIII−Vバッファ層(例えばIII−窒化物層))を備えており、
上記バッファ層は、当該バッファおよび上記基板の間に界面を有しており、
導電性パスは、上記基板およびバッファ層の間の上記界面に存在しており、上記界面に流れる電流を妨げるために当該界面に形成されている1つ以上の電気絶縁(例えば、シャロートレンチアイソレーション(STI)、LOCOS、不純物インプランテーション、ディープトレンチエッチングおよびこれらの組み合わせ)によって遮断されていることを特徴とする。
(b)上記1つ以上の局所的な電気絶縁の間の間隙は、0.2μm〜20μmの幅、より好ましくは0.5μm〜10μmの幅、より一層好ましくは1μm〜5μmの幅であるか、および/または、
(c)上記1つ以上の局所的な電気絶縁の規則的なパターンの周期は、ゲートからドレインまでの距離より小さく、当該周期および距離は、同一平面にあり、好ましくは実質的に同一方向にある、ことが好ましい。
感受性の生物学的要素、生物学的に生成された材料または生物模倣物;
生物学的な要素との分析物の相互作用から生じる信号を他の信号に変換する変換器または検出器の構成要素;ならびに、
付属する電子部品またはシグナルプロセッサからなる。
図1は、従来技術に係る半導体素子の断面図である。
図2は、本発明に係る半導体素子を製造する方法の断面図である。
図3a〜bは、本発明に係る半導体素子を製造する方法の断面図である。
図4〜7および図8a〜dは、本発明に係る半導体素子を製造する方法の断面図である。
図9a〜fは、本発明に係る半導体素子を製造する方法の平面図である。
本発明は、特定の実施態様に関して図面を参照して説明されているが、本発明は、それらに限定されることなく、特許請求の範囲のみによって限定される。説明されている図面は、概略に過ぎず、非限定的である。図面において、いくつかの要素の大きさは、拡大されており、例示を目的とする大きさを描写していない。寸法および相対的な寸法は、本発明の実施に対する実際の縮尺と対応していない。
本発明の一例において、基板(層1)上のエピタキシャルバッファ構造(層2)は、AlN核生成層によって構成されているとともに、GaN(層3)、Al(Ga)N(層4)、およびSiN(層5)から構成される(Al(Ga)N(層4)およびSiN(層5)は任意)保護積層によってそのまま覆われた1つ以上の(In)AlGaNバッファ層によって任意に構成されている(従来技術を示す比較図1を参照)。構造は、基板とバッファ構成層(図1において矢印で示されている)との間に形成された導電チャネルをさらに備えている。この構造には、種々の標準的な半導体プロセスの工程(例えば、リソグラフィ、エッチング、堆積、インプラント、または酸化など)を実行し得、バッファ層上における選択的なエピタキシャル再成長のために、当該構造をMOCVD反応装置にさらに再導入し得る。一例において、基板(1)は、Si<111>である。他の例において、基板(1)はGe<111>である。また、他の例において、基板(1)は、結晶性Geの被覆を有しているSiである。上述のSiおよびGeの間には、SiGe移行層が存在し得る。
Claims (17)
- 半導体構造を製造する方法であって、
基板(例えば、Si、SiGe、Ge、絶縁体上のSi、絶縁体上のGe基板およびそれらの組み合わせ、好ましくはSi基板(例えば<111>Si基板))を準備すること;
上記基板上にエピタキシャルな半導体のバッファ層(例えばIII−Vバッファ層(例えばIII−窒化物層))を設けることによって、上記バッファ層および基板の間に導電性界面を得ること;
上記導電性界面における電流を遮断するために、上記導電性界面および部分的に上記基板に、1つ以上の局所的な電気絶縁を形成すること;ならびに、
上記1つ以上の局所的な電気絶縁を、少なくとも1つの上記局所的な電気絶縁が当該素子の高圧の端子および低圧の端子の間に配置されるように、素子と位置合わせすることを包含している、方法。 - 上記1つ以上の局所的な電気絶縁は、シャロートレンチアイソレーション(STI)、LOCOS、不純物インプランテーション、ディープトレンチエッチングおよびこれらの組み合わせによって形成される、請求項1に記載の方法。
- 上記1つ以上の局所的な電気絶縁は、規則的なパターンに好ましく形成される、請求項1または2に記載の方法。
- 上記1つ以上の局所的な電気絶縁は、25nm〜2.5μmの幅、好ましくは50nm〜1.5μmの幅、より好ましくは100nm〜1μmの幅(例えば200nm〜500nmの幅)であるか、および/または、上記1つ以上の局所的な電気絶縁の間の間隙は、0.2μm〜20μmの幅、好ましくは0.5μm〜10μmの幅、より好ましくは1μm〜5μmの幅であるか、および/または、上記1つ以上の局所的な電気絶縁の上記規則的なパターンの周期は、ゲートからドレインまでの距離より小さく、当該周期および距離は同一平面にある、請求項1〜3のいずれか1項に記載の方法。
- 上記1つ以上の局所的な電気絶縁によって形成されたパターンを、上記素子のゲートが当該パターンの直上に配置されるように、上記素子と位置合わせすることをさらに包含している、請求項3または4に記載の方法。
- 上記1つ以上の局所的な電気絶縁を、少なくとも1つの上記電気絶縁が上記素子のゲートおよびドレインの間に配置されるように、上記素子と位置合わせすることをさらに包含している、請求項1〜5のいずれか1項に記載の方法。
- 上記バッファ層は、1つ以上の局所的な電気絶縁を形成する前に、1つ以上の保護層を用いて覆われ、例えば、III−V層(例えば、GaN、AlNおよびAlGaN)、SiN層およびそれらの組み合わせである、請求項1〜6のいずれか1項に記載の方法。
- 上記1つ以上の保護層は、上記バッファ層上に付与されているGaN、GaN層上に付与されているAlN、およびAlN層上に付与されているSiNのスタックである、請求項7に記載の方法。
- 上記1つ以上の保護層は、再成長の前に、除去され、好ましくは選択的に除去される、請求項1〜8のいずれか1項に記載の方法。
- 上記絶縁は、例えばCMPによって、上記保護層の除去前に平坦化されている表面を形成する、請求項1〜9のいずれか1項に記載の方法。
- 再成長は、絶縁パターン(例えば、SiNパターンおよびSiOxパターン、ならびにこれらの組み合わせ)を用いて上記基板および/またはバッファ層をパターニングすることによって好ましく、選択的に実施され、好ましくはIII−N層といったIII−V層の再成長が実施される、請求項9または10に記載の方法。
- 請求項1〜11のいずれか1項にしたがって製造される半導体構造であって、
基板(例えば、Si、SiGe、Ge、絶縁体上のSi、絶縁体上のGe基板およびそれらの組み合わせ、好ましくはSi基板(例えば<111>Si基板))、
上記基板上にあるバッファ層(例えばIII−Vバッファ層(例えばIII−窒化物層))を備えており、
上記バッファ層は、当該バッファおよび上記基板の間に界面を有しており、
導電性パスは、1つ以上の電気絶縁によって遮断されていることを特徴とし、上記基板およびバッファ層の間の上記界面に存在している、半導体構造。 - 上記1つ以上の局所的な電気絶縁は、シャロートレンチアイソレーション(STI)、LOCOS、不純物インプランテーション、ディープトレンチエッチングおよびこれらの組み合わせによって形成されている、請求項12に記載の半導体構造。
- (a)上記1つ以上の局所的な電気絶縁は、25nm〜2.5μmの幅、より好ましくは50nm〜1.5μmの幅、より一層好ましくは100nm〜1μmの幅(例えば200nm〜500nmの幅)であるか、および/または、
(b)上記1つ以上の局所的な電気絶縁の間の間隙は、0.2μm〜20μmの幅、より好ましくは0.5μm〜10μmの幅、より一層好ましくは1μm〜5μmの幅であるか、および/または、
(c)上記1つ以上の局所的な電気絶縁の規則的なパターンの周期は、ゲートからドレインまでの距離より小さく、当該周期および距離は、同一平面にあり、好ましくは実質的に同一方向にある、請求項12または13に記載の半導体構造。 - 上記基板は局所的に除去されている、請求項12〜14のいずれか1項に記載の半導体構造。
- 請求項12〜15のいずれか1項に記載の半導体構造を備えている、素子(例えば、トランジスタ、FET、HEMT、DHFET、LED、ダイオードおよびパワーデバイス)。
- 請求項12〜15のいずれか1項に記載の半導体構造および/または請求項16に記載の素子を備えている、電子回路(例えば、電子回路、スイッチ、高出力の用途、高圧の用途、電力変換回路、画像センサ、バイオセンサ、ガスセンサおよびイオンセンサ)。
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CN113224193A (zh) * | 2021-04-12 | 2021-08-06 | 华南理工大学 | 结合嵌入电极与钝化层结构的InGaN/GaN多量子阱蓝光探测器及其制备方法与应用 |
CN113224193B (zh) * | 2021-04-12 | 2022-06-14 | 华南理工大学 | 结合嵌入电极与钝化层结构的InGaN/GaN多量子阱蓝光探测器及其制备方法与应用 |
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KR20140063593A (ko) | 2014-05-27 |
WO2013010828A1 (en) | 2013-01-24 |
US9230803B2 (en) | 2016-01-05 |
US20140167114A1 (en) | 2014-06-19 |
US20160099309A1 (en) | 2016-04-07 |
JP6120841B2 (ja) | 2017-04-26 |
CN103765592A (zh) | 2014-04-30 |
KR101674274B1 (ko) | 2016-11-08 |
CN103765592B (zh) | 2017-09-19 |
GB201112327D0 (en) | 2011-08-31 |
US9748331B2 (en) | 2017-08-29 |
EP2735030B1 (en) | 2017-03-15 |
EP2735030A1 (en) | 2014-05-28 |
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