JP2014519700A - 二枚のウェーハを接合するための方法及びデバイス - Google Patents
二枚のウェーハを接合するための方法及びデバイス Download PDFInfo
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- JP2014519700A JP2014519700A JP2014509646A JP2014509646A JP2014519700A JP 2014519700 A JP2014519700 A JP 2014519700A JP 2014509646 A JP2014509646 A JP 2014509646A JP 2014509646 A JP2014509646 A JP 2014509646A JP 2014519700 A JP2014519700 A JP 2014519700A
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- Prior art keywords
- pressure
- bonding
- wafers
- wafer
- pressure surface
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- 235000012431 wafers Nutrition 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000005540 biological transmission Effects 0.000 claims abstract description 10
- 238000005304 joining Methods 0.000 claims abstract description 7
- 238000003825 pressing Methods 0.000 claims description 2
- 238000002604 ultrasonography Methods 0.000 claims description 2
- 230000033001 locomotion Effects 0.000 description 9
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Measuring Fluid Pressure (AREA)
Abstract
Description
2、2’ 第二の構造ウェーハ
2o、2o’ 作用面
3 第一の構造ウェーハ
3o 固定面
4 固定具
5、5’ 構造体
6 湾曲部
7 辺
8 辺
9 交点
10 長辺
11 辺
15 第二の圧力板
V 接合面
D 圧力面
L 直線方向
特許文献1には、ウェーハがピンによってプレ接合される基板処理システムが開示されている。特許文献2には、SOIウェーハ用の製造方法及びラミネーションデバイスが開示されている。特許文献3には、ウェーハの接合方法が開示されている。特許文献4には、ウェーハを接合するための方法及びデバイスが開示されている。
Claims (9)
- 二枚のウェーハ(2、3)を該ウェーハ(2、3)の一つの接合面(V)において接合するためのデバイスであって、圧力面(D)において前記ウェーハ(2、3)に接合圧力を印加するための圧力面(D)を備えた圧力伝達手段が存在し、前記圧力面(D)が前記接合面(V)よりも小さいことを特徴とするデバイス。
- 前記圧力面(D)が前記接合面(V)の<80%、特に<60%、好ましくは<40%である、請求項1に記載のデバイス。
- 前記圧力面(D)が、前記接合面(V)の反対側の前記ウェーハ(2、3)の一方の一つの作用面(2o、2o’)に沿って少なくとも部分的に特に完全に移動する、請求項1又は2に記載のデバイス。
- 前記接合圧力が、前記圧力面(D)に対応する部分である前記接合面(V)の一部に印加される、請求項1から3のいずれか一項に記載のデバイス。
- 前記圧力面が、少なくとも部分的に特に完全に超音波に晒される、請求項1から4のいずれか一項に記載のデバイス。
- 前記圧力面(D)が、作用面(2o、2o’)に平行に特に直線的に又は回転して移動する、請求項1から5のいずれか一項に記載のデバイス。
- 前記圧力面(D)が楔型である、請求項1から6のいずれか一項に記載のデバイス。
- 前記圧力面(D)がストリップ状であり、特に平行な長辺(10)を備える、請求項1から6のいずれか一項に記載のデバイス。
- 二枚のウェーハ(2、3)を該二枚のウェーハ(2、3)の一つの接合面(V)において該ウェーハ(2,3)に作用する圧力面(D)を備えた圧力伝達手段によって接合するための方法であって、接合圧力が前記接合面(V)の複数の部分に逐次的に印加される、方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ATA666/2011A AT511384B1 (de) | 2011-05-11 | 2011-05-11 | Verfahren und vorrichtung zum bonden zweier wafer |
ATA666/2011 | 2011-05-11 | ||
PCT/EP2012/055840 WO2012152507A1 (de) | 2011-05-11 | 2012-03-30 | Verfahren und vorrichtung zum bonden zweier wafer |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015179211A Division JP2016036031A (ja) | 2011-05-11 | 2015-09-11 | 二枚のウェーハを接合するための方法及びデバイス |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014519700A true JP2014519700A (ja) | 2014-08-14 |
JP6066120B2 JP6066120B2 (ja) | 2017-01-25 |
Family
ID=45954643
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014509646A Active JP6066120B2 (ja) | 2011-05-11 | 2012-03-30 | 二枚のウェーハを接合するための方法及びデバイス |
JP2015179211A Pending JP2016036031A (ja) | 2011-05-11 | 2015-09-11 | 二枚のウェーハを接合するための方法及びデバイス |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015179211A Pending JP2016036031A (ja) | 2011-05-11 | 2015-09-11 | 二枚のウェーハを接合するための方法及びデバイス |
Country Status (8)
Country | Link |
---|---|
US (1) | US8926775B2 (ja) |
EP (1) | EP2659505B1 (ja) |
JP (2) | JP6066120B2 (ja) |
KR (1) | KR20130140157A (ja) |
CN (1) | CN103582940B (ja) |
AT (1) | AT511384B1 (ja) |
SG (1) | SG193422A1 (ja) |
WO (1) | WO2012152507A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102014106231A1 (de) * | 2014-05-05 | 2015-11-05 | Ev Group E. Thallner Gmbh | Verfahren und Vorrichtung zum permanenten Bonden |
CN111223810A (zh) * | 2018-11-27 | 2020-06-02 | 中科院微电子研究所昆山分所 | 一种晶圆键合加压装置、晶圆键合的方法及晶圆键合设备 |
US11651973B2 (en) | 2020-05-08 | 2023-05-16 | International Business Machines Corporation | Method and apparatus of processor wafer bonding for wafer-scale integrated supercomputer |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0684735A (ja) * | 1992-08-31 | 1994-03-25 | Sony Corp | 張り合わせ基板の製造方法と張り合わせ装置 |
JPH076937A (ja) * | 1993-06-16 | 1995-01-10 | Canon Inc | 半導体基板貼り合わせ装置 |
JP2005294824A (ja) * | 2004-03-12 | 2005-10-20 | Bondotekku:Kk | 真空中での超音波接合方法及び装置 |
JP2006245279A (ja) * | 2005-03-03 | 2006-09-14 | Nitto Denko Corp | 判別機能付き位置決め装置 |
JP2007301600A (ja) * | 2006-05-11 | 2007-11-22 | Matsushita Electric Ind Co Ltd | 接合方法及びその装置 |
JP2009220151A (ja) * | 2008-03-17 | 2009-10-01 | Bondtech Inc | 接合方法およびこの方法により作成されるデバイス、接合装置並びにこの方法により接合される基板 |
JP2010045189A (ja) * | 2008-08-12 | 2010-02-25 | Nitto Denko Corp | 半導体ウエハの保護テープ貼付け方法およびその装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6181474A (ja) * | 1984-09-28 | 1986-04-25 | Toshiba Ceramics Co Ltd | ウエ−ハ接着装置 |
JPH0725463B2 (ja) * | 1986-07-02 | 1995-03-22 | 富士通株式会社 | 半導体装置の製造方法 |
JP3321882B2 (ja) | 1993-02-28 | 2002-09-09 | ソニー株式会社 | 基板はり合わせ方法 |
JPH10178071A (ja) * | 1996-12-18 | 1998-06-30 | Sony Corp | チップボンディング装置及びチップボンディング方法 |
JP4322328B2 (ja) * | 1997-06-05 | 2009-08-26 | テキサス インスツルメンツ インコーポレイテツド | ウエハをウエハテープに接着する方法および装置 |
SG71182A1 (en) | 1997-12-26 | 2000-03-21 | Canon Kk | Substrate processing apparatus substrate support apparatus substrate processing method and substrate manufacturing method |
JP3901862B2 (ja) | 1998-12-21 | 2007-04-04 | 信越半導体株式会社 | ウェーハの結合方法 |
US6975016B2 (en) * | 2002-02-06 | 2005-12-13 | Intel Corporation | Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof |
JP2006032815A (ja) * | 2004-07-21 | 2006-02-02 | Kazuo Tanabe | ウエーハと支持基板の貼り合せ方法及び装置 |
TWI261316B (en) * | 2005-12-28 | 2006-09-01 | Ind Tech Res Inst | Wafer bonding method |
US8029638B2 (en) * | 2007-12-04 | 2011-10-04 | Panasonic Corporation | Component mounting apparatus and method |
JP5668275B2 (ja) | 2009-04-08 | 2015-02-12 | 株式会社Sumco | Soiウェーハの製造方法及び貼り合わせ装置 |
JP4988801B2 (ja) * | 2009-09-29 | 2012-08-01 | 東京エレクトロン株式会社 | 貼り合せ装置及び貼り合せ方法 |
-
2011
- 2011-05-11 AT ATA666/2011A patent/AT511384B1/de active
-
2012
- 2012-03-30 SG SG2013068572A patent/SG193422A1/en unknown
- 2012-03-30 JP JP2014509646A patent/JP6066120B2/ja active Active
- 2012-03-30 WO PCT/EP2012/055840 patent/WO2012152507A1/de active Application Filing
- 2012-03-30 KR KR1020137028655A patent/KR20130140157A/ko active Search and Examination
- 2012-03-30 EP EP12714278.4A patent/EP2659505B1/de active Active
- 2012-03-30 CN CN201280015662.5A patent/CN103582940B/zh active Active
- 2012-03-30 US US14/113,256 patent/US8926775B2/en active Active
-
2015
- 2015-09-11 JP JP2015179211A patent/JP2016036031A/ja active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0684735A (ja) * | 1992-08-31 | 1994-03-25 | Sony Corp | 張り合わせ基板の製造方法と張り合わせ装置 |
JPH076937A (ja) * | 1993-06-16 | 1995-01-10 | Canon Inc | 半導体基板貼り合わせ装置 |
JP2005294824A (ja) * | 2004-03-12 | 2005-10-20 | Bondotekku:Kk | 真空中での超音波接合方法及び装置 |
JP2006245279A (ja) * | 2005-03-03 | 2006-09-14 | Nitto Denko Corp | 判別機能付き位置決め装置 |
JP2007301600A (ja) * | 2006-05-11 | 2007-11-22 | Matsushita Electric Ind Co Ltd | 接合方法及びその装置 |
JP2009220151A (ja) * | 2008-03-17 | 2009-10-01 | Bondtech Inc | 接合方法およびこの方法により作成されるデバイス、接合装置並びにこの方法により接合される基板 |
JP2010045189A (ja) * | 2008-08-12 | 2010-02-25 | Nitto Denko Corp | 半導体ウエハの保護テープ貼付け方法およびその装置 |
Also Published As
Publication number | Publication date |
---|---|
CN103582940A (zh) | 2014-02-12 |
CN103582940B (zh) | 2017-05-31 |
US8926775B2 (en) | 2015-01-06 |
KR20130140157A (ko) | 2013-12-23 |
JP2016036031A (ja) | 2016-03-17 |
EP2659505A1 (de) | 2013-11-06 |
US20140196846A1 (en) | 2014-07-17 |
WO2012152507A1 (de) | 2012-11-15 |
EP2659505B1 (de) | 2014-04-09 |
AT511384A1 (de) | 2012-11-15 |
AT511384B1 (de) | 2019-10-15 |
JP6066120B2 (ja) | 2017-01-25 |
SG193422A1 (en) | 2013-10-30 |
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