JP2014209505A - 炭化珪素半導体装置の製造方法および炭化珪素半導体装置 - Google Patents
炭化珪素半導体装置の製造方法および炭化珪素半導体装置 Download PDFInfo
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- JP2014209505A JP2014209505A JP2013085734A JP2013085734A JP2014209505A JP 2014209505 A JP2014209505 A JP 2014209505A JP 2013085734 A JP2013085734 A JP 2013085734A JP 2013085734 A JP2013085734 A JP 2013085734A JP 2014209505 A JP2014209505 A JP 2014209505A
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Abstract
【解決手段】炭化珪素基板100は第1〜第3の半導体層121〜123を有する。第1および第3の半導層は第1の導電型を有し、第2の半導体層は第2の導電型を有する。トレンチTRは、第1の半導体層121からなる底面BTと、第1〜第3の半導体層121〜123のそれぞれからなる第1〜第3の側面SW1〜SW3とを有する。トレンチTR上には底部201Bおよび側壁部201Sを有するゲート絶縁膜201が設けられている。底部201Bは最小厚さd0を有する。側壁部201Sのうち第2の側面SW2上の部分は最小厚さd1を有する。側壁部201Sのうち第1の側面SW1上で底部201Bにつながる部分は厚さd2を有する。d2>d1かつd2>d0が満たされている。
【選択図】図3
Description
第1の導電型を有する第1の半導体層と、第1の半導体層上に設けられ第2の導電型を有する第2の半導体層と、第2の半導体層上に設けられ第2の半導体層によって第1の半導体層と分離され第1の導電型を有する第3の半導体層とを含む炭化珪素基板が準備される。
本発明の炭化珪素半導体装置は、炭化珪素基板と、ゲート絶縁膜と、ゲート電極とを有する。
(i) 炭化珪素半導体装置501,502の製造方法は、以下の工程を有する。
この製造方法によれば、角絶縁膜201Rを形成することで、d2>d1かつd2>d0を満たすゲート絶縁膜201が得られる。d2>d1により、低い電圧でのゲート制御と、トレンチTRの角部CR近傍でのゲート絶縁膜201の絶縁破壊防止との両方が可能となる。さらにd2>d0により、ゲート絶縁膜201の底部201Bが厚さd2よりも薄い部分を有するので、トレンチTRの底面BTから第1の半導体層121中への空乏層の延びを抑制することができる。よってこの空乏層が第1の半導体層121中の電流経路を狭窄する程度を抑制することができる。よって炭化珪素半導体装置501,502のオン抵抗を小さくすることができる。
(iii) 上記(ii)において、被覆絶縁膜251,252をエッチバックする工程は、ウエットエッチングによって行なわれることが好ましい。
この炭化珪素半導体装置501,502によれば、ゲート絶縁膜201がd2>d1かつd2>d0を満たす。d2>d1により、低い電圧でのゲート制御と、トレンチTRの角部CR近傍でのゲート絶縁膜201の絶縁破壊防止との両方が可能となる。さらにd2>d0により、ゲート絶縁膜201の底部201Bが厚さd2よりも薄い部分を有するので、トレンチTRの底面BTから第1の半導体層121中への空乏層の延びを抑制することができる。よってこの空乏層が第1の半導体層121中の電流経路を狭窄する程度を抑制することができる。よって炭化珪素半導体装置501,502のオン抵抗を小さくすることができる。
これにより、ゲート絶縁膜201の底部201Bに、過度に薄い部分が形成されない。よってゲート絶縁膜201の絶縁破壊をより確実に防止することができる。
図1に示すように、本実施の形態のMOSFET501(炭化珪素半導体装置)は、エピタキシャル基板100(炭化珪素基板)と、ゲート絶縁膜201と、ゲート電極230と、層間絶縁膜203と、ソース電極221と、ドレイン電極211と、ソース配線222と、保護電極212とを有する。
図4を参照して、単結晶基板110上にn-層121がエピタキシャル成長により形成される。このエピタキシャル成長は、たとえば原料ガスとしてシラン(SiH4)とプロパン(C3H8)との混合ガスを用い、キャリアガスとしてたとえば水素ガス(H2)を用いたCVD(Chemical Vapor Deposition)法により行うことができる。また、このときドナーとしてたとえば窒素(N)やリン(P)を導入することが好ましい。
図19に示すように、本実施の形態のMOSFET502(炭化珪素半導体装置)においては、実施の形態1(図3)と異なり、境界部BPが側面SW1およびSW2の境界上に位置している。ここでの「境界上に位置し」とは製造誤差を全く許容しないものではなく、具体的には±0.1μm程度の誤差は許容される。境界部BPをこのように位置させるためには、たとえば、実施の形態1におけるエッチバック工程(図11および図12)の進行の程度を抑えればよい。なお上記以外の構成については、上述した実施の形態1の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。
本実施の形態の炭化珪素半導体装置の製造方法においては、まず、実施の形態1の図4〜図8と同様の工程が行われる。
上述したように、トレンチTRの側壁面SW(図3)、特に側面SW2は、所定の結晶面(特殊面とも称する)を有することが好ましい。このような側壁面SWは、図21に示すように、面方位{0−33−8}を有する面S1(第1の面)を含む。面S1は好ましくは面方位(0−33−8)を有する。
一般に、ポリタイプ4Hの炭化珪素単結晶を(000−1)面から見ると、図22に示すように、Si原子(またはC原子)は、A層の原子(図中の実線)と、この下に位置するB層の原子(図中の破線)と、この下に位置するC層の原子(図中の一点鎖線)と、この下に位置するB層の原子(図示せず)とが繰り返し設けられている。つまり4つの層ABCBを1周期としてABCBABCBABCB・・・のような周期的な積層構造が設けられている。
今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。たとえば、炭化珪素半導体装置は、MOSFET以外のMISFET(Metal Insulator Semiconductor Field Effect Transistor)であってもよい。また炭化珪素半導体装置はMISFETに限定されず、たとえばIGBT(Insulated Gate Bipolar Transistor)であってもよい。また第1および第2の導電型のそれぞれはn型およびp型に限定されず、これらが入れ替えられてもよい。
110 単結晶基板
121 n-層121(第1の半導体層)
122 p型ボディ層(第2の半導体層)
123 n領域(第3の半導体層)
124 コンタクト領域
201 ゲート絶縁膜
201P 下部絶縁膜(第1の絶縁膜)
202 上部絶縁膜(第2の絶縁膜)
201B 底部
201P 下部絶縁膜(第1の絶縁膜)
201S 側壁部
202 上部絶縁膜(第2の絶縁膜)
203 層間絶縁膜
211 ドレイン電極
212 保護電極
221 ソース電極
222 ソース配線
230 ゲート電極
251,252 被覆絶縁膜
252B 底部分
252S 側壁部分
252T 表面部分
302 シリコン膜
302P 堆積膜
401 マスク
402 レジスト層
501,502 MOSFET(炭化珪素半導体装置)
BT 底面
CR 角部
SW 側壁面
SW1〜SW3 第1〜第3の側面
TR トレンチ
Claims (14)
- 第1の導電型を有する第1の半導体層と、前記第1の半導体層上に設けられ第2の導電型を有する第2の半導体層と、前記第2の半導体層上に設けられ前記第2の半導体層によって前記第1の半導体層と分離され前記第1の導電型を有する第3の半導体層とを含む炭化珪素基板を準備する工程と、
前記炭化珪素基板にトレンチを形成する工程とを備え、前記トレンチは、前記第1の半導体層からなる底面と、前記第1〜第3の半導体層のそれぞれからなる第1〜第3の側面を有する側壁面とを含み、前記トレンチは前記第1の側面と前記底面とが合わさることで構成された角部を有し、
前記トレンチ上にゲート絶縁膜を形成する工程を備え、前記ゲート絶縁膜は、前記底面を覆う底部と、前記底部につながっておりかつ前記側壁面を覆う側壁部とを有し、前記底部は最小厚さd0を有し、前記側壁部のうち前記第2の側面上の部分は最小厚さd1を有し、前記側壁部のうち前記第1の側面上で前記底部につながる部分は厚さd2を有し、d2>d1かつd2>d0が満たされており、前記ゲート絶縁膜を形成する工程は、前記角部を覆い、かつ前記トレンチの前記第2の側面の少なくとも一部を露出する角絶縁膜を形成する工程と、前記角絶縁膜が形成された後に前記トレンチを熱酸化する工程とを含み、さらに
前記ゲート絶縁膜を介して前記トレンチ上にゲート電極を形成する工程を備える、炭化珪素半導体装置の製造方法。 - 前記角絶縁膜を形成する工程は、
前記トレンチを覆う被覆絶縁膜を形成する工程と、
前記被覆絶縁膜をエッチバックする工程とを含む、請求項1に記載の炭化珪素半導体装置の製造方法。 - 前記被覆絶縁膜を前記エッチバックする工程はウエットエッチングによって行なわれる、請求項2に記載の炭化珪素半導体装置の製造方法。
- 前記被覆絶縁膜を形成する工程は、
前記トレンチ上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜を形成する工程の後に、前記第1の絶縁膜のうち前記角部に位置する部分を覆い、かつ前記第1の絶縁膜のうち第2の側面上に位置する部分の少なくとも一部を露出する第2の絶縁膜を形成する工程とを含む、請求項2または3のいずれか1項に記載の炭化珪素半導体装置の製造方法。 - 前記第2の絶縁膜を形成する工程は、
前記第1の絶縁膜を形成する工程の後に、前記第1の絶縁膜のうち角部に位置する部分を覆い、かつ前記第1の絶縁膜のうち第2の側面上に位置する部分の少なくとも一部を露出するシリコン膜を形成する工程と、
前記シリコン膜を酸化する工程とを含む、請求項4に記載の炭化珪素半導体装置の製造方法。 - 前記シリコン膜を形成する工程は、
シリコンを堆積することによって、前記トレンチを被覆する堆積膜を形成する工程と、
前記堆積膜を介して前記トレンチを埋めるようにレジスト液を塗布することでレジスト層を形成する工程と、
前記レジスト層をエッチバックすることによって、前記トレンチ内に前記レジスト層が部分的に残るように、前記レジスト層をパターニングする工程と、
前記レジスト層をパターニングする工程の後に、前記レジスト層をマスクとして用いて前記堆積膜をエッチングする工程とを含む、請求項5に記載の炭化珪素半導体装置の製造方法。 - 前記被覆絶縁膜は、前記底面上に位置する底部分と、前記底部分につながるように前記側壁面上に位置する側壁部分とを有し、
前記被覆絶縁膜を形成する工程は、前記底部分につながる位置において前記側壁部分が最大の厚さを有するように前記トレンチ上に熱酸化膜を形成することによって行なわれる、請求項2または3のいずれか1項に記載の炭化珪素半導体装置の製造方法。 - 前記熱酸化膜を形成する工程は、1300℃未満の温度での熱酸化によって行なわれる、請求項7に記載の炭化珪素半導体装置の製造方法。
- 炭化珪素半導体装置であって、
第1の導電型を有する第1の半導体層と、前記第1の半導体層上に設けられ第2の導電型を有する第2の半導体層と、前記第2の半導体層上に設けられ前記第2の半導体層によって前記第1の半導体層と分離され前記第1の導電型を有する第3の半導体層とを含む炭化珪素基板を備え、前記炭化珪素基板にはトレンチが設けられており、前記トレンチは、前記第1の半導体層からなる底面と、前記第1〜第3の半導体層のそれぞれからなる第1〜第3の側面を有する側壁面とを含み、前記炭化珪素半導体装置はさらに
前記トレンチ上に設けられたゲート絶縁膜を備え、前記ゲート絶縁膜は、前記底面を覆う底部と、前記底部につながっておりかつ前記側壁面を覆う側壁部とを有し、前記底部は最小厚さd0を有し、前記側壁部のうち前記第2の側面上の部分は最小厚さd1を有し、前記側壁部のうち前記第1の側面上で前記底部につながる部分は厚さd2を有し、d2>d1かつd2>d0が満たされており、前記炭化珪素半導体装置はさらに
前記ゲート絶縁膜を介して前記トレンチ上に設けられたゲート電極を備える、炭化珪素半導体装置。 - d0>d1が満たされている、請求項9に記載の炭化珪素半導体装置。
- 前記ゲート絶縁膜の前記側壁部は、前記第2の側面上において、厚さd2よりも小さい厚さを有する部分によって前記第1および第3の半導体層をつないでいる、請求項9または10に記載の炭化珪素半導体装置。
- 前記ゲート絶縁膜の前記側壁部は、前記第2の側面上において、厚さd1を有する部分によって前記第1および第3の半導体層をつないでいる、請求項9〜11のいずれか1項に記載の炭化珪素半導体装置。
- 前記ゲート絶縁膜の前記側壁部は、前記第1の側面上において、厚さd1よりも大きい厚さを有する部分によって前記第2の半導体層と前記底部との間をつないでいる、請求項9〜12のいずれか1項に記載の炭化珪素半導体装置。
- 前記ゲート絶縁膜の前記側壁部は、前記第1の側面上において、厚さd2を有する部分によって前記第2の半導体層と前記底部との間をつないでいる、請求項9〜13のいずれか1項に記載の炭化珪素半導体装置。
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JP2016164906A (ja) * | 2015-03-06 | 2016-09-08 | 豊田合成株式会社 | 半導体装置およびその製造方法ならびに電力変換装置 |
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CN112736123A (zh) * | 2019-10-28 | 2021-04-30 | 苏州东微半导体股份有限公司 | 半导体功率器件终端结构 |
CN111489962B (zh) * | 2020-04-17 | 2023-09-26 | 重庆伟特森电子科技有限公司 | 一种厚底沟槽的制备方法 |
US11469307B2 (en) * | 2020-09-29 | 2022-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device |
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