JP2014204041A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2014204041A
JP2014204041A JP2013080783A JP2013080783A JP2014204041A JP 2014204041 A JP2014204041 A JP 2014204041A JP 2013080783 A JP2013080783 A JP 2013080783A JP 2013080783 A JP2013080783 A JP 2013080783A JP 2014204041 A JP2014204041 A JP 2014204041A
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Japan
Prior art keywords
gate electrode
insulating film
film
semiconductor device
region
Prior art date
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Withdrawn
Application number
JP2013080783A
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English (en)
Japanese (ja)
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JP2014204041A5 (enExample
Inventor
平野　有一
Yuichi Hirano
有一 平野
竜善 三原
Tatsuyoshi Mihara
竜善 三原
恵介 塚本
Keisuke Tsukamoto
恵介 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2013080783A priority Critical patent/JP2014204041A/ja
Priority to TW103104997A priority patent/TW201440171A/zh
Priority to US14/244,952 priority patent/US20140302646A1/en
Priority to CN201410136063.XA priority patent/CN104103594A/zh
Publication of JP2014204041A publication Critical patent/JP2014204041A/ja
Publication of JP2014204041A5 publication Critical patent/JP2014204041A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0147—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2013080783A 2013-04-08 2013-04-08 半導体装置の製造方法 Withdrawn JP2014204041A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2013080783A JP2014204041A (ja) 2013-04-08 2013-04-08 半導体装置の製造方法
TW103104997A TW201440171A (zh) 2013-04-08 2014-02-14 半導體裝置之製造方法
US14/244,952 US20140302646A1 (en) 2013-04-08 2014-04-04 Method of manufacturing semiconductor device
CN201410136063.XA CN104103594A (zh) 2013-04-08 2014-04-04 半导体器件的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013080783A JP2014204041A (ja) 2013-04-08 2013-04-08 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2014204041A true JP2014204041A (ja) 2014-10-27
JP2014204041A5 JP2014204041A5 (enExample) 2016-03-24

Family

ID=51654727

Family Applications (1)

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JP2013080783A Withdrawn JP2014204041A (ja) 2013-04-08 2013-04-08 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US20140302646A1 (enExample)
JP (1) JP2014204041A (enExample)
CN (1) CN104103594A (enExample)
TW (1) TW201440171A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017092290A (ja) * 2015-11-11 2017-05-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR20170086634A (ko) * 2014-12-04 2017-07-26 실리콘 스토리지 테크놀로지 인크 동시에 형성되는 저전압 및 고전압 로직 디바이스들을 구비한 비휘발성 메모리 어레이
JP2017174887A (ja) * 2016-03-22 2017-09-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2018117067A (ja) * 2017-01-19 2018-07-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6026914B2 (ja) * 2013-02-12 2016-11-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9496276B2 (en) * 2013-11-27 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. CMP fabrication solution for split gate memory embedded in HK-MG process
JP6450624B2 (ja) * 2015-03-30 2019-01-09 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6518485B2 (ja) 2015-03-30 2019-05-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
EP3179514B1 (en) * 2015-12-11 2024-01-24 IMEC vzw Transistor device with reduced hot carrier injection effect
JP6683488B2 (ja) * 2016-02-03 2020-04-22 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2017139375A (ja) * 2016-02-04 2017-08-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US10276587B2 (en) * 2016-05-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. NVM memory HKMG integration technology
JP6591347B2 (ja) * 2016-06-03 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US11037830B2 (en) * 2019-10-14 2021-06-15 Renesas Electronics Corporation Method of manufacturing semiconductor device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100429790C (zh) * 2003-03-19 2008-10-29 富士通株式会社 半导体器件及其制造方法
US7220650B2 (en) * 2004-04-09 2007-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Sidewall spacer for semiconductor device and fabrication method thereof
US20060046523A1 (en) * 2004-08-25 2006-03-02 Jack Kavalieros Facilitating removal of sacrificial layers to form replacement metal gates
US7394155B2 (en) * 2004-11-04 2008-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Top and sidewall bridged interconnect structure and method
JP2009302269A (ja) * 2008-06-13 2009-12-24 Renesas Technology Corp 半導体装置の製造方法および半導体装置
US8536007B2 (en) * 2012-02-22 2013-09-17 Freescale Semiconductor, Inc. Non-volatile memory cell and logic transistor integration
US9006045B2 (en) * 2013-03-11 2015-04-14 Globalfoundries Inc. Transistor including a gate electrode extending all around one or more channel regions

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170086634A (ko) * 2014-12-04 2017-07-26 실리콘 스토리지 테크놀로지 인크 동시에 형성되는 저전압 및 고전압 로직 디바이스들을 구비한 비휘발성 메모리 어레이
JP2017536703A (ja) * 2014-12-04 2017-12-07 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 同時に形成された低及び高電圧論理デバイスを有する不揮発性メモリアレイ
KR102050146B1 (ko) 2014-12-04 2020-01-08 실리콘 스토리지 테크놀로지 인크 동시에 형성되는 저전압 및 고전압 로직 디바이스들을 구비한 비휘발성 메모리 어레이
JP2017092290A (ja) * 2015-11-11 2017-05-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9768187B2 (en) 2015-11-11 2017-09-19 Renesas Electronics Corporation Method of manufacturing split-gate non-volatile memory with hi-voltage and low-voltage peripheral circuitry
JP2017174887A (ja) * 2016-03-22 2017-09-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2018117067A (ja) * 2017-01-19 2018-07-26 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
TW201440171A (zh) 2014-10-16
CN104103594A (zh) 2014-10-15
US20140302646A1 (en) 2014-10-09

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