JP2013513976A - 電子基板に組み込まれたビア構造 - Google Patents
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Abstract
Description
104 基板
106 TSV
108 導電層
110 絶縁層または誘電層
112 遮蔽層
114 サリサイド膜
116 誘電材料
118 前面
120 背面
122 拡散障壁誘電膜
124 誘電材料
126 第1背面金属層
128 第2背面金属層
130 背面ビア構造
Claims (17)
- 第1ビア構造を含む、基板内のビア構造のシステムであって、
前記基板に配置された外側導電層と、
前記外側導電層が内側絶縁層と前記基板とを分離するように、前記基板に配置された前記内側絶縁層と、
前記内側絶縁層が内側導電層と前記外側導電層とを分離するように、前記基板に配置された前記内側導電層と、を備え、
第1相補的対の第1信号が前記内側導電層を通過し、前記第1相補的対の第2信号が前記外側導電層を通過する、システム。 - 外側絶縁層が前記外側導電層と前記基板とを分離するように、前記基板に配置された前記外側絶縁層をさらに備える、請求項1に記載のシステム。
- 前記外側導電層に連結されたサリサイド膜をさらに備える、請求項1に記載のシステム。
- 前記サリサイド膜が、金属層に連結されるように構成されたリング状構造を有する、請求項3に記載のシステム。
- 前記第1信号および前記第2信号が実質的に逆の極性を有する、請求項1に記載のシステム。
- 前記第1ビア構造に隣接して配置された第2ビア構造をさらに備え、
前記第2ビア構造が、
外側導電層が内側導電層を取り囲むように、前記基板に配置された前記内側導電層および前記外側導電層と、
前記外側導電層と前記内側導電層との間に配置された内側絶縁層と、を備え、
第2相補的対の第1信号が前記内側導電層を通過し、前記第2相補的対の第2信号が前記外側導電層を通過する、請求項1に記載のシステム。 - 前記第1相補的対の前記第2信号および前記第2相補的対の前記第2信号が実質的に逆の極性を有する、請求項6に記載のシステム。
- 前記外側導電層が、チタン、窒化チタン、タンタル、窒化タンタル、またはこれらの組合せを含む、請求項1に記載のシステム。
- 電子基板にビア構造を形成する方法であって、
前記基板に開口部を形成するステップと、
前記開口部に外側導電層を堆積するステップと、
前記外側導電層が内側絶縁層と前記基板とを分離するように、前記開口部に前記内側絶縁層を堆積するステップと、
前記内側絶縁層が前記外側導電層と内側導電層とを分離するように、前記開口部に前記内側導電層を堆積するステップと、
前記外側導電層をサリサイド材料に接触させるステップと、を含む方法。 - 外側絶縁層が前記外側導電層と前記基板とを分離するように、前記開口部に前記外側絶縁層を堆積するステップをさらに含む、請求項9に記載の方法。
- 前記サリサイド材料を接地するステップをさらに含む、請求項9に記載の方法。
- 前記サリサイド材料をリング状構造として形成するステップをさらに含む、請求項9に記載の方法。
- 電子デバイスにおける電場または磁場を低減する方法であって、
基板に第1導電層を形成するステップと、
前記第1導電層を絶縁層で取り囲むステップと、
前記絶縁層を第2導電層で取り囲むステップと、
相補的対の第1信号を前記第1導電層に通過させ、前記相補的対の第2信号を前記第2導電層に通過させるステップと、を含み、
前記第2導電層が、前記第1導電層を通過する前記第1信号によって生じる電場または磁場を低減するように構成される、方法。 - 前記第2導電層を第1電位に連結するステップをさらに含む、請求項16に記載の方法。
- 前記第2導電層をサリサイド材料に連結するステップをさらに含む、請求項16に記載の方法。
- 前記第2導電層を取り囲む別の絶縁層を形成するステップをさらに含む、請求項16に記載の方法。
- 電子デバイスにおける電場または磁場を低減するためのビア構造であって、
基板において相補的対の第1信号を伝導するための第1導電手段と、
前記基板において前記相補的対の第2信号を伝導するための第2導電手段であって、前記第1導電手段が第2導電手段を取り囲んでいる、第2導電手段と、
前記第1導電手段を前記第2導電手段から絶縁するための絶縁手段と、を備え、
前記第1信号および前記第2信号が実質的に逆の極性を有する、ビア構造。
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US12/637,104 | 2009-12-14 | ||
US12/637,104 US8227708B2 (en) | 2009-12-14 | 2009-12-14 | Via structure integrated in electronic substrate |
PCT/US2010/060362 WO2011075491A1 (en) | 2009-12-14 | 2010-12-14 | Via structure integrated in electronic substrate |
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JP2013513976A true JP2013513976A (ja) | 2013-04-22 |
JP5568644B2 JP5568644B2 (ja) | 2014-08-06 |
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US (1) | US8227708B2 (ja) |
EP (1) | EP2513969B1 (ja) |
JP (1) | JP5568644B2 (ja) |
KR (1) | KR101394062B1 (ja) |
CN (1) | CN102656687B (ja) |
TW (1) | TW201133758A (ja) |
WO (1) | WO2011075491A1 (ja) |
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- 2010-12-14 WO PCT/US2010/060362 patent/WO2011075491A1/en active Application Filing
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Publication number | Publication date |
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KR101394062B1 (ko) | 2014-05-13 |
US20110139497A1 (en) | 2011-06-16 |
TW201133758A (en) | 2011-10-01 |
EP2513969B1 (en) | 2019-01-16 |
JP5568644B2 (ja) | 2014-08-06 |
WO2011075491A1 (en) | 2011-06-23 |
EP2513969A1 (en) | 2012-10-24 |
CN102656687A (zh) | 2012-09-05 |
KR20120102778A (ko) | 2012-09-18 |
US8227708B2 (en) | 2012-07-24 |
CN102656687B (zh) | 2017-03-22 |
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