JP2013503480A - 完全アモルファスの相変化メモリ細孔セルの化学機械研磨ストップ層 - Google Patents
完全アモルファスの相変化メモリ細孔セルの化学機械研磨ストップ層 Download PDFInfo
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
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Abstract
【解決手段】本方法は、下部電極を形成するステップと、下部電極上に第1の誘電体層を形成するステップと、第1の誘電体層上に犠牲層を形成するステップと、犠牲層上に絶縁層を形成するステップと、絶縁層上に第2の誘電体層を形成するステップとを含む。本方法はさらに、下部電極の上方に位置し犠牲層まで延在するビアを形成するステップと、犠牲層及び第1の誘電体層を貫いて延在する画定された細孔を形成するために、犠牲層を貫いて第1の誘電体層までをエッチングするステップと、犠牲層上及び細孔の中に相変化物質を堆積させ、細孔の外に形成された相変化物質を除去するステップと、細孔を露出させるために犠牲層を除去するステップであって、細孔は垂直配向されている、該ステップと、細孔の上に上部電極を形成するステップとを含む。
【選択図】図19
Description
Claims (23)
- 相変化メモリ細孔セルを製造する方法であって、
下部電極を形成するステップと、
前記下部電極上に第1の誘電体層を形成するステップと、
前記第1の誘電体層上に犠牲層を形成するステップと、
前記犠牲層上に絶縁層を形成するステップと、
前記絶縁層上に第2の誘電体層を形成するステップと、
前記下部電極の上方に位置し前記犠牲層に向かって延在するビアを形成するステップと、
前記犠牲層及び前記第1の誘電体層を貫いて延在する画定された細孔を形成するために、前記犠牲層を貫いて前記第1の誘電体層までをエッチングするステップと、
前記犠牲層上及び前記細孔の中に相変化物質を堆積させ、前記細孔の外に形成された前記相変化物質を除去するステップと、
前記細孔を露出させるために前記犠牲層を除去するステップであって、前記細孔は垂直配向されている、前記ステップと、
前記細孔の上に上部電極を形成するステップと、
を含む方法。 - 前記犠牲層は、前記細孔の外の前記相変化物質を除去するとき、化学機械研磨ストップ層としての機能を果たす、請求項1に記載の方法。
- 前記第1の誘電体層は、窒化ケイ素から形成され、前記犠牲層は、窒化ケイ素から形成され、前記第2の誘電体層は、窒化ケイ素から形成され、前記絶縁層は、二酸化ケイ素から形成される、請求項2に記載の方法。
- 前記犠牲層は、摂氏200度の加工温度を有する窒化ケイ素から形成され、前記第1の誘電体層は、摂氏400度の加工温度を有する窒化ケイ素から形成される、請求項3に記載の方法。
- 前記犠牲層は、化学機械研磨動作によって除去される、請求項4に記載の方法。
- 前記犠牲層は、前記相変化物質よりも遅い化学機械研磨速度と、前記細孔を含む前記第1の誘電体層よりも速い化学機械研磨速度とを有する、請求項5に記載の方法。
- ビアを形成するステップは、
エッチング動作を使用して、前記ビアの周囲の前記絶縁層を窪ませ、前記第2の誘電体層に突出部を作るステップと、
前記ビア内にコンフォーマル膜を堆積させて、前記ビアの下方の領域内でキーホール構造の形成を生じさせるステップと、
前記細孔を形成するために、前記犠牲層及び前記第1の誘電体層を貫いて前記キーホール構造をエッチングするステップであって、前記下部電極を露出させる、前記ステップと、
をさらに含む、請求項3に記載の方法。 - 前記細孔は、前記上部電極及び前記下部電極と直接接触している、請求項1に記載の方法。
- 前記細孔は、均一な幅である、請求項8に記載の方法。
- 前記細孔の前記均一な幅は、1nm〜40nmの間である、請求項9に記載の方法。
- 前記細孔は、実質的に垂直な側壁を含み、側壁はそれぞれ、75度〜90度の角度を有する、請求項8に記載の方法。
- 下部電極を含む下部電極層と、
前記下部電極層の上に形成されたメモリ・セル層と、
を含む相変化メモリ細孔セルであって、前記メモリ・セル層は、
前記下部電極層の上に形成された誘電体層と、
前記誘電体層の上に形成され、前記下部電極から離れている上部電極と、
を含み、前記誘電体層は、垂直配向され前記上部電極及び前記下部電極により境界を付けられている細孔を含み、前記細孔は、前記上部電極及び前記下部電極と電気的に連絡しており、前記細孔は、電気特性状態間を切り替え可能な相変化物質を含む、相変化メモリ細孔セル。 - 前記細孔は、前記上部電極及び前記下部電極と直接接触している、請求項12に記載の相変化メモリ細孔セル。
- 前記細孔は、均一な幅である、請求項13に記載の相変化メモリ細孔セル。
- 前記細孔の前記均一な幅は、1nm〜40nmの間である、請求項14に記載の相変化メモリ細孔セル。
- 前記細孔は、実質的に垂直な側壁を含み、側壁はそれぞれ、75度〜90度の角度を有する、請求項13に記載の相変化メモリ細孔セル。
- 前記細孔は、前記誘電体層の高さと同じ高さである、請求項13に記載の相変化メモリ細孔セル。
- 1つ以上の相変化メモリ要素と、
前記1つ以上の相変化メモリ要素のうちの1つと接触している下部電極と、
前記1つ以上の相変化メモリ要素のうちの1つと接触し、前記下部電極から離れている上部電極と、
を含むメモリ・デバイスであって、
相変化メモリ要素はそれぞれ、
前記下部電極の上に形成された誘電体層
を含み、前記誘電体層は、垂直配向され前記上部電極及び前記下部電極により境界を付けられている細孔を含み、前記細孔は、前記上部電極及び前記下部電極と電気的に連絡しており、前記細孔は、電気特性状態間を切り替え可能な相変化物質を含む、メモリ・デバイス。 - 前記細孔は、前記上部電極及び前記下部電極と直接接触している、請求項18に記載の相変化メモリ・デバイス。
- 前記細孔は、均一な幅である、請求項19に記載の相変化メモリ・デバイス。
- 前記細孔の前記均一な幅は、1nm〜40nmの間である、請求項20に記載の相変化メモリ・デバイス。
- 前記細孔は、実質的に垂直な側壁を含み、側壁はそれぞれ、75度〜90度の角度を有する、請求項19に記載の相変化メモリ・デバイス。
- 前記細孔は、前記誘電体層の高さと同じ高さである、請求項19に記載の相変化メモリ・デバイス。
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PCT/US2010/043631 WO2011025620A1 (en) | 2009-08-28 | 2010-07-29 | Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |
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US8012790B2 (en) * | 2009-08-28 | 2011-09-06 | International Business Machines Corporation | Chemical mechanical polishing stop layer for fully amorphous phase change memory pore cell |
US8283650B2 (en) * | 2009-08-28 | 2012-10-09 | International Business Machines Corporation | Flat lower bottom electrode for phase change memory cell |
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US8012790B2 (en) | 2011-09-06 |
JP5829317B2 (ja) | 2015-12-09 |
CN102473597A (zh) | 2012-05-23 |
DE112010003457B4 (de) | 2019-04-18 |
CN102473597B (zh) | 2016-01-20 |
US20110210307A1 (en) | 2011-09-01 |
US8492194B2 (en) | 2013-07-23 |
TWI493763B (zh) | 2015-07-21 |
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