JP2013243187A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2013243187A JP2013243187A JP2012114126A JP2012114126A JP2013243187A JP 2013243187 A JP2013243187 A JP 2013243187A JP 2012114126 A JP2012114126 A JP 2012114126A JP 2012114126 A JP2012114126 A JP 2012114126A JP 2013243187 A JP2013243187 A JP 2013243187A
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Abstract
【解決手段】半導体装置1は、基板10と、ゲート絶縁膜20と、ゲート電極30とを有している。基板10は、一方の主表面10A上に開口し、第1の側壁面17Aを有する複数の第1の凹部17が形成され、化合物半導体からなる。ゲート絶縁膜20は、第1の側壁面17A上に接触して配置されている。ゲート電極30は、ゲート絶縁膜20上に接触して配置されている。基板10は、厚み方向に沿った断面で見て、第1の凹部17を挟んで対向するように配置された第1導電型のソース領域15と、第1の凹部17を挟んで対向するように配置された第2導電型のボディ領域14とを含んでいる。対向するソース領域15同士は、平面的に見て第1の凹部17と、第1の凹部17と隣り合う他の第1の凹部17とに挟まれる領域において互いに接続されている。
【選択図】図1
Description
まず、本発明の一実施の形態である実施の形態1について説明する。はじめに、図1を参照して、実施の形態1に係る半導体装置としてのMOSFET1の構造について説明する。MOSFET1は、化合物半導体からなり、主表面10Aを有する基板10と、ゲート絶縁膜20と、ゲート電極30と、層間絶縁膜40と、オーミック電極50と、ソースパッド電極60と、ドレイン電極70と、ドレインパッド電極80とを備えている。基板10は、ベース基板11と、半導体層12とを含み、半導体層12にはドリフト領域13と、ボディ領域14と、ソース領域15と、高濃度第2導電型領域16とが形成されている。また、基板10には、主表面10A側に開口し、第1の側壁面17Aおよび第1の底壁面17Bを有する複数の第1の凹部17(図9参照)が形成されている。さらに、基板10には、主表面10A側に開口し、第2の側壁面18Aおよび第2の底壁面18Bを有する第2の凹部18(図9参照)が形成されている。
実施の形態1に係るMOSFET1によれば、第1の凹部17を挟んで対向するソース領域15同士は、平面的に見て第1の凹部17と、当該第1の凹部17と隣り合う他の第1の凹部17とに挟まれる領域において互いに接続されている。それゆえ、第1の凹部17を挟んで対向するソース領域15の一方に接してオーミック電極50を設ければ、他方にオーミック電極50を設けなくとも双方のソース領域15に電流を流すことができる。結果として、オーミック電極50を設けるセルの数を低減することができるので、セルを微細化することができる。
次に、本発明の他の実施の形態である実施の形態2について説明する。まず、実施の形態2に係る半導体装置としてのMOSFET2の構造について説明する。図14を参照して、MOSFET2は、基本的には、実施の形態1のMOSFET1と同様の構造を有する。しかし、MOSFET2は、図14に示すように、コンタクトセル18Cとチャネルセル17Cとの間にパッシブセル19Cを有している点においてMOSFET1とは異なっている。なお、パッシブセル19Cとは主に電界緩和の機能を有するセルのことである。
実施の形態2に係るMOSFET2によれば、基板10は、第3の凹部19の第3の側壁面19Aに接触し、かつボディ領域14と接触して配置された第2導電型の電界緩和領域35をさらに含む。電界緩和に特化するセルを設けることにより、電界集中をより確実に抑制することができる。
Claims (7)
- 一方の主表面上に開口し、第1の側壁面を有する複数の第1の凹部が形成され、化合物半導体からなる基板と、
前記第1の側壁面上に接触して配置されたゲート絶縁膜と、
前記ゲート絶縁膜上に接触して配置されたゲート電極とを備え、
前記基板は、
厚み方向に沿った断面で見て、前記第1の側壁面において露出し、第1の凹部を挟んで対向するように配置された第1導電型のソース領域と、
前記ソース領域に接触するとともに前記第1の側壁面において露出し、前記第1の凹部を挟んで対向するように前記ソース領域から見て前記一方の主表面とは反対側に配置された第2導電型のボディ領域とを含み、
前記第1の凹部を挟んで対向する前記ソース領域同士は、平面的に見て前記第1の凹部と、前記第1の凹部に隣り合う他の第1の凹部に挟まれる領域において互いに接続されている、半導体装置。 - 前記基板には、第2の側壁面を有する第2の凹部がさらに形成されており、
前記第2の側壁面において前記ソース領域が露出し、
前記第2の側壁面上に形成され、前記ソース領域とオーミック接触するオーミック電極をさらに備える、請求項1に記載の半導体装置。 - 前記オーミック電極および前記ボディ領域に接触する高濃度第2導電型領域をさらに備えた、請求項2に記載の半導体装置。
- 前記高濃度第2導電型領域の底面は前記第1の凹部の第1の底壁面よりも前記一方の主表面から離れた位置に配置されている、請求項3に記載の半導体装置。
- 前記第1の凹部を挟んで対向する前記ボディ領域同士は、平面的に見て前記第1の凹部と、前記第1の凹部と隣接する他の第1の凹部とに挟まれる領域において互いに接続されている、請求項1〜4のいずれか1項に記載の半導体装置。
- 前記基板には、前記一方の主表面上に開口し、第3の側壁面を有する第3の凹部がさらに形成されており、
前記基板は、前記第3の凹部の前記第3の側壁面に接触し、かつ前記ボディ領域と接触して配置された第2導電型の電界緩和領域をさらに含む、請求項1〜5のいずれか1項に記載の半導体装置。 - 前記電界緩和領域の底面は前記第1の凹部の第1の底壁面よりも前記一方の主表面から離れた位置に配置されている、請求項6に記載の半導体装置。
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