JP2013197531A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP2013197531A
JP2013197531A JP2012066194A JP2012066194A JP2013197531A JP 2013197531 A JP2013197531 A JP 2013197531A JP 2012066194 A JP2012066194 A JP 2012066194A JP 2012066194 A JP2012066194 A JP 2012066194A JP 2013197531 A JP2013197531 A JP 2013197531A
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resin
semiconductor chip
semiconductor device
protective resin
bonding wire
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JP2012066194A
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Japanese (ja)
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JP2013197531A5 (enExample
Inventor
Takayuki Mihara
敬之 三原
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Sharp Corp
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Sharp Corp
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Priority to JP2012066194A priority Critical patent/JP2013197531A/ja
Publication of JP2013197531A publication Critical patent/JP2013197531A/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP2012066194A 2012-03-22 2012-03-22 半導体装置およびその製造方法 Pending JP2013197531A (ja)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140145403A (ko) * 2013-06-13 2014-12-23 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 시스템
EP3163610A1 (en) * 2015-11-02 2017-05-03 MediaTek Inc. Semiconductor package with coated bonding wires
CN107403782A (zh) * 2016-05-20 2017-11-28 英飞凌科技股份有限公司 芯片封装体、形成芯片封装体的方法和形成电接触结构的方法
FR3058260A1 (fr) * 2016-11-03 2018-05-04 Stmicroelectronics (Grenoble 2) Sas Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique
JP2019009171A (ja) * 2017-06-21 2019-01-17 スタンレー電気株式会社 半導体装置
US10224306B2 (en) 2016-11-03 2019-03-05 Stmicroelectronics (Grenoble 2) Sas Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device
US10847488B2 (en) 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
CN112292766A (zh) * 2018-06-04 2021-01-29 雷莱昂等离子有限责任公司 具有电陶瓷部件的装置

Citations (14)

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Publication number Priority date Publication date Assignee Title
JPS61111569A (ja) * 1984-11-06 1986-05-29 Shin Etsu Chem Co Ltd 樹脂封止半導体装置
JPS61268464A (ja) * 1985-05-23 1986-11-27 Kyocera Corp サ−マルプリントヘツド
JPS6224650A (ja) * 1985-07-24 1987-02-02 Hitachi Vlsi Eng Corp 半導体装置
JPS6297360A (ja) * 1985-10-24 1987-05-06 Mitsubishi Metal Corp 半導体装置のボンデイングワイヤ用表面被覆高純度銅極細線
JPH0582678A (ja) * 1991-09-24 1993-04-02 Sanyo Electric Co Ltd 混成集積回路
JP2001226565A (ja) * 2000-12-25 2001-08-21 Nitto Denko Corp 半導体装置
JP2003092379A (ja) * 2001-09-18 2003-03-28 Hitachi Ltd 半導体装置
JP2003261576A (ja) * 2002-03-08 2003-09-19 Shin Etsu Chem Co Ltd 有機ケイ素化合物の精製方法及び硬化性シリコーン組成物
JP2004064033A (ja) * 2001-10-23 2004-02-26 Sumitomo Electric Wintec Inc ボンディングワイヤー
JP2006241411A (ja) * 2005-03-07 2006-09-14 Nitto Denko Corp 半導体封止用エポキシ樹脂組成物およびその製法ならびにそれを用いた半導体装置
JP2009263601A (ja) * 2008-04-30 2009-11-12 Hitachi Chem Co Ltd 封止用エポキシ樹脂成形材料及び電子部品装置
JP2010157695A (ja) * 2008-12-29 2010-07-15 Jin Imu Myun チップパッケージ化における保護薄膜コーティング
WO2010147187A1 (ja) * 2009-06-18 2010-12-23 ローム株式会社 半導体装置
WO2011070739A1 (ja) * 2009-12-07 2011-06-16 住友ベークライト株式会社 半導体封止用エポキシ樹脂組成物、その硬化体及び半導体装置

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61111569A (ja) * 1984-11-06 1986-05-29 Shin Etsu Chem Co Ltd 樹脂封止半導体装置
JPS61268464A (ja) * 1985-05-23 1986-11-27 Kyocera Corp サ−マルプリントヘツド
JPS6224650A (ja) * 1985-07-24 1987-02-02 Hitachi Vlsi Eng Corp 半導体装置
JPS6297360A (ja) * 1985-10-24 1987-05-06 Mitsubishi Metal Corp 半導体装置のボンデイングワイヤ用表面被覆高純度銅極細線
JPH0582678A (ja) * 1991-09-24 1993-04-02 Sanyo Electric Co Ltd 混成集積回路
JP2001226565A (ja) * 2000-12-25 2001-08-21 Nitto Denko Corp 半導体装置
JP2003092379A (ja) * 2001-09-18 2003-03-28 Hitachi Ltd 半導体装置
JP2004064033A (ja) * 2001-10-23 2004-02-26 Sumitomo Electric Wintec Inc ボンディングワイヤー
JP2003261576A (ja) * 2002-03-08 2003-09-19 Shin Etsu Chem Co Ltd 有機ケイ素化合物の精製方法及び硬化性シリコーン組成物
JP2006241411A (ja) * 2005-03-07 2006-09-14 Nitto Denko Corp 半導体封止用エポキシ樹脂組成物およびその製法ならびにそれを用いた半導体装置
JP2009263601A (ja) * 2008-04-30 2009-11-12 Hitachi Chem Co Ltd 封止用エポキシ樹脂成形材料及び電子部品装置
JP2010157695A (ja) * 2008-12-29 2010-07-15 Jin Imu Myun チップパッケージ化における保護薄膜コーティング
WO2010147187A1 (ja) * 2009-06-18 2010-12-23 ローム株式会社 半導体装置
WO2011070739A1 (ja) * 2009-12-07 2011-06-16 住友ベークライト株式会社 半導体封止用エポキシ樹脂組成物、その硬化体及び半導体装置

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140145403A (ko) * 2013-06-13 2014-12-23 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 시스템
KR102063508B1 (ko) 2013-06-13 2020-01-08 엘지이노텍 주식회사 발광 소자 및 이를 구비한 조명 시스템
EP3163610A1 (en) * 2015-11-02 2017-05-03 MediaTek Inc. Semiconductor package with coated bonding wires
CN106941098A (zh) * 2015-11-02 2017-07-11 联发科技股份有限公司 半导体封装及其制造方法
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