CN101388375A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN101388375A
CN101388375A CNA2008101491132A CN200810149113A CN101388375A CN 101388375 A CN101388375 A CN 101388375A CN A2008101491132 A CNA2008101491132 A CN A2008101491132A CN 200810149113 A CN200810149113 A CN 200810149113A CN 101388375 A CN101388375 A CN 101388375A
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China
Prior art keywords
mentioned
electrode
semiconductor device
semiconductor element
lead
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CNA2008101491132A
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English (en)
Inventor
井口知洋
西内秀夫
樋口和人
木谷智之
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Toshiba Corp
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Toshiba Corp
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Publication of CN101388375A publication Critical patent/CN101388375A/zh
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Abstract

本发明提供一种可靠性高并且容易制造，同时不增大半导体器件的大小就能够进一步降低内部电阻的半导体器件及其制造方法。具备：半导体元件(2)、引线(3)、将半导体元件(2)的电极(2a)和引线(3)电连接起来的布线构件(4)，其中布线构件(4)至少被具有导电性的材料覆盖。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，特别涉及能够降低半导体元件的电极和引线(lead)的电极之间的电阻的半导体器件及其制造方法。
背景技术
作为半导体器件的一个例子，可以列举在电流的开关和放大时使用的包含场效应晶体管的晶体管封装。在该晶体管封装中，半导体元件上的电极和引线的电极通过由金(Au)、铝(Al)等具有导电性的金属形成的多条导线(wire)而电连接。
在近年的半导体市场上，要求高速动作且具有高处理能力，同时动作中的消耗电力低的半导体器件。为了克服这样的相反的2个课题，半导体器件的电路正在被微小化，同时为了在半导体器件全体中有效地利用所供给的电力，内部电阻(ON电阻)正在被低电阻化。
作为该内部电阻的例子，可以利用将半导体元件和引线连接起来的布线构件的电阻成分、该布线构件和各电极之间的连接电阻成分。通常使用金属导线作为该布线构件，但相对于半导体器件全体的内部电阻值，该金属导线的电阻大到无法无视的程度。因此，如果即使使用金属导线也能够降低与金属导线相关的电阻，则还能够降低半导体元件的电极和引线的电极的连接电阻成分。
因此，例如可以考虑金属导线的加粗或多线，但由于相邻的金属导线之间的短路、安装条数和安装空间的限制，所以在技术上会产生难点。特别地如果采用粗线，则变得无法容易地弯曲，循环成本变高。进而，对于半导体元件上的电极和引线的电极之间的距离，为了在设计上具有自由度的同时吸收金属导线的弯曲，作为结果，必须提高半导体器件的整体成本。
另一方面，作为降低金属导线自身的电阻值的方法，可以考虑将形成金属导线的金属材料变更为电阻比金(Au)、铝(Al)低的材料。但是，在该方法中，从成本方面考虑，由于可以使用的金属种类有限，并且接合部分的可靠性不高，因此难以采用。
作为用于解决这样的问题的一个方法，在以下的专利文献1或专利文献2中，为了谋求半导体器件全体的低电阻化，提出了使用具有导电性的平板状的金属材料，将半导体元件的电极和引线的电极电连接起来的半导体器件。即，通过该方法扩大半导体元件的电极和引线的电极之间的电流的流路截面面积，因此能够降低电极和引线之间的电阻。
专利文献1：专利第3240292号公报
专利文献2：特开2002-76195号公报
但是，在上述专利文献1所揭示的发明中，用金属导线将半导体元件的栅电极和引线之间连接起来，因此从以上理由出发，降低半导体器件内部的电阻是有限的。
另外，上述专利文献1和专利文献2主要着眼于通过使用具有导电性的平板状的金属材料来降低半导体器件的电阻，而对于使用了没有使用平板状的金属材料的金属导线的半导体器件，则完全没有揭示降低电阻的方法。进而，在上述专利文献1和专利文献2中，并没有涉及在使用平板状的金属材料的情况下进一步降低电阻的方法。
发明内容
本发明就是为了解决上述问题而提出的，本发明的目的在于：提供一种可靠性高并且容易制造，同时不增大半导体器件的大小就能够进一步降低内部电阻的半导体器件及其制造方法。
本发明的实施例的第一特征在于：在半导体器件中，具备半导体元件、引线、将半导体元件的电极和引线电连接起来的布线构件，布线构件至少被具有导电性的材料覆盖。
本发明的实施例的第二特征在于：在半导体器件中，具备：衬底；设置在衬底上的端子；经由设置在衬底上的贯通孔(through whole)布线与端子电连接的外部电极；形成在端子上的凸点电极；经由凸点(bump)电极与端子电连接的半导体元件；设置在端子、外部电极、凸点电极以及半导体元件上，覆盖与凸点电极连接的电极的金属膜。
本发明的实施例的第三特征在于：在半导体器件的制造方法中，用布线构件将设置在半导体元件上的电极和设置在引线上的电极电连接起来的工序；用导电性材料覆盖布线构件的工序；将半导体元件、引线和被导电性材料覆盖的布线构件密封的工序。
本发明的实施例的第四特征在于：在半导体器件的制造方法中，在塞住设置在衬底上的贯通孔布线的位置上设置外部电极的工序；在能够经由贯通孔布线与外部电极电连接的位置上设置端子的工序；在半导体元件上形成电极的工序；经由凸点电极将电极与端子电连接起来的工序；用导电性材料覆盖外部电极、端子、凸点电极和电极的工序；将形成在衬底上的端子、凸点电极、电极和半导体元件密封的工序。
根据本发明，能够提供一种可靠性高并且容易制造，同时不增大半导体器件的大小就能够进一步降低内部电阻的半导体器件及其制造方法。
附图说明
图1是表示本发明的实施例1的半导体器件全体的切断截面图。
图2是说明本发明的实施例1的半导体器件的制造方法的第一工序截面图。
图3是说明本发明的实施例1的半导体器件的制造方法的第二工序截面图。
图4是说明本发明的实施例1的半导体器件的制造方法的第三工序截面图。
图5是表示本发明的实施例2的半导体器件全体的切断截面图。
图6是说明本发明的实施例2的半导体器件的制造方法的第一工序截面图。
图7是说明本发明的实施例2的半导体器件的制造方法的第二工序截面图。
图8是说明本发明的实施例2的半导体器件的制造方法的第三工序截面图。
具体实施方式
以下，参考附图，详细说明本发明的实施例。
(实施例1)
首先，说明实施例1的半导体器件的结构。本发明的实施例的半导体器件1如图1的半导体器件1的切断截面图所示那样，具备：半导体元件2；具有与设置在半导体元件2上的电极2a连接的电极的引线3；被将半导体元件2的电极2a和引线3的电极3a电连接起来的导电性材料C覆盖的布线构件4。另外，包含半导体元件2、引线3、布线构件4的半导体器件1用密封树脂(以下表示为“外围器5”)气密地密封其大致外部全体。
半导体元件2经由芯片焊接材料D被连接到引线3上。另外，在半导体元件2的和引线3相接的面相反的面上，形成有与设置在引线3上的电极3a连接的电极2a(例如源电极和栅电极)。另外，作为该电极2a的材料，可以适合地使用金(Au)、铜(Cu)、铝(Al)等。另外，作为芯片焊接材料D，例如可以使用银膏焊料等具有导电性的接合材料。另外，其涂抹方法也可以是分配(dispense)、屏幕印刷转印等任意的方法。
在电极2a上，例如形成有具有导电性的焊料等接合构件J，该结合构件J和布线构件4的一端连接。在本发明的实施例的半导体器件1中，通过球形结合(ballbonding)进行电极2a和布线构件4的连接。另一方面，布线构件4的另一端与引线3的电极3a连接。同时使用超声波地通过热压接来进行该布线构件4的另一端和电极3a的连接。
引线3起到作为所谓的布线衬底的作用，除了引线3以外，例如也可以采用陶瓷布线衬底或树脂衬底作为衬底材料。
考虑到电极2a和电极3a之间的电阻等，在本发明的实施例的半导体器件1中，布线构件4使用金导线。进而，使用导电性材料C的的连续膜，覆盖该布线构件4(金导线)的表面。通过用导电性材料C的连续膜覆盖布线构件4，能够使布线构件4变粗。并且，由于并不是要通过使用直径粗的金导线来使线变粗，所以在避免成本上升的同时能够使线变粗。在此，对金导线进行镀铜(Cu)处理，来进行基于导电性材料C的覆盖。另外，覆盖在金导线上的导电性材料C的种类并没有特别限定，另外覆盖方法除了电镀处理以外，例如也可以通过蒸镀或喷溅等的方法。
接着，使用图2～图4，说明本发明的实施例1的半导体器件1的制造方法。
首先，如图2所示那样，经由芯片焊接材料D将半导体元件2连接到引线3上。在此，已经在半导体元件2上形成有电极2a。另外，在引线3上也形成有电极3a。
接着，如图3所示那样，在半导体元件2的电极2a上设置接合构件J，在与引线3的电极3a之间通过导线接合(wire bonding)而电连接布线构件4(金导线)。作为该金导线的直径，例如可以使用25微米的金导线。
在此基础上，在与引线3上连接的半导体元件2、引线3以及布线构件4上覆盖导电性材料C的连续膜。所覆盖的导电性材料C例如可以采用铜(Cu)等，只要是具备导电性的材料，就可以采用。另外，覆盖的方法也可以是电镀处理、蒸镀、喷溅等任意的方法。例如，作为一个例子，可以列举将半导体元件2等浸渍到铜(Cu)的电镀液中的方法(并没有图示该状态)。在此基础上，将一个电极连接到引线3上，在与另一个电极之间施加电场。在电镀处理后，经过未图示的洗净、干燥的工序，如图4所示那样，在布线构件4等上覆盖电镀膜(基于导电性材料C的连续膜)。可以任意地决定对布线构件4等施加的电镀膜的厚度。
不特别进行掩模(masking)，不对用于连接半导体元件2和引线3的芯片焊接材料D和半导体元件2实施电镀。这是因为：对半导体元件2等的电镀处理的密接性低，另外半导体元件2的电阻大因此即使施加电场也难以流过电等。另外，由于可以至少对布线构件4实施电镀，所以可以在不希望形成电镀的被膜的位置进行掩模使得不被电镀。
如果实施电镀处理，则能够在布线构件4上覆盖导电性材料C，因此能够使布线构件4的线变粗，并且与布线构件4的另一端和引线3的电极3a之间的连接相比更确实。即，如上所述，同时使用超声波地通过热压接来进行布线构件4的另一端和电极3a的连接。严谨地说，由于将圆筒状的布线构件4与平面的电极3a连接，所以在布线构件4和电极3a之间产生间隙。这样的间隙的存在增大了布线构件4和电极3a之间的接触电阻，但通过实施电镀而将该间隙掩埋，能够将布线构件4完全连续地与电极3a连接。由此，减小了布线构件4和电极3a之间的接触电阻。
然后，通过外围器5覆盖半导体元件2、引线3、布线构件4。对于该外围器5，只要不是阻碍半导体元件的特性的材料，其种类并没有限制。另外，外围器5的形状只要是至少覆盖而保护半导体元件2、布线构件4，则其形状可以任意决定。进而，在对引线3的形状进行了成形的基础上进行切断(cut)。通过这样的制造工序，能够得到图1所示那样的半导体器件1。
这样，在用金属导线连接了半导体元件和引线的各电极之间的半导体器件中，提供一种通过在该金属导线上覆盖导电性材料，能够使得可靠性变高并且容易制造，同时不增大半导体器件的大小就能够进一步降低内部电阻的半导体器件及其制造方法。
(实施例2)
接着，说明本发明的实施例2。另外，在实施例2中，对与在上述实施例1中说明了的结构要素相同的结构要素附加相同的符号，由于同一结构要素的说明重复，所以省略。
实施例1的半导体器件1用金属导线将半导体元件2的电极2a和引线3的电极3a之间连接起来。在实施例2中的半导体器件10中，通过球形凸点进行电极2a和电极3a的连接，即采用了所谓的倒装片结合连接的方式。
如图5的半导体器件10的切断截面图，半导体器件10具备：衬底11；设置在衬底11上的端子12；经由设置在衬底11上的贯通孔布线H与端子12电连接的外部电极13；形成在端子12上的凸点电极14；经由凸点电极14与端子12电连接的半导体元件2。另外，在端子12、外部电极13、凸点电极14和设置在半导体元件2上并与凸点电极14连接的电极2a上，覆盖有金属膜S。形成在衬底11上的端子12、凸点电极14、电极2a、半导体元件2被外围器5密封。
衬底11例如可以是陶瓷布线衬底、树脂衬底、引线的任意一个。在该衬底11上，在其相对的面上分别连接有端子12和外部电极13。端子12和外部电极13经由贯通设置在衬底11上的贯通孔布线H电连接。进而，在端子12上形成有凸点电极14，通过将该凸点电极14和半导体元件2的电极2a连接起来，将形成在端子12上的电极和电极2a电连接起来。
接着，使用图6～图8，说明本发明的实施例2的半导体器件10的制造方法。
首先，准备衬底11。在该衬底11上，设置有贯通孔布线H，使得在规定的位置贯通衬底11。另外，在衬底11的一个面上连接外部电极13，使得塞住该贯通孔布线H。在将外部电极13连接到衬底11上时，可以例如涂抹焊料膏等，使用适合于衬底11等的连接构件。
接着，将端子12连接到与外部电极13所连接的面相对的衬底11的面上。该端子12在基板11上的连接位置是经由贯通孔布线H与外部电极13电连接的位置。进而，在该端子12上，形成凸点电极14。另一方面，在另一工序中，在半导体元件2上形成电极2a。如果假设形成该电极2a的面为半导体元件2的上面，则该半导体元件2的上面朝向为与衬底11(端子12)相对，使半导体元件2向图7所示的箭头方向移动，将凸点电极14夹在其间，通过倒装片连接电极2a和端子12。
在此基础上，在将衬底11和半导体元件2连接起来的状态下，覆盖导电性材料C的连续膜。例如使其浸渍在铜(Cu)的电镀液中(并没有图示该状态)。电镀处理的方法例如可以采用电场电镀等方法。另外，可以任意地决定电镀厚度。电镀处理后，经过未图示的洗净、干燥的工序，如图8所示那样，在除了衬底11和半导体元件2以外的部分上实施电镀。由此，使金属膜S覆盖作为电流路径的外部电极13、端子12、凸点电极14、电极2a。另外，由于只要对这些部分实施电镀就可以，所以可以在不希望形成基于电镀的被膜的位置实施掩模。
然后，通过外围器5覆盖衬底11上的端子12、凸点电极14、电极2a、半导体元件2。对于该外围器5，如上所述，只要不是阻碍半导体元件的特性的材料，其种类并没有限制，并且可以任意地决定外围器5的形状。经过这样的制造工序，能够得到图5所示那样的半导体器件10。
这样，能够提供一种可靠性高并且容易制造，同时不增大半导体器件的大小就能够进一步降低内部电阻的半导体器件及其制造方法。
特别地在实施例2的半导体器件中，在外部电极、端子、凸点电极、电极上覆盖金属膜S，与以前的进行倒装片连接而制造出的半导体器件相比，能够扩大电流路径，因此能够提供一种可以进一步降低内部电阻的半导体器件及其制造方法。
另外，本发明并不只限于上述实施例自身，在实施阶段，在不脱离其宗旨的范围内，可以对构成要素进行变形并具体化。另外，通过适当地组合上述实施例所揭示的多个构成要素，能够形成各种发明。例如，也可以从实施例所示的全部构成要素中，删除若干个构成要素。进而，可以适当地组合不同的实施例的构成要素。

Claims (9)

1.一种半导体器件，其特征在于包括：
半导体元件；
引线；
将上述半导体元件的电极和上述引线电连接起来的布线构件，其中
上述布线构件至少被具有导电性的材料覆盖。
2.根据权利要求1所述的半导体器件，其特征在于：
上述布线构件是金导线。
3.根据权利要求1或2所述的半导体器件，其特征在于：
覆盖上述布线构件的导电性材料是金属，是通过电镀形成的连续膜。
4.一种半导体器件，其特征在于包括：
衬底；
设置在上述衬底上的端子；
经由设置在上述衬底上的贯通孔布线与上述端子电连接的外部电极；
形成在上述端子上的凸点电极；
经由上述凸点电极与上述端子电连接的半导体元件；
设置在上述端子、上述外部电极、上述凸点电极以及上述半导体元件上，覆盖与上述凸点电极连接的电极的金属膜。
5.根据权利要求4所述的半导体器件，其特征在于：
通过电镀形成上述金属膜。
6.一种半导体器件的制造方法，其特征在于包括：
用布线构件将设置在半导体元件上的电极和设置的引线上的电极电连接起来的工序；
用导电性材料覆盖上述布线构件的工序；
将上述半导体元件、上述引线和被上述导电性材料覆盖的上述布线构件密封的工序。
7.根据权利要求6所述的半导体器件的制造方法，其特征在于：
上述用导电性材料覆盖布线构件的工序是：不进行掩模，而通过电镀覆盖上述布线构件的工序。
8.一种半导体器件的制造方法，其特征在于包括：
在塞住设置在衬底上的贯通孔布线的位置上设置外部电极的工序；
在能够经由上述贯通孔布线与上述外部电极电连接的位置上设置端子的工序；
在半导体元件上形成电极的工序；
经由凸点电极将上述电极与上述端子电连接起来的工序；
用导电性材料覆盖上述外部电极、上述端子、上述凸点电极和上述电极的工序；
将形成在上述衬底上的上述端子、上述凸点电极、上述电极和上述半导体元件密封的工序。
9.根据权利要求8所述的半导体器件的制造方法，其特征在于：
上述用导电性材料覆盖上述外部电极、上述端子、上述凸点电极和上述电极的工序是：实施电镀处理，在上述外部电极、上述端子、上述凸点电极和上述电极上覆盖导电性材料的连续膜的工序。
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