CN101416311A - 无夹片和无引线半导体管芯封装及其制造方法 - Google Patents

无夹片和无引线半导体管芯封装及其制造方法 Download PDF

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CN101416311A
CN101416311A CNA2006800505620A CN200680050562A CN101416311A CN 101416311 A CN101416311 A CN 101416311A CN A2006800505620 A CNA2006800505620 A CN A2006800505620A CN 200680050562 A CN200680050562 A CN 200680050562A CN 101416311 A CN101416311 A CN 101416311A
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semiconductor element
lead frame
frame structure
die package
semiconductor die
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CN101416311B (zh
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A·V·C·杰瑞扎
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Fairchild Semiconductor Corp
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Abstract

公开了一种制造半导体管芯封装的方法。在某些实施方式中，该方法包括使用包括至少一个具有引线表面的引线结构的引线框结构。具有第一表面和第二表面的半导体管芯被附连到该引线框结构上。该半导体管芯的第一表面与引线表面基本在同一平面上，且该半导体管芯的第二表面与引线框结构耦连。导电材料层在引线表面和半导体管芯的第一表面上形成以使至少一个引线结构与半导体管芯电耦连。

Description

无夹片和无引线半导体管芯封装及其制造方法
发明背景
有许多种半导体管芯封装。许多半导体封装使用引线来使半导体管芯上的源极区和栅极区与引线框架上的源极引线和栅极引线电连接。许多其它半导体封装使用夹片代替引线来形成与外部终端的外部连接。这种半导体管芯封装有时被称为“无引线”封装。典型的无引线封装包括与半导体管芯附连的夹片。无引线半导体管芯封装通常是优选的，因为它们比针对终端连接使用引线的半导体管芯封装具有更好的热特性和电特性。
虽然夹片接合的半导体封装是有用的，但仍可作一些改进。例如，一个问题是需要夹片接合的半导体封装平台的高成本。夹片的成本可与引线框的成本一样高。此外，夹片接合需要昂贵的定制的夹片连接器和点胶系统。因而，夹片连接封装具有非常高的材料和制造成本。
夹片接合存在的另一问题是在夹片和半导体管芯之间涂敷不一致的或不均匀量的焊料的问题。当不一致的或不均匀量的焊料用在管芯和夹片之间时，该所得封装可显示较差的性能。并且，由于微引线封装(MLP)组件的特征尺寸日益变小，设计受到蚀刻和半蚀刻引线框技术的金属到金属间隙和尺寸公差能力的限制。
本发明的各个实施方式个别地和共同地解决以上问题和其它问题。
发明概要
本发明的各个实施方式涉及半导体管芯封装以及制造半导体管芯封装的方法。本发明的一些实施方式涉及微引线封装(MLP)。然而，本发明的各个实施方式最好可被扩展到诸如小外形(SO)封装的其它类型的半导体管芯封装。
本发明的一个实施方式涉及一种形成半导体管芯封装的方法，该方法包括：获取包括至少一个具有引线表面的引线结构的引线框结构；将具有第一表面和第二表面的半导体管芯附连到引线框结构，其中该半导体管芯的第一表面与引线表面基本在同一平面上，且该半导体管芯的第二表面与引线框结构耦连；以及在引线表面和该半导体管芯的第一表面上形成一导电材料层来使至少一个引线结构与该半导体管芯电耦连。
本发明的另一实施方式涉及一种半导体管芯封装，该半导体管芯封装包括：包括至少一个具有引线表面的引线结构的引线框结构；该引线框结构上的具有第一表面和第二表面的半导体管芯，其中该半导体管芯的第一表面与引线表面基本在同一平面上且该半导体管芯的第二表面与引线框结构耦连；以及在该引线表面和该半导体管芯的第一表面上的且使至少一个引线结构与该半导体管芯的第一表面耦连的导电薄膜。
附图简要描述
图1示出例示根据本发明一实施方式的方法的流程图。
图2(a)示出根据本发明一实施方式的引线框结构的横截面侧视图。
图2(a)＇示出根据本发明一实施方式的引线框结构的俯视图。
图2(b)示出根据本发明一实施方式的安装于引线框结构上的半导体管芯的横截面侧视图。
图2(b)＇示出根据本发明一实施方式的安装于引线框结构上的半导体管芯的俯视图。
图2(c)示出用制模材料安装于引线框结构上的半导体管芯的横截面侧视图。
图2(c)＇示出用制模材料安装于引线框结构上的半导体管芯的俯视图。
图2(d)示出用制模材料和导电材料层安装于引线框结构上的半导体管芯的横截面侧视图。
图2(d)＇示出用制模材料和导电材料层安装于引线框结构上的半导体管芯的俯视图。
图2(e)示出用制模材料、导电材料层、以及焊膏的叠加层安装于引线框结构上的半导体管芯的横截面侧视图。
图2(e)＇示出用制模材料、导电材料层、以及焊膏的叠加层安装于引线框结构上的半导体管芯的的俯视图。
图3示出例示根据本发明另一实施方式的方法的流程图。
图4(a)示出根据本发明一实施方式的安装于引线框结构上的半导体管芯的横截面侧视图。
图4(a)＇示出根据本发明一实施方式的安装于引线框结构上的半导体管芯的俯视图。
图4(b)示出根据本发明一实施方式的安装于引线框结构上的经修改的半导体管芯的横截面侧视图。
图4(b)＇示出根据本发明一实施方式的安装于引线框结构上的经修改的半导体管芯的俯视图。
图4(c)示出用非导电掩模安装于引线框结构上的半导体管芯的横截面侧视图。
图4(c)＇示出用非导电掩模安装于引线框结构上的半导体管芯的俯视图。
图4(d)示出用非导电掩模安装于引线框结构上的经修改的半导体管芯的横截面侧视图。
图4(d)＇示出用非导电掩模安装于引线框结构上的经修改的半导体管芯的俯视图。
图4(e)示出用非导电掩模和用于源极连接的导电材料层安装于引线框结构上的半导体管芯的横截面侧视图。
图4(e)＇示出用非导电掩模和用于源极连接的导电材料层安装于引线框结构上的半导体管芯的俯视图。
图4(f)示出用非导电掩模、用于源极连接的导电材料层和用于栅极连接的引线接合安装于引线框结构上的半导体管芯的横截面侧视图。
图4(f)＇示出用非导电掩模、用于源极连接的导电材料层和用于栅极连接的引线接合安装于引线框结构上的半导体管芯的俯视图。
图4(g)示出用非导电掩模、用于源极连接的导电材料层、用于栅极连接的引线接合和半导体封装上的封装剂安装于引线框结构上的半导体管芯的横截面侧视图。
图4(h)示出用非导电掩模的连续条、用于源极和栅极连接的导电材料层安装于引线框结构上的经修改的半导体管芯的横截面侧视图。
图4(h)＇示出用非导电掩模的连续条、用于源极和栅极连接的导电材料层安装于引线框结构上的经修改的半导体管芯的俯视图。
图4(i)示出用两条非传导掩模、用于源极和栅极连接的导电材料层、以及叠加的焊膏安装于引线框结构上的经修改的半导体管芯的横截面侧视图。
图4(i)＇示出用两条非传导掩模、用于源极和栅极连接的导电材料层、以及叠加的焊膏安装于引线框结构上的经修改的半导体管芯的俯视图。
图4(j)示出用两条非传导掩模、用于源极和栅极连接的导电材料层、叠加的焊膏和半导体封装上的封装剂安装于引线框结构上的经修改的半导体管芯的横截面侧视图。
图5(a)示出根据本发明一实施方式的包括两个安装于引线框结构上的半导体管芯的多管芯平台的俯视图。
图5(b)示出包括两个用制模材料安装于引线框结构上的半导体管芯的多管芯平台的俯视图。
图5(c)示出包括两个用制模材料和导电材料安装于引线框结构上的半导体管芯的多管芯平台的俯视图。
图5(d)示出包括两个用制模材料、导电材料层、以及焊膏的叠加层安装于引线框结构上的半导体管芯的多管芯平台的俯视图。
图5(e)示出包括两个用制模材料、导电材料层、焊膏的叠加层、以及半导体封装上的封装剂安装于引线框结构上的半导体管芯的多管芯平台的俯视图。
图5(f)示出包括两个用制模材料、导电材料层、焊膏的叠加层、以及半导体封装上的封装剂安装于引线框结构上的半导体管芯的多管芯平台的横截面侧视图。
详细描述
本发明的各个实施方式通过引线在封装内提供完全的或基本完全的无夹片和无引线连接，同时保留在引线接合封装上的夹片接合封装的优点来解决以上问题和其它问题。这些优点包括低导通电阻(RDSon)和高载流能力。
这种封装的另一益处是完全的或基本完全的无夹片和无引线平台的低成本。因为夹片的成本通常和引线框结构的成本一样高，所以无夹片封装将相当大地降低用于半导体管芯封装的平台的材料成本。此外，虽然夹片接合需要昂贵的定制的夹片接合器和点胶系统，但是本发明的各个实施方式可以只使用标准的丝网印刷机。因而，制造成本也被降低。因此，与现存标准封装的简易替换相关联的成本也被降低。
根据本发明一实施方式的无引线和无夹片封装不使用或显著减少使半导体管芯中的电气器件的输入和/或输出端子与引线框结构连接所需的引线或夹片结构的数量。在根据本发明一实施方式的半导体管芯封装中，代替夹片或引线接合，半导体管芯封装包括在引线框结构和半导体管芯上的导电材料层来使引线框结构中的至少一个引线结构与半导体管芯的端子电耦连。
图1示出例示根据本发明一实施方式的示例性工艺流程的流程图。以下参考图2(a)到2(e)＇对该流程图的每一步骤进行更详细地描述。
首先，如图1的步骤1(a)所示，提供一引线框结构。术语“引线框结构”可指的是从引线框得到的或与引线框一样的结构。图2(a)示出引线框结构20的横截面视图，而图2(a)＇示出引线框结构20的俯视图。每个引线框结构可包括两条或多条具有引线表面20(a)和管芯附着区20(b)的引线。该引线从管芯附着区20(b)横向地延伸。单个引线框结构可包括栅极引线结构20(c)和源极引线结构20(d)。在图2(a)＇中，G、S和D的示例性标记分别指的是栅极、源极和漏极引线指。栅极和源极引线指与结构在最终形成的半导体封装中相互电隔离。
引线框结构20可以包括任何适当的材料。示例性的引线框结构材料包括诸如铜、铝、金等金属及其合金。引线框结构还可以包括诸如金、铬、银、钯、镍等电镀层的电镀层。该引线框结构20还可具有任何适当厚度，包括约小于1mm(例如约小于0.5mm)的厚度。
引线框结构可使用常规工艺来蚀刻和/或形成图案，以定形该引线框结构的引线或其它各部分。例如，引线框结构可通过蚀刻连续的导电板以形成预定图案来形成。在蚀刻之前或之后，引线框结构还可被压印以使引线框结构的管芯附连表面相对引线框结构的引线的引线表面来下移设置。如果使用压印，则引线框结构可以是由系杆连接的引线框结构阵列中的多个引线框结构中的一个。引线框结构阵列还可被切开以使引线框结构与其它引线框结构分离。作为切开的结果，诸如源极引线和栅极引线的在最终半导体管芯封装中的引线框结构的各个部分可相互电去耦和机械去耦。因而，引线框结构可以是连续的金属结构或不连续的金属结构。
在获得引线框结构之后，至少一个半导体管芯被安装和附连到该引线框结构上，如图1的步骤1(b)所示。图2(b)示出安装在引线框结构20上的具有第一表面32(a)和第二表面32(b)的半导体管芯30。该半导体管芯30的第二表面32(b)靠近该引线框结构20的管芯附连区20(b)。任何适合的粘合剂或焊料可用来在该引线框结构20的管芯附连区20(b)处使半导体管芯30与引线框结构20附连。
半导体管芯30可包括在该半导体管芯30的第一表面32(a)上的栅极区30(a)和源极区30(b)，以及在该半导体管芯30的第二表面32(b)上的漏极区30(c)。该栅极区30(a)和源极区30(b)在图2(b)的俯视图中被示出。在本发明的较佳实施方式中，半导体管芯30的第一表面32(a)与引线框结构20的引线表面20(a)基本共面，如由图2(b)中的虚线所示。
半导体管芯30可是任何适合的半导体器件。适合的器件可包括垂直的或水平的器件。垂直的器件至少具有在该管芯的一侧的一个输入和在该管芯的另一侧的一个输出使得电流可以垂直地流经该管芯。水平器件包括在该管芯的一侧的至少一个输入和在该管芯的同一侧的至少一个输出使得电流水平地流经该管芯。在与本申请一样被转让给同一个受让人且为了所有目的被完整纳入于此以供参考的美国专利申请No.6,274,905和6,351,018中也对示例性垂直功率器件进行了描述。
垂直功率晶体管包括VDMOS晶体管和垂直双极型晶体管。VDMOS晶体管是具有两个或多个通过扩散形成的半导体区的MOSFET。它具有源极区、漏极区、以及栅极。因为源极区和漏极区在半导体管芯的相反表面上，所以该器件是垂直的。该栅极可以是沟槽栅极结构或平面栅极结构，且与源极区在同一表面上形成。沟槽栅极结构是优选的，因为沟槽栅极结构比平面栅极结构更窄且占据更少空间。在运行期间，在VDMOS器件中从源极区流向漏极区的电流与管芯表面基本垂直。
以下相关于在半导体管芯30与在管芯附连区20(b)的引线框结构20附连之后的半导体管芯封装工艺，对本发明的两个较佳实施方式进行进一步描述。
I.工艺流程A
在半导体管芯30与引线框结构20附连之后，制模材料40可在引线框结构20和管芯30的至少一部分的周围形成以提供包括该引线框结构20和该管芯30的制模结构，如图1中的步骤1(c)所示。通常制模结构具有比其它结构低的翘曲度和比其高的整体面板刚度。如图2(c)所示，具有第一表面40(a)和第二表面40(b)的制模材料40覆盖引线框结构20。通常，诸如引线表面20(a)的该引线框结构20的至少一个表面与制模材料40的第一表面40(a)基本共面。在图2(c)中示出的较佳实施方式中，半导体管芯30的第一表面32(a)还与引线表面20(a)和模制材料40的第一表面40(a)共用同一平面。在图2(c)＇中示出的制模结构还示出半导体管芯30的栅极区30(a)和源极区30(b)的表面与栅极引线结构20(c)和源极引线结构20(d)的表面都共用同一平面且通过制模材料40暴露。
可使用任何包括膜或带辅助转移模制工艺的适当的模制工艺。例如，在带辅助的、单面模制工艺中，引线框结构30和半导体管芯20被粘附于带结构的附着面。然后该组合被置入模子的模腔中。然后将制模材料40(以液态或半液态形式)引入到在引线框结构20下面的模制腔室，且该制模材料40向上流动并填充引线框结构20的空隙中。一旦制模材料凝固，该带结构、引线框结构20、以及制模材料40就可从腔中除去。在制模材料凝固之前或之后，过剩的制模材料可从引线框结构20的与带结构相反的一侧除去。然后带结构可与引线框结构20和半导体管芯30分离。引线框结构20和半导体管芯30的曾与带结构接触的表面，诸如引线结构20(c)和20(d)与管芯区30(a)和30(b)，通过凝固的制模材料40暴露。在其它实施方式中，可使用两个模制管芯代替带辅助工艺。
在用制模材料40模制引线框结构20和半导体管芯30之后，可执行修边、去毛刺以及去废料工艺。本领域已知的去毛刺和去废料工艺可用来除去过剩的制模材料。
制模材料40可以是诸如基于联苯的材料和多功能交联环氧树脂合成材料的任何适于模制的材料。如果引线框结构20的引线结构20(c)和20(d)不横向地向外延伸超过制模材料40，则该半导体封装可被视为是“无引线”封装。如果引线框结构20的引线结构20(c)和20(d)确实延伸了超过制模材料40，那么该半导体封装可能是“引线封装”。
在半导体管芯30附加到引线框结构20上之后，半导体管芯30的顶面32(a)和/或底面32(b)可与引线框结构的导电区，诸如引线结构20(c)和20(d)电耦连。通常，半导体管芯30和引线框结构的各个导电部分引线接合在一起。可选地，使用了导电夹片来使半导体管芯30与引线框结构20的各个导电部分电耦连。然而，本发明较佳实施方式完全地消除了对引线接合或导电夹片的需要。
作为替换，在本发明的实施方式中，半导体管芯30与引线结构20(c)和20(d)之间的电连接由导电膜或导电材料层在半导体管芯30和引线框结构20的经制模材料40暴露的各个部分上提供，如由图1的步骤1(d)所示。根据图2(d)中示出的较佳实施方式，导电材料50的薄膜或层涂覆制模结构，且引线框结构20和半导体管芯30的经暴露表面共享同一平面。导电材料50具有外部的第一表面50(a)和与引线框结构20、半导体管芯30、以及制模材料40接触的第二表面50(b)。在某些实施方式中，该导电材料50可形成第一导电层。
导电材料50的膜或层可以各种方式形成。示例性成膜工艺包括丝网印刷、气相沉积、辊涂、旋涂、帘幕式淋涂等。也可使用加色或减色工艺。在示例性实施方式中，在导电材料50通过掩模沉积或涂敷之前，制模结构可被置于工作面或带上。然后导电材料50固化，如图1的步骤1(e)所示。当导电材料50凝固时，掩模然后可从制模结构除去或剥落。引线框结构20的先前由掩模覆盖的各个部分将没有导电材料50且因而通过凝固的导电材料50暴露。半导体管芯30和引线框结构20的由丝网印刷暴露的各个部分包括源极引线结构20(d)和半导体30(b)的源极区的一部分，如图2(d)＇所示。半导体管芯30和源极引线结构20(d)的经暴露部分可使随后的焊料印刷或电镀能直接附加于导电材料50之下的表面，且因而锚入导电材料。这将增大电连接的可靠性并减小其电阻，并且还增大导电迹线的横截面。
在本发明一实施方式中，导电材料50起用于随后的焊料印刷和/或电镀的籽晶层或粘合层的作用。随后的如图1的步骤1(f)到1(h)所示的焊料印刷、焊料回流和电镀工艺可进一步改进半导体管芯30与引线结构20(c)和20(d)之间的接触的电性能。随后用焊膏的印刷在图2(e)和2(e)＇中示出。焊膏60的覆盖范围可比导电材料50的覆盖范围大，以使得焊膏60可锚到导电材料50之上并提供更可靠的电连接。在某些实施方式中，焊膏60的层可形成第二导电层。如图所示，有两个分别与栅极和源极连接相对应的分立焊料区。
导电材料50的层和焊膏60的层可具有任何适当厚度。例如，在某些实施方式中，导电材料50的层的厚度可约小于50微米。在某些实施方式中，焊膏60的层的厚度可约小于100微米。
导电层50、随后的焊膏60和/或电镀的覆盖范围可小于引线框20的制模结构、半导体管芯30和制模材料40的大小，以保留半导体封装边缘周围的经暴露模子。这可防止在插件装配期间的焊料桥接。
在半导体管芯30通过导电层50和随后的焊料60和/或电镀层与栅极和源极引线结构电耦连之后，封装材料(未示出)可在整个半导体管芯封装上沉积来保护其组件。该封装材料可包括与前述的诸如联苯材料和多功能交联环氧树脂合成物的制模材料相同或不同类型的材料。在某些实施方式中，封装材料可与制模材料不同。可使用任何适当的封装材料。
II.工艺流程B
图3示出例示根据本发明可选较佳实施方式的示例性工艺流程的流程图。以下参考图4(a)到4(j)＇对该流程图中的每个步骤进行更详细的描述。
图4(a)和4(a)＇示出与由步骤3(a)指示的提供引线框结构20和由步骤3(b)指示的将半导体管芯30附加到引线框结构20上的以上详述的工艺流程A的步骤相同的工艺步骤。半导体管芯30具有第一表面32(a)和第二表面32(b)，且该第二表面32(b)靠近引线框结构20且第一表面32(a)与引线表面20(a)具有同一平面。图4(b)和4(b)＇示出使用经修改的半导体管芯来增大栅极和源极到管芯边缘的间隙的本发明的另一实施方式。图4(b)＇示出经修改的半导体管芯30的经修改的栅极和源极区38的俯视图。
在半导体管芯30附加到引线框结构20之后，不执行如图2(c)所示的在工艺流程A中详述的模制步骤。取而代之地，图3的步骤3(c)指示半导体管芯30和引线框结构20之间的间隙由非导电材料覆盖。该步骤可通过在引线表面20(a)和半导体管芯的第一表面32(a)之间的间隙上印刷焊料掩模或放置带或粘合剂来实现，如图4(c)到4(d)所示。非导电掩模或带70防止后续的导电材料流经引线框结构的表面20(a)和半导体管芯30之间的间隙。
在图4(c)和4(c)＇所示的实施方式中，焊料掩模、非导电粘合剂或带应用70覆盖源极引线结构20(d)和半导体管芯30的源极区30(b)之间的间隙。这种方法允许使用现存的半导体管芯。在图4(d)和4(d)＇中所示的另一实施方式示出图4(b)和4(b)＇的经修改的半导体管芯。焊料掩模、非导电粘合剂或带应用70覆盖用于经修改的半导体管芯实施方式的经修改的栅极和源极区38。
在焊料掩模或非导电粘合剂70被分散或涂敷后，导电材料在半导体封装上被印刷和固化，如图3中的步骤3(d)和3(e)所示。图4(e)和4(e)＇示出导电层80在引线框结构20和半导体管芯30之间提供源极连接。导电材料80在半导体管芯30的源极引线表面20(d)、非导电材料70、以及源极区30(b)上沉积或涂覆来提供引线和半导体管芯之间的电连接。该导电材料80可以是如上针对工艺流程A中的导电材料50的膜或层所述的任何材料且可通过上述任何方法形成。
在本发明一实施方式中，栅极连接可由引线接合提供。例如，引线接合82在图4(f)和4(f)＇中示为将半导体管芯30的栅极区30(a)电连接到引线框结构20的栅极引线结构20(c)。在一替换实施方式中，此栅极连接可由导电材料84的膜或层代替引线接合82提供，如图4(h)＇所示。
图4(h)到图4(i)＇示出具有经修改的栅极和源极区38的经修改的半导体结构。在图4(h)和4(h)＇示出的经修改的半导体结构的实施方式中，非导电层或粘合剂72涂敷在跨越栅极引线结构20(c)和源极引线结构20(d)的单个条中。在图4(i)和4(i)＇示出的经修改的半导体结构的另一实施方式中，非导电层或粘合剂涂敷在两个条74(a)和74(b)中。非导电条74(a)覆盖栅极引线结构20(c)和半导体栅极区30(a)之间的间隙，而非导电条74(b)覆盖源极引线结构20(d)和半导体源极区30(b)之间的间隙。
图3的步骤3(f)＇和3(g)示出对于某些实施方式，焊膏可被印刷在导电材料之上且随后被回流以增强半导体封装的电特性。源极和栅极连接之上的焊膏将减小导电迹线电阻并增大电流处理能力。图4(i)到图4(i)＇示出焊膏90被直接涂敷在导电材料80的膜或层之上。
在本发明一实施方式中，导电材料80将起用于后续的焊膏印刷工艺的籽晶层或粘合层的作用。如在图4(i)＇中示出的焊膏90的覆盖范围还可比导电层80的大，以使得焊料90可锚在导电材料80之上。这将导致可靠的和低电阻的连接。
最后，封装剂100可如图4(g)所示地针对具有布线接合的栅极连接82的实施方式以及如图4(j)所示的针对具有导电层栅极连接84的实施方式覆盖该半导体封装。对于实施方式A，该封装剂材料可包括与诸如联苯材料和多功能交联环氧树脂合成物的制模材料相同或不同类型的材料。
图5(a)到图5(e)示出根据提供多管芯平台的工艺流程A的实施方式的工艺步骤。例如，图5(a)示出其中两个半导体管芯安装在引线框结构不同面上的引线框结构。这些栅极引线结构在管芯的两个面，即200(a)和200(b)上形成。源极引线结构也在该管芯的两个面202(a)和202(b)上。半导体管芯204与200(a)和202(a)的栅极和源极引线结构连接，且半导体管芯206与200(b)和202(b)的栅极和源极引线结构连接。该栅极和源极引线指分别在引线框结构的两个面上的G和S处示出。
在图5(b)中，制模材料208覆盖引线框结构与半导体管芯204和206的各个部分。如根据工艺流程A，引线框结构200(a)和202(a)的各个部分被暴露，半导体管芯204和206的各个部分也一样。图5(c)示出用与工艺流程A中描述的相同方式在半导体封装上印刷和固化的导电材料层210。图5(d)示出在导电材料210层上的电镀层212。图5(e)示出封装剂214在电镀层212上的半导体管芯。图5(f)示出贯穿图5(a)到图5(e)中示出的工艺步骤的半导体管芯封装的所有层的横截面。在图5(f)中，暴露的漏极连接由在半导体管芯封装底部的附图标记216指示。
在此采用的术语和表达是用作描述而非限制的术语，且没有旨在使用除所示和所述的特征、或其各部分的等价物之外的术语和表达，应该认可各种修改在要求权利的本发明的范围内是可能的。此外，本发明任一实施方式的任何一个或多个特征可在不背离本发明的范围的情况下与本发明任何其它实施方式的任何一个或多个特征进行组合。
以上注释的所有专利申请、专利、以及公开是为了所有目的通过引用被完整纳入于此。没有一项被认为属于现有技术。

Claims (15)

1.一种用于形成半导体管芯封装的方法，包括：
获得包括至少一个具有引线表面的引线结构的引线框结构；
使具有第一表面和第二表面的半导体管芯与所述引线框结构附连，其中所述半导体管芯的第一表面与所述引线表面基本在同一平面上，且所述半导体管芯的第二表面与所述引线框结构耦连；以及
在所述引线表面和所述半导体管芯的第一表面上形成导电材料层以使至少一个引线结构与所述半导体管芯电耦连。
2.如权利要求1所述的方法，进一步包括在所述引线框结构和所述半导体管芯的至少一部分周围模制制模材料，其中在模制之后，所述引线表面和所述半导体管芯的第一表面通过所述制模材料暴露。
3.如权利要求1所述的方法，进一步包括在所述引线框结构上将非导电材料掩模置于至少一个引线结构与所述半导体管芯之间的间隙上。
4.如权利要求1所述的方法，进一步包括在所述导电层上形成焊膏层。
5.如权利要求1所述的方法，进一步包括使用电镀在所述导电材料层上形成第二导电层。
6.如权利要求1所述的方法，进一步包括使用电镀在所述导电材料层上形成第二导电层以及在所述第二导电层上形成防护材料层。
7.一种半导体管芯封装，包括：
包括至少一个具有引线表面的引线结构的引线框结构；
在所述引线框结构上的具有第一表面和第二表面的半导体管芯，其中所述半导体管芯的第一表面与所述引线表面基本在同一平面上，且所述半导体管芯的第二表面与所述引线框结构耦连；以及
在所述引线表面和所述半导体管芯的第一表面上、并使至少一个引线结构与所述半导体管芯的第一表面耦连的导电薄膜。
8.如权利要求7所述的半导体管芯，进一步包括覆盖所述引线框结构和半导体管芯的制模材料，其中所述半导体管芯包括垂直功率器件。
9.如权利要求7所述的半导体管芯封装，进一步包括覆盖引线框结构和半导体管芯的制模材料，其中所述半导体管芯封装的边缘通过所述制模材料暴露。
10.如权利要求7所述的半导体管芯封装，进一步包括在所述引线框结构上的覆盖至少一个引线结构与所述半导体管芯之间的间隙的非导电材料掩模。
11.如权利要求7所述的半导体管芯封装，进一步包括在引线框结构上的覆盖至少一个引线结构与所述半导体管芯之间的间隙的非导电材料层，其中所述非导电材料是焊料掩模。
12.如权利要求7所述的半导体管芯封装，其特征在于，所述半导体管芯的第一表面包括至少一个栅极区和至少一个源极区。
13.如权利要求7所述的半导体管芯封装，其特征在于，所述半导体管芯的第二表面包括至少一个漏极区。
14.如权利要求7所述的半导体管芯封装，其特征在于，所述半导体管芯包括至少一个栅极区和至少一个源极区，且所述栅极区与所述至少一个引线结构引线接合。
15.如权利要求7所述的半导体管芯封装，其特征在于，所述半导体管芯包括功率MOSFET。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057852A1 (en) * 2007-08-27 2009-03-05 Madrid Ruben P Thermally enhanced thin semiconductor package
DE102006015447B4 (de) * 2006-03-31 2012-08-16 Infineon Technologies Ag Leistungshalbleiterbauelement mit einem Leistungshalbleiterchip und Verfahren zur Herstellung desselben
US8106501B2 (en) * 2008-12-12 2012-01-31 Fairchild Semiconductor Corporation Semiconductor die package including low stress configuration
KR101391925B1 (ko) * 2007-02-28 2014-05-07 페어차일드코리아반도체 주식회사 반도체 패키지 및 이를 제조하기 위한 반도체 패키지 금형
KR101489325B1 (ko) 2007-03-12 2015-02-06 페어차일드코리아반도체 주식회사 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
US20090057855A1 (en) * 2007-08-30 2009-03-05 Maria Clemens Quinones Semiconductor die package including stand off structures
KR20090062612A (ko) * 2007-12-13 2009-06-17 페어차일드코리아반도체 주식회사 멀티 칩 패키지
US8106406B2 (en) 2008-01-09 2012-01-31 Fairchild Semiconductor Corporation Die package including substrate with molded device
KR101463074B1 (ko) * 2008-01-10 2014-11-21 페어차일드코리아반도체 주식회사 리드리스 패키지
US20090194856A1 (en) * 2008-02-06 2009-08-06 Gomez Jocel P Molded package assembly
KR101524545B1 (ko) * 2008-02-28 2015-06-01 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
US7812430B2 (en) * 2008-03-04 2010-10-12 Powertech Technology Inc. Leadframe and semiconductor package having downset baffle paddles
US7972906B2 (en) * 2008-03-07 2011-07-05 Fairchild Semiconductor Corporation Semiconductor die package including exposed connections
KR101519062B1 (ko) * 2008-03-31 2015-05-11 페어차일드코리아반도체 주식회사 반도체 소자 패키지
US8274164B2 (en) * 2008-11-06 2012-09-25 Microsemi Corporation Less expensive high power plastic surface mount package
US8193618B2 (en) * 2008-12-12 2012-06-05 Fairchild Semiconductor Corporation Semiconductor die package with clip interconnection
US8222718B2 (en) * 2009-02-05 2012-07-17 Fairchild Semiconductor Corporation Semiconductor die package and method for making the same

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3044872B2 (ja) * 1991-09-25 2000-05-22 ソニー株式会社 半導体装置
DE69529677T2 (de) * 1994-07-14 2004-03-25 Surgx Corp., Fremont Schutzstrukturen gegen veränderliche spannung und verfahren zur herstellung
SE9403575L (sv) * 1994-10-19 1996-04-20 Ericsson Telefon Ab L M Benram för kapslad optokomponent
US20040062759A1 (en) * 1995-07-12 2004-04-01 Cygnus, Inc. Hydrogel formulations for use in electroosmotic extraction and detection of glucose
US6072228A (en) * 1996-10-25 2000-06-06 Micron Technology, Inc. Multi-part lead frame with dissimilar materials and method of manufacturing
JP3003624B2 (ja) * 1997-05-27 2000-01-31 ソニー株式会社 半導体装置
CN1134839C (zh) * 1997-12-26 2004-01-14 三星航空产业株式会社 引线框架及涂敷引线框架的方法
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6040626A (en) * 1998-09-25 2000-03-21 International Rectifier Corp. Semiconductor package
KR100335481B1 (ko) * 1999-09-13 2002-05-04 김덕중 멀티 칩 패키지 구조의 전력소자
JP2001166162A (ja) * 1999-12-09 2001-06-22 Hitachi Cable Ltd アレイ導波路型グレーティング
US6720642B1 (en) * 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6525405B1 (en) * 2000-03-30 2003-02-25 Alphatec Holding Company Limited Leadless semiconductor product packaging apparatus having a window lid and method for packaging
US6989588B2 (en) * 2000-04-13 2006-01-24 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6691257B1 (en) * 2000-04-13 2004-02-10 Stratus Technologies Bermuda Ltd. Fault-tolerant maintenance bus protocol and method for using the same
TW451392B (en) * 2000-05-18 2001-08-21 Siliconix Taiwan Ltd Leadframe connecting method of power transistor
EP1158483A3 (en) 2000-05-24 2003-02-05 Eastman Kodak Company Solid-state display with reference pixel
JP3664045B2 (ja) * 2000-06-01 2005-06-22 セイコーエプソン株式会社 半導体装置の製造方法
KR100403608B1 (ko) * 2000-11-10 2003-11-01 페어차일드코리아반도체 주식회사 스택구조의 인텔리젠트 파워 모듈 패키지 및 그 제조방법
US6672806B2 (en) * 2000-11-22 2004-01-06 Forasol International Sa Device for drilling and anchoring and process for placing grout anchors
KR100374629B1 (ko) * 2000-12-19 2003-03-04 페어차일드코리아반도체 주식회사 얇고 작은 크기의 전력용 반도체 패키지
US6617702B2 (en) * 2001-01-25 2003-09-09 Ibm Corporation Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
CA2441924C (en) * 2001-03-20 2013-07-02 Shell Canada Limited Detecting a boundary in a formation
US6891257B2 (en) 2001-03-30 2005-05-10 Fairchild Semiconductor Corporation Packaging system for die-up connection of a die-down oriented integrated circuit
US6645791B2 (en) * 2001-04-23 2003-11-11 Fairchild Semiconductor Semiconductor die package including carrier with mask
US6893901B2 (en) * 2001-05-14 2005-05-17 Fairchild Semiconductor Corporation Carrier with metal bumps for semiconductor die packages
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US6633030B2 (en) 2001-08-31 2003-10-14 Fiarchild Semiconductor Surface mountable optocoupler package
US6853076B2 (en) * 2001-09-21 2005-02-08 Intel Corporation Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
US6774465B2 (en) * 2001-10-05 2004-08-10 Fairchild Korea Semiconductor, Ltd. Semiconductor power package module
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
JP3704304B2 (ja) * 2001-10-26 2005-10-12 新光電気工業株式会社 リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法
US6674157B2 (en) * 2001-11-02 2004-01-06 Fairchild Semiconductor Corporation Semiconductor package comprising vertical power transistor
JP2003197663A (ja) * 2001-12-28 2003-07-11 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6867489B1 (en) * 2002-01-22 2005-03-15 Fairchild Semiconductor Corporation Semiconductor die package processable at the wafer level
US6830959B2 (en) * 2002-01-22 2004-12-14 Fairchild Semiconductor Corporation Semiconductor die package with semiconductor die having side electrical connection
DE10392377T5 (de) * 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
US20040018667A1 (en) * 2002-07-26 2004-01-29 Haren Joshi Method and apparatus for producing a silicon wafer chip package
US7061077B2 (en) * 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US6943434B2 (en) * 2002-10-03 2005-09-13 Fairchild Semiconductor Corporation Method for maintaining solder thickness in flipchip attach packaging processes
US6825556B2 (en) * 2002-10-15 2004-11-30 Lsi Logic Corporation Integrated circuit package design with non-orthogonal die cut out
US20040191955A1 (en) * 2002-11-15 2004-09-30 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US20050012225A1 (en) 2002-11-15 2005-01-20 Choi Seung-Yong Wafer-level chip scale package and method for fabricating and using the same
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US6806580B2 (en) * 2002-12-26 2004-10-19 Fairchild Semiconductor Corporation Multichip module including substrate with an array of interconnect structures
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
JP3759131B2 (ja) 2003-07-31 2006-03-22 Ｎｅｃエレクトロニクス株式会社 リードレスパッケージ型半導体装置とその製造方法
US7315077B2 (en) * 2003-11-13 2008-01-01 Fairchild Korea Semiconductor, Ltd. Molded leadless package having a partially exposed lead frame pad
US7414843B2 (en) * 2004-03-10 2008-08-19 Intel Corporation Method and apparatus for a layered thermal management arrangement
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
US20050275089A1 (en) * 2004-06-09 2005-12-15 Joshi Rajeev D Package and method for packaging an integrated circuit die
US7501702B2 (en) * 2004-06-24 2009-03-10 Fairchild Semiconductor Corporation Integrated transistor module and method of fabricating same
JP4011076B2 (ja) * 2004-06-28 2007-11-21 株式会社東芝 半導体装置及びその製造方法

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TWI405274B (zh) 2013-08-11
US20070155058A1 (en) 2007-07-05
DE112006003633T5 (de) 2008-11-13
CN101416311B (zh) 2012-03-21
KR101378792B1 (ko) 2014-03-27
US7371616B2 (en) 2008-05-13
WO2007081546A2 (en) 2007-07-19
TW200733277A (en) 2007-09-01
KR20080092935A (ko) 2008-10-16

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