JP2013197276A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2013197276A JP2013197276A JP2012062149A JP2012062149A JP2013197276A JP 2013197276 A JP2013197276 A JP 2013197276A JP 2012062149 A JP2012062149 A JP 2012062149A JP 2012062149 A JP2012062149 A JP 2012062149A JP 2013197276 A JP2013197276 A JP 2013197276A
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Abstract
【解決手段】第1リードの先端部LE1c、第2リードの先端部LE2c、および第3リードの先端部LE3cを、スパンキング金型SDM1を用いて成形する際、第1リードの先端部LE1c、第2リードの先端部LE2c、および第3リードの先端部LE3cを、下金型SD1の押圧面に設けられた突起部の上面と上金型SU1の押圧面に設けられた溝部の底面とで押圧し、第2リードの曲げ部および第3リードの曲げ部を、下金型SD1の平坦な押圧面と上金型SU1の平坦な押圧面とで押圧する。
【選択図】図24
Description
例えば3端子の半導体装置PT0は、図38に示すように、半導体チップ(図示は省略)を封止する樹脂封止体(封止体)RSの下面(底面、下端)から3本のリード(外部端子)、すなわち第1リードLE1、第2リードLE2、および第3リードLE3が突き出した構造を有する。
≪半導体装置≫
本実施の形態1による複数のリードを備える半導体装置の構造を図1〜図3を用いて説明する。ここでは、複数のリードを備える半導体装置として、3端子の半導体装置を例示する。図1(a)および(b)はそれぞれ3端子の半導体装置の正面図および背面図、図2は3端子の半導体装置の側面図、図3は3端子の半導体装置の底面図である。
次に、本実施の形態1による3端子の半導体装置PT1の製造方法を図4〜図26を用いて工程順に説明する。ここで説明する3端子の半導体装置PT1を構成する半導体チップとして、パワートランジスタが形成された半導体チップを例示する。さらに、そのパワートランジスタとして、パワーMOSFETを例示する。
半導体ウエハの回路形成面(表面)に複数のパワーMOSFETを形成する。複数のパワーMOSFETは前工程または拡散工程と呼ばれる製造工程において、所定の製造プロセスに従って半導体ウエハにチップ単位で形成される。続いて、半導体ウエハに形成された各半導体チップの良・不良を判定した後、半導体ウエハをダイシングして、各半導体チップに個片化する。
図5に示すように、第1面、およびこの第1面とは反対側の第2面を有し、金属製の枠組みであるリードフレーム(配線部材)LFを準備する。リードフレームLFは、例えば銅(Cu)合金などの導電性部材から成る。リードフレームLFは、図5に示す第2方向に、半導体製品1つ分に該当する単位フレームが複数配置された構成となっている。各単位フレームは、チップ搭載部SCB、ならびに第2方向と直交する第1方向に延びて、互いに離間して配置された第1リードLE1、第2リードLE2、および第3リードLE3を有している。第1リードLE1、第2リードLE2、および第3リードLE3の断面形状は四角形であり、例えば断面における正面(第1面)側および背面(第2面)側の一辺の長さ(前述のリード幅LEW)は0.5mm、この辺と直交する側面側の他辺の長さ(前述のリード厚さLET)は0.4mmである。
図6(a)および(b)に示すように、リードフレームLFにめっき処理を施す。これにより、リードフレームLFの第1面に、例えば銀(Ag)からなるめっき膜AGを形成する。
図7(a)および(b)に示すように、コレットCOによって半導体チップSCを搬送し、第1リードLE1の第1面と半導体チップSCの裏面とを対向させて、各単位フレームのチップ搭載部SCBの第1面上に半導体チップSCを搭載する。チップ搭載部SCBの第1面と半導体チップSCの裏面とを、例えば金−錫(Au−Sn)共晶接合など接合する。これにより、半導体チップSCに形成されたパワーMOSFETのドレインと第1リードLE1とが裏面電極を介して電気的に接続する。なお、ここでは、チップ搭載部SCBの第1面と半導体チップSCの裏面との接続を、金−錫(Au−Sn)共晶接合で行う方法について説明したが、これに限定されるものではない。チップ搭載部SCBの第1面と半導体チップSCの裏面との接続は、その他の導電性接着材(半田または銀(Ag)ペースト)で行ってもよい。
図8(a)および(b)に示すように、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング(ボールボンディング)法により、半導体チップSCの表面に形成され、パワーMOSFETのゲートと電気的に接続するボンディングパッド(図示は省略)と、本体部となる部分の第2リードLE2の第1面とを導電性部材、例えばワイヤWGを介して電気的に接続する。これにより、パワーMOSFETのゲートと第2リードLE2とがボンディングパッドおよびワイヤWGを介して電気的に接続される。
図9(a)および(b)に示すように、半導体チップSCが配置されたリードフレームLFを金型成型機にセットし、温度を上げて液状化した封止樹脂を金型成型機に圧送して流し込み、本体部となる部分を封止樹脂で封入して、1個の樹脂封止体RSを形成する。続いて、例えば175℃の温度で5時間の熱処理(ポストキュアベーク)を施す。これにより、半導体チップSCの一部(上面および側面)、ワイヤWG,WS、チップ搭載部SCB、ならびに本体部となる部分の第1リードLE1、第2リードLE2、および第3リードLE3などが樹脂封止体RSによって封止される。樹脂封止体RSは、低応力化を図ることを目的として、例えばフェノール系硬化剤、シリコーンゴム、および多数のフィラー(例えばシリカ)などが添加されたエポキシ系の熱硬化性絶縁樹脂からなる。
図10に示すように、複数の単位フレームの第1方向の一方の端部と他方の端部との間に形成され、第1リードLE1、第2リードLE2、および第3リードLE3を連結保持しているタイバーTBを、切断装置を用いて切断する。
図11に示すように、複数の単位フレームの第1方向の一方の端部を連結保持している保持部LFHを、切断装置を用いて切断し、個々の半導体装置(半導体製品)PT1に切り分ける。この際、例えば切断装置に備わるダイ上に置かれたリードフレームLFに、切断装置に備わる切断パンチが打ち下ろされて、リードフレームLFの本体から各半導体装置PT1が切り離される。
図12に示すように、樹脂封止体RSから突き出している第1リードLE1、第2リードLE2、および第3リードLE3にめっき処理を施す。これにより、樹脂封止体RSから突出した第1リードLE1、第2リードLE2、および第3リードLE3のそれぞれの表面(正面、背面、側面、および底面)に、例えば厚さ10μm以下の錫(Sn)系合金または錫−鉛(Sn−Pb)系合金からなるめっき膜(図示は省略)を形成する。錫(Sn)系合金の場合、錫−銀(Sn−Ag)系合金、錫−銅(Sn−Cu)系合金、または錫−ビスマス(Sn−Bi)系合金などがある。また、純錫(Sn)の場合もある。
図13に示すように、レーザまたはインクなどを用いて樹脂封止体RSの背面に品名などを印字する。
図14に示すように、成形金型を用いて、樹脂封止体RSから突き出している第2リードLE2および第3リードLE3を所定の形状に加工する。
リード曲げ工程後の第2リードLE2の先端部LE2cおよび第3リードLE3の先端部LE3cでは、曲げた部分(曲げ部LE2b,LE3b)に生じた加工歪により、第2リードLE2の先端部LE2cおよび第3リードLE3の先端部LE3cが変形する(不揃いを起こす)場合がある。
次に、製品規格に沿って選別し、さらに最終外観検査を経て製品(半導体装置PT1)が完成する。
次に、キャリアテープに予め形成されている窪みに製品(半導体装置PT1)を収納する。その後、例えばキャリアテープをリールに巻き取り、防湿された袋にリールを収納し、出荷する。
前述した実施の形態1と相違する点は、半導体装置の一製造過程であるリード先端整列工程において使用するスパンキング金型の下金型(または上金型)に形成された突起部および上金型(または下金型)に形成された溝部の形状である。すなわち、前述した実施の形態1では、突起部の幅および溝部の幅はいずれも一定とした。以降に説明する本実施の形態2では、突起部の幅および溝部の幅はいずれも一定ではなく、突起部および溝部の断面形状はテーパ形状となっている。
<リード先端整列(スパンキング)工程>
本実施の形態2による3端子の半導体装置の製造方法を図27〜図31を用いて説明する。図27はリード先端整列工程におけるスパンキング金型の下金型および半導体装置を示す要部平面図、図28はリード先端整列工程におけるスパンキング金型の上金型および半導体装置を、上金型を透かして示す要部平面図、図29はリード先端整列工程におけるスパンキング金型に押圧された各リードの先端部を示す要部断面図、図30はリード先端整列工程におけるスパンキング金型に押圧された各リードの曲げ部を示す要部断面図である。図31はリード先端整列工程におけるスパンキング金型に押圧された各リードの曲げ部の他の例を示す要部断面図である。
前述した実施の形態2では、複数のリードを備える半導体装置として、3端子の半導体装置を例示し、3端子の半導体装置に備わる3本のリードの先端部を成形するリード先端整列工程について説明した。ここでは、変形例として、5端子の半導体装置に備わる5本のリードの先端部を成形するリード先端整列工程について説明する。
B 底面(第4面)
CO コレット
F 正面(第1面)
FD1 第1曲げダイ
FD2 第2曲げダイ
FSD 下金型固定部(第2固定部)
FSU 上金型固定部(第1固定部)
FP1 第1曲げパンチ
FP2 第2曲げパンチ
GSD 下金型ガイド部(第2ガイド部)
GSU 上金型ガイド部(第1ガイド部)
L1 リード長さ
L2 封止体長さ
LE1 第1リード
LE2 第2リード
LE3 第3リード
LE4 第4リード
LE5 第5リード
LE1a,LE2a,LE3a,LE4a,LE5a 根元部(第1部分)
LE2b,LE3b,LE4b,LE5b 曲げ部(第2部分)
LE1c,LE2c,LE3c,LE4c,LE5c 先端部(第3部分)
LEW リード幅
LET リード厚さ(奥行き)
LF リードフレーム(配線部材)
LFH 保持部
P1,P2 ピッチ
PT0,PT1,PT2 半導体装置
R 背面(第2面)
RS 樹脂封止体(封止体)
S 側面(第3面)
SC 半導体チップ
SCB チップ搭載部
SD0,SD1,SD2,SD3 下金型(第2金型)
SD1a,SD2a,SD3a 下金型(第2金型)
SDM0,SDM1,SDM2,SDM3 スパンキング金型
SDM1a,SDM2a,SDM3a スパンキング金型
SU0,SU1,SU2,SU3, 上金型(第1金型)
SU1a,SU2a,SU3a 上金型(第1金型)
TB タイバー
W1 突起部の幅
W2 溝部の幅
W4,W6 突起部の上面の幅
W5,W7 溝部の底面の幅
WG,WS ワイヤ(導電性部材)
θ1,θ2,θ3,θ4 角度
Claims (12)
- 以下の工程を含む半導体装置の製造方法:
(a)表面、および前記表面と反対側の裏面を有する半導体チップを準備する工程;
(b)第1面、および前記第1面と反対側の第2面を有し、さらに、チップ搭載部、第1リード、および前記第1リードと離間して配置された第2リードを有し、前記第1リードの一端および前記第2リードの一端が保持部により連結保持され、前記第1リードの他端が前記チップ搭載部と連結したリードフレームを準備する工程;
(c)前記チップ搭載部の前記第1面と前記半導体チップの前記裏面とを対向させて、前記チップ搭載部の前記第1面上に、前記半導体チップを搭載する工程;
(d)前記半導体チップの前記表面に形成された表面電極と前記第2リードの前記第1面とを電気的に接続する工程;
(e)前記半導体チップ、前記チップ搭載部、前記第1リードの一部、および前記第2リードの一部を樹脂で封止することにより、樹脂封止体を形成する工程;
(f)前記保持部から、前記第1リードおよび前記第2リードを分離する工程;
(g)前記樹脂封止体から突き出た前記第2リードの一部を前記第1リードから離れる方向に成形する工程;
(h)前記樹脂封止体から突き出た前記第1リードの先端部および前記樹脂封止体から突き出た前記第2リードの先端部を揃える工程、
さらに、前記(g)工程では、
前記第2リードが第1部分、一端が前記第1部分と連結し、他端が前記第1部分よりも前記第1リードから離れて位置する第2部分、および前記第2部分の他端と連結する第3部分を有するように、前記第2リードは成形され、
さらに、前記(h)工程では、
前記第2リードの前記第2部分の前記第1面、および前記第2部分の前記第2面を金型で押圧する。 - 請求項1記載の半導体装置の製造方法において、
前記金型は、前記第2リードの前記第1面を押圧する第1金型と、前記第2リードの前記第2面を押圧する第2金型とを有し、
前記第1金型には、前記第2リードの前記第2部分を押圧する第1固定部と、前記第2リードの前記第3部分を押圧する第1ガイド部とを有し、
前記第2金型には、前記第2リードの前記第2部分を押圧する第2固定部と、前記第2リードの前記第3部分を押圧する第2ガイド部とを有し、
前記第2金型の前記第2ガイド部の押圧面には、第1方向に延びる突起部が設けられ、
前記第1金型の前記第1ガイド部の押圧面には、前記突起部に対応して、前記第1方向に延びる溝部が設けられており、
さらに、前記(h)工程では、
前記第1金型に設けられた前記溝部の底面で、前記第2リードの前記第3部分の前記第1面を押圧し、
前記第2金型に設けられた前記突起部の上面で、前記第2リードの前記第3部分の前記第2面を押圧する。 - 請求項2記載の半導体装置の製造方法において、
前記第1金型の前記第1固定部の押圧面は平坦であり、前記第2金型の前記第2固定部の押圧面は平坦である。 - 請求項2記載の半導体装置の製造方法において、
前記第2金型に設けられた前記突起部の上面の前記第1方向と直交する第2方向の幅は、前記第2リードのリード幅以上であり、(前記第2リードの前記リード幅+(前記第2リードの前記リード幅×0.1)×2)以下である。 - 請求項2記載の半導体装置の製造方法において、
前記第1方向と直交する第2方向に沿った断面では、前記第2金型に設けられた前記突起部の断面形状はテーパ形状であり、前記突起部の上面の前記第2方向の幅は、前記突起部の他の部分の前記第2方向の幅よりも小さい。 - 請求項2記載の半導体装置の製造方法において、
前記第1金型に設けられた前記溝部の底面の前記第1方向と直交する第2方向の幅は、前記第2リードのリード幅よりも大きい。 - 請求項2記載の半導体装置の製造方法において、
前記第1方向と直交する第2方向に沿った断面では、前記第1金型に設けられた前記溝部の断面形状はテーパ形状であり、前記溝部の底面の前記第2方向の幅は、前記溝部の他の部分の前記第2方向の幅よりも小さい。 - 請求項1記載の半導体装置の製造方法において、
前記第2リードの断面形状は四角形である。 - 請求項8記載の半導体装置の製造方法において、
前記第2リードのリード幅は前記第2リードのリード厚さよりも大きい。 - 請求項1記載の半導体装置の製造方法において、
前記第1リードの長さは、前記第1リードが延びる方向における前記樹脂封止体の長さの2倍以上である。 - 請求項1記載の半導体装置の製造方法において、
前記半導体チップには、ソース、ドレイン、およびゲートから構成されるパワーMOSFETが形成されており、
前記第1リードは、前記半導体チップの前記裏面に形成された裏面電極を介して、前記パワーMOSFETの前記ドレインと電気的に接続し、
前記第2リードは、前記半導体チップの前記表面に形成された前記表面電極および導電性部材を介して、前記パワーMOSFETの前記ソースまたは前記ゲートと電気的に接続されている。 - 請求項1記載の半導体装置の製造方法において、
前記(d)工程では、前記半導体チップの前記表面電極と前記第2リードの前記第1面とをワイヤにより電気的に接続する。
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JPS5987152U (ja) * | 1982-11-30 | 1984-06-13 | 三菱電機株式会社 | 半導体装置用フレ−ム |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2020092112A (ja) * | 2018-12-03 | 2020-06-11 | 株式会社デンソー | 電子回路および電子回路の接合方法 |
JP7103193B2 (ja) | 2018-12-03 | 2022-07-20 | 株式会社デンソー | 電子回路および電子回路の接合方法 |
US20230268312A1 (en) * | 2022-02-18 | 2023-08-24 | Bae Systems Information And Electronic Systems Integration Inc. | Soft touch eutectic solder pressure pad |
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JP5851897B2 (ja) | 2016-02-03 |
TWI559415B (zh) | 2016-11-21 |
US8975119B2 (en) | 2015-03-10 |
CN103325699A (zh) | 2013-09-25 |
US20130244381A1 (en) | 2013-09-19 |
TW201344816A (zh) | 2013-11-01 |
CN103325699B (zh) | 2017-04-19 |
KR20130106327A (ko) | 2013-09-27 |
KR102052459B1 (ko) | 2019-12-05 |
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