CN106981471B - 引线框组合件 - Google Patents

引线框组合件 Download PDF

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CN106981471B
CN106981471B CN201610952595.XA CN201610952595A CN106981471B CN 106981471 B CN106981471 B CN 106981471B CN 201610952595 A CN201610952595 A CN 201610952595A CN 106981471 B CN106981471 B CN 106981471B
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leads
bond wire
package
bond
attached
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CN106981471A (zh
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涩谷诚
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本发明涉及一种引线框组合件。引线框组合件(101)包含具有裸片附接垫(102)及第一多个引线(107A、107B、107C)等等的引线框(100)。具有第一端(124)及第二端(128)的第一大体上正弦波形线(120)使其所述第一端(124)附接到所述第一多个引线中的第一者(107A)并使其所述第二端(128)附接到所述第一多个引线中的第二者(107C)。一种制造引线框组合件(101)的方法包含：通过将第一线(120)弯曲成大体上正弦波形配置而在引线框(100)上形成电感器；及将所述第一线(120)附接到所述引线框(100)的第一组引线(107A、107B、107C)。

Description

引线框组合件
技术领域
本发明涉及集成电路的技术领域，且更特定来说，涉及一种引线框组合件、集成电路封装、及制造引线框组合件的方法。
背景技术
集成电路裸片包含有源电路元件，例如晶体管。有源电路元件有时必须连接到例如电感器、电容器及电阻器的无源电路元件以便执行所期望的操作。电感器及其它无源电路元件通常被提供作为连接到集成电路裸片而非经形成作为裸片本身的部件的单独的离散元件。
发明内容
一种引线框组合件包含具有裸片附接垫(DAP)及第一多个引线的引线框。具有第一端及第二端的第一大体上正弦波形线使其所述第一端附接到所述第一多个引线中的第一者并使其所述第二端附接到所述第一多个引线的第二者以在所述引线框上形成电感器。
一种集成电路封装包含具有裸片附接垫(DAP)及第一及第二多个引线的引线框。第一及第二大体上正弦波形线分别附接到所述第一及第二多个引线，所述第一线与所述第二线成对置间隔开的关系而定位。至少一个裸片安装于所述DAP上且电连接到所述第一及第二引线。
一种制造引线框组合件的方法包含：通过将第一线弯曲成大体上正弦波形配置而在引线框上形成电感器；及将所述第一线附接到所述引线框的第一组引线。
附图说明
图1是现有技术双引线框组合件的等距视图。
图2是图1的组合件的第一引线框的示意性俯视图。
图2A是图2中所展示的第一引线框的示意性侧视图。
图3是图1的引线框组合件的第二引线框的示意性俯视图。
图3A是图3中所展示的第二引线框的示意性侧视图。
图4是引线框组合件的示意性俯视图，所述引线框组合件具有图2及2A中所说明的与图3及3A中所说明的第二引线框成叠加关系而定位的第一引线框。
图4A是在图4中所展示的引线框组合件的示意性侧视图。
图5是在图4及4A中所展示的引线框组合件在模制之后及在引线切割期间的示意性横截面侧视图。
图6是图5的引线框组合件在引线形成已产生集成电路封装之后的示意性横截面侧视图。
图7是实例引线框实施例的等距视图。
图8是具有附接到其引线的正弦波形线的图7的实例引线框实施例的等距视图。
图8A是图8中所展示的正弦波形线中的一者的实例实施例。
图8B是具有成叠加关系而定位的两个正弦波形线的图8的实例引线框实施例的等距视图。
图9是实例引线框实施例的示意性俯视图，其展示集成电路(“IC”)封装的产生的第一阶段。
图9A是图9的引线框实施例的示意性侧视图。
图10是图9及9A的引线框实施例的示意性俯视图，其说明IC封装的产生的线附接阶段。
图10A是图10的引线框实施例的示意性侧视图。
图11是图10的引线框实施例的示意性俯视图，其说明在IC封装的产生中附接线的弯曲。
图11A是图11的引线框实施例的示意性侧视图。
图12是其中引线框已被模制并切割的另一产生阶段中的图11的引线框实施例的横截面侧视图。
图13是图12的模制引线框实施例在引线形成将产生集成电路封装之后的横截面侧视图。
图14是说明制造引线框组合件的方法的流程图。
具体实施方式
图1是现有技术双引线框组合件10的等距视图。组合件10具有包含裸片附接垫(DAP)14的第一引线框12。多个引线16定位于裸片附接垫14的每一横向侧上。第一引线框12具有与裸片附接垫14纵向间隔开的第二多个引线18A、18B、18C。大体上M形引线延长部分20整体由引线18A及18C形成。
此进一步参考图1，包含引线34A、34B、34C的第二引线框32具有整体附接到引线34A及34C的第二M形引线延长部分36。此第二引线框32叠加第一引线框12，从而与其一起形成电感器组合件。在图1中，单个裸片38以常规方式安装于裸片附接垫14上。
图2到6说明构建图1的双引线框组合件10的方法。
图2是图1的双引线框组合件10的第二引线框32在其与第一引线框12组装之前的示意性俯视图。图2A是此第二引线框12的示意性侧视图。
图3是图1的双引线框组合件10的第一引线框12在其与第二引线框32组装之前的俯视图，且图3A是其侧视图。
图4是引线框组合件的示意性俯视图，且图4A是引线框组合件的侧视图，其中图2及2A中所说明的第二引线框32与图3及3A中所说明的第一引线框12成叠加关系而定位。裸片38已被安装于裸片附接垫14上。
图5是图4及4A中所展示的引线框组合件在其模制之后及在引线切割期间的示意性侧视图。如图5中所说明，在切割之前，组合件已被模制且因此模制化合物层40覆盖裸片附接垫14及裸片38及引线16、16A等等与34A等等的部分。这些引线部分从模制化合物40向外突出，且随后如使用切割锯或冲压机42被切割，以在上部及下部引线框片材(未展示)中分离引线框12、32与邻近的经整体连接的引线框(未展示)。
如图6中所说明，在引线切割之后，引线16等等形成为对应于图1中所说明的引线16的形状的最终形状。因此，形成包含由两个分离的引线框12、32的重叠部分提供的电感器组合件的集成电路封装60。
图7是包括单个引线框100的实例引线框实施例的等距视图。引线框100包含裸片附接垫102、邻近于裸片附接垫102的多个引线104及与裸片附接垫102纵向间隔开的多个引线106A、106B、106C、及107A、107B、107C。裸片110安装于裸片附接垫102上。在一个实施例中，裸片110具有在其底部上的如通过焊料或导电粘合剂电连接到裸片附接垫102的电接触表面。(在另一实施例中，裸片110可通过线接合连接到裸片附接垫及/或各种引线)。图7中所说明的裸片附接垫102是分割垫，在一些实施例中，其可具有安装于其每一半上的一或多个裸片。
图8是图7的实例引线框实施例100的等距视图，但引线框实施例100具有附接到其的两个正弦波形线120、140且现引用作为引线框组合件101。图8A是可相同于另一线140的正弦波形线120中的一者的实例实施例的侧视图。在此实例实施例中，线120是大体上M形且包括：具有第一足部124的第一腿部122；具有第二足部128的第二腿部126；及整体连接到两个腿部122、126的上端的大体上V形中间部分130。在一个实例实施例中，两个足部124、128之间的距离“a”可为大约750μm；每一足部124、128与V形部分130的底端之间的距离“b”可为大约250μm；V形部分的两个上端之间的距离“c”可为大约250μm；且从V形部分130的底部到V形部分的顶部的高度“d”可为大约3mm。
如由图8进一步说明，第一线120可使其第一足部124附接到引线107C并使其第二足部128附接到引线107A。类似地，第二线140使其第一足部146附接到引线106C并使其第二足部144附接到引线106A。最初，两个线120、140都以垂直定向附接到引线框。
如由图8B说明，线120、140随后经弯曲，使得其大体上平行于裸片附接垫102放置，且第一线120与第二线140成非接触叠加关系而定位。如此定位的线形成可如通过线接合线附接到裸片110的电感器。
图9到13说明可产生具有电感器的集成电路封装的操作序列。图9是图7中所说明的单个引线框在引线成型之前的示意性俯视图。如先前所论述，引线框100包含裸片附接垫102、邻近于裸片附接垫102的多个引线104及与裸片附接垫102纵向间隔开的多个引线106A、106B、106C、及107A、107B、107C。
大体上对应于图8的图10及10A说明将两个大体上M形线120、142添加到图9的引线框100，其中线120、140与裸片附接垫102成垂直关系而定位。图10还说明裸片110到裸片附接垫102的附接。为清晰地说明，在图10到13中未展示将裸片110连接到引线的接合线。在一个方法实施例中，此类线接合发生于图11中所展示的组装状态与图12中所展示的组装状态之间。
大体上对应于图8B的图11及11A说明在将M形线120、140弯曲成叠加关系之后的图10的组合件。线120、140现彼此成大体上平行关系而定位，且可平行于裸片附接垫102或相对于裸片附接垫102稍微歪斜。
如由图12说明，接着，引线框100、线120、140及裸片110由模制化合物150覆盖，且如通过使用切割锯或冲压机155以常规方式从相关联的引线框条带(未展示)的邻近引线框割断引线104等等的经暴露部分。
接着，如由图13说明，引线104等等的经暴露端以常规方式形成为用于附接集成电路封装160的适当配置，因此，形成为其它电子组件(未展示)，如同印刷电路板(未展示)。
集成电路封装160因此包含由线120及140形成的电感器组合件，线120及140附接到如与图6的集成电路封装60对置的单个引线框的引线，在图6中，两个单独的引线框用于形成电感器组合件。通过从电感器组合件消除一个引线框，产生集成电路封装160的成本大幅减小以优于产生图6的现有技术封装60的成本。
图14是说明制造引线框组合件的方法的流程图。所述方法包含：如框201处所展示，通过将第一线弯曲成大体上正弦波形配置而在引线框上形成电感器；及将所述第一线附接到引线框的第一组引线。
本文中详细描述引线框组合件的实施例及制造引线框组合件的方法。在阅读本发明之后，所属领域的技术人员将明白此类引线框组合件及产生方法的替代性实施例。希望概括地解释所附权利要求书的语言以涵盖除如由现有技术限制外的此类替代性实施例。

Claims (34)

1.一种集成电路IC封装，其包括：
引线框，其包括裸片附接垫、第一多个引线以及第二多个引线；
第一接合线，其附接到所述第一多个引线中的两个引线；及
第二接合线，其附接到所述第二多个引线中的两个引线，其中所述第一接合线的平面与所述第二接合线的平面平行，所述第一接合线和所述第二接合线彼此部分重叠，且所述第一接合线不与所述第二接合线接触。
2.根据权利要求1所述的IC封装，其进一步包括IC裸片，所述IC裸片附接到所述裸片附接垫且电连接到所述第一多个引线中的至少一者和所述第二多个引线中的至少一者。
3.根据权利要求1所述的IC封装，其中所述第一接合线及所述第二接合线大体上是正弦波形。
4.根据权利要求1所述的IC封装，其中所述第一接合线及所述第二接合线大体上是M形。
5.根据权利要求1所述的IC封装，其中所述第一接合线包括附接到所述第一多个引线中的所述两个引线的两个足部，且所述第二接合线包括附接到所述第二多个引线中的所述两个引线的两个足部。
6.根据权利要求5所述的IC封装，其中所述第一接合线和所述第二接合线中的每一者的所述两个足部分别楔焊接合到所述第一多个引线中的所述两个引线和所述第二多个引线中的所述两个引线。
7.根据权利要求1所述的IC封装，其中所述第一接合线和所述第二接合线中的每一者包括铜。
8.根据权利要求1所述的IC封装，其中所述第二多个引线横向定位成与所述第一多个引线相对。
9.根据权利要求1所述的IC封装，其中所述第一接合线被线接合到所述第一多个引线中的所述两个引线且所述第二接合线被线接合到所述第二多个引线中的所述两个引线。
10.一种集成电路IC封装，其包括：
引线框，其包括第一多个引线和第二多个引线，及裸片附接垫；
第一接合线，其附接到所述第一多个引线中的两个引线；
第二接合线，其附接到所述第二多个引线中的两个引线，所述第一接合线和所述第二接合线彼此部分平行且重叠；
IC裸片，其附接到所述裸片附接垫且电连接到所述第一多个引线中的至少一者和所述第二多个引线中的至少一者；以及
模制化合物，其覆盖所述引线框、所述第一接合线、所述第二接合线和所述IC裸片的部分，
其中所述第一接合线不与所述第二接合线接触。
11.根据权利要求10所述的IC封装，其中所述第一接合线及所述第二接合线一起形成电感器。
12.根据权利要求10所述的IC封装，其中所述第一接合线包括附接到所述第一多个引线中的所述两个引线的两个足部，且所述第二接合线包括附接到所述第二多个引线中的所述两个引线的两个足部。
13.根据权利要求12所述的IC封装，其中所述第一接合线的所述两个足部或所述第二接合线的所述两个足部之间的距离是750微米。
14.根据权利要求10所述的IC封装，其中所述IC裸片电连接到所述第一接合线和所述第二接合线。
15.根据权利要求10所述的IC封装，其中所述第一接合线和所述第二接合线的平面与所述裸片附接垫的平面平行。
16.根据权利要求10所述的IC封装，其中所述第一多个引线和所述第二多个引线部分延伸穿过所述模制化合物。
17.根据权利要求10所述的IC封装，其中所述裸片附接垫是分割裸片附接垫。
18.一种集成电路IC封装，其包括：
第一多个引线和第二多个引线，第一裸片附接垫和第二裸片附接垫；
第一接合线，其附接到所述第一多个引线中的两个引线；及
第二接合线，其附接到所述第二多个引线中的两个引线，其中所述第一接合线的平面与所述第二接合线的平面平行，所述第一接合线和所述第二接合线彼此部分重叠，且所述第一接合线不与所述第二接合线接触。
19.根据权利要求18所述的IC封装，其进一步包括附接到所述第一裸片附接垫的第一IC裸片和附接到所述第二裸片附接垫的第二IC裸片，所述第一IC裸片和所述第二IC裸片中的每一者电连接到所述第一多个引线中的至少一者或所述第二多个引线中的至少一者。
20.根据权利要求18所述的IC封装，其中所述第一接合线及所述第二接合线大体上是正弦波形。
21.根据权利要求18所述的IC封装，其中所述第一接合线及所述第二接合线大体上是M形。
22.根据权利要求18所述的IC封装，其中所述第一接合线包括附接到所述第一多个引线中的所述两个引线的两个足部，且所述第二接合线包括附接到所述第二多个引线中的所述两个引线的两个足部。
23.根据权利要求22所述的IC封装，其中所述第一接合线和所述第二接合线中的每一者的所述两个足部分别楔焊接合到所述第一多个引线中的所述两个引线和所述第二多个引线中的所述两个引线。
24.根据权利要求18所述的IC封装，其中所述第一接合线和所述第二接合线中的每一者包括铜。
25.根据权利要求18所述的IC封装，其中所述第二多个引线横向定位成与所述第一多个引线相对。
26.根据权利要求18所述的IC封装，其中所述第一接合线被线接合到所述第一多个引线中的所述两个引线且所述第二接合线被线接合到所述第二多个引线中的所述两个引线。
27.一种集成电路IC封装，其包括：
引线框，其包括第一多个引线和第二多个引线、第一裸片附接垫和第二裸片附接垫；
第一接合线，其附接到所述第一多个引线中的两个引线；
第二接合线，其附接到所述第二多个引线中的两个引线，所述第一接合线和所述第二接合线彼此部分平行且重叠；
第一IC裸片，其附接到所述第一裸片附接垫且电连接到所述第一多个引线中的至少一者或所述第二多个引线中的至少一者；以及
模制化合物，其覆盖所述引线框、所述第一接合线、所述第二接合线和所述第一IC裸片的部分，
其中所述第一接合线不与所述第二接合线接触。
28.根据权利要求27所述的IC封装，其进一步包括第二IC裸片，所述第二IC裸片附接到所述第二裸片附接垫且电连接到所述第一多个引线中的至少一者或所述第二多个引线中的至少一者，且其中所述模制化合物覆盖所述第二IC裸片的部分。
29.根据权利要求27所述的IC封装，其中所述第一接合线及所述第二接合线一起形成电感器。
30.根据权利要求27所述的IC封装，其中所述第一接合线包括附接到所述第一多个引线中的所述两个引线的两个足部，且所述第二接合线包括附接到所述第二多个引线中的所述两个引线的两个足部。
31.根据权利要求30所述的IC封装，其中所述第一接合线的所述两个足部或所述第二接合线的所述两个足部之间的距离是750微米。
32.根据权利要求28所述的IC封装，其中所述第一IC裸片或所述第二IC裸片电连接到所述第一接合线和所述第二接合线。
33.根据权利要求27所述的IC封装，其中所述第一接合线和所述第二接合线的平面与所述第一裸片附接垫的平面和所述第二裸片附接垫的平面平行。
34.根据权利要求27所述的IC封装，其中所述第一多个引线和所述第二多个引线部分延伸穿过所述模制化合物。
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