JP2013140982A5 - - Google Patents

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Publication number
JP2013140982A5
JP2013140982A5 JP2012287211A JP2012287211A JP2013140982A5 JP 2013140982 A5 JP2013140982 A5 JP 2013140982A5 JP 2012287211 A JP2012287211 A JP 2012287211A JP 2012287211 A JP2012287211 A JP 2012287211A JP 2013140982 A5 JP2013140982 A5 JP 2013140982A5
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JP
Japan
Prior art keywords
die
forming
bond pad
plating
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012287211A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013140982A (ja
JP6137832B2 (ja
Filing date
Publication date
Priority claimed from US13/343,318 external-priority patent/US8519513B2/en
Application filed filed Critical
Publication of JP2013140982A publication Critical patent/JP2013140982A/ja
Publication of JP2013140982A5 publication Critical patent/JP2013140982A5/ja
Application granted granted Critical
Publication of JP6137832B2 publication Critical patent/JP6137832B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2012287211A 2012-01-04 2012-12-28 半導体ウェハめっきブスおよびその形成方法 Expired - Fee Related JP6137832B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/343,318 US8519513B2 (en) 2012-01-04 2012-01-04 Semiconductor wafer plating bus
US13/343,318 2012-01-04

Publications (3)

Publication Number Publication Date
JP2013140982A JP2013140982A (ja) 2013-07-18
JP2013140982A5 true JP2013140982A5 (enExample) 2016-02-04
JP6137832B2 JP6137832B2 (ja) 2017-05-31

Family

ID=48694186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012287211A Expired - Fee Related JP6137832B2 (ja) 2012-01-04 2012-12-28 半導体ウェハめっきブスおよびその形成方法

Country Status (3)

Country Link
US (2) US8519513B2 (enExample)
JP (1) JP6137832B2 (enExample)
CN (1) CN103199021B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269622B2 (en) * 2013-05-09 2016-02-23 Deca Technologies Inc. Semiconductor device and method of land grid array packaging with bussing lines
TWI559413B (zh) 2014-07-25 2016-11-21 力智電子股份有限公司 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法
US10566268B1 (en) 2018-09-26 2020-02-18 Nxp Usa, Inc. Package to die connection system and method therefor
US12424450B2 (en) 2023-11-22 2025-09-23 Deca Technologies Usa, Inc. Embedded component interposer or substrate comprising displacement compensation traces (DCTs) and method of making the same

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3053675B2 (ja) * 1991-09-09 2000-06-19 ローム株式会社 半導体装置およびその製造方法
US5648661A (en) * 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5659189A (en) * 1995-06-07 1997-08-19 Lsi Logic Corporation Layout configuration for an integrated circuit gate array
US6136517A (en) * 1998-03-06 2000-10-24 Raytheon Company Method for photo composition of large area integrated circuits
JP2000012589A (ja) * 1998-06-18 2000-01-14 Toyota Motor Corp バンプ電極形成方法
US6479887B1 (en) * 1998-08-31 2002-11-12 Amkor Technology, Inc. Circuit pattern tape for wafer-scale production of chip size semiconductor packages
US6692629B1 (en) * 2000-09-07 2004-02-17 Siliconware Precision Industries Co., Ltd. Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer
TW484216B (en) * 2001-05-09 2002-04-21 Siliconware Precision Industries Co Ltd Singulation method of semiconductor package
US6566736B1 (en) * 2001-11-30 2003-05-20 Advanced Micro Devices, Inc. Die seal for semiconductor device moisture protection
JP3813562B2 (ja) * 2002-03-15 2006-08-23 富士通株式会社 半導体装置及びその製造方法
SG142115A1 (en) * 2002-06-14 2008-05-28 Micron Technology Inc Wafer level packaging
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
JP2004153015A (ja) * 2002-10-30 2004-05-27 Fujitsu Ltd 半導体装置及びその製造方法
US7435990B2 (en) * 2003-01-15 2008-10-14 International Business Machines Corporation Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer
US6744067B1 (en) * 2003-01-17 2004-06-01 Micron Technology, Inc. Wafer-level testing apparatus and method
US6995462B2 (en) * 2003-09-17 2006-02-07 Micron Technology, Inc. Image sensor packages
US7181837B2 (en) 2004-06-04 2007-02-27 Micron Technology, Inc. Plating buss and a method of use thereof
US8461675B2 (en) * 2005-12-13 2013-06-11 Sandisk Technologies Inc. Substrate panel with plating bar structured to allow minimum kerf width
JP4998270B2 (ja) * 2005-12-27 2012-08-15 富士通セミコンダクター株式会社 半導体装置とその製造方法
EP2052292B1 (en) * 2006-08-14 2014-02-26 Dow Corning Corporation Method of preparing a patterned film with a developing solvent
US7829998B2 (en) * 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US7898066B1 (en) * 2007-05-25 2011-03-01 Amkor Technology, Inc. Semiconductor device having EMI shielding and method therefor
US7679384B2 (en) * 2007-06-08 2010-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Parametric testline with increased test pattern areas
JP2010087354A (ja) * 2008-10-01 2010-04-15 Fujitsu Microelectronics Ltd 半導体ウエハ及び半導体装置
US20100301398A1 (en) * 2009-05-29 2010-12-02 Ion Torrent Systems Incorporated Methods and apparatus for measuring analytes
US8168529B2 (en) * 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8349666B1 (en) * 2011-07-22 2013-01-08 Freescale Semiconductor, Inc. Fused buss for plating features on a semiconductor die

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