CN103199021B - 半导体晶片镀总线以及形成方法 - Google Patents

半导体晶片镀总线以及形成方法 Download PDF

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Publication number
CN103199021B
CN103199021B CN201210583531.9A CN201210583531A CN103199021B CN 103199021 B CN103199021 B CN 103199021B CN 201210583531 A CN201210583531 A CN 201210583531A CN 103199021 B CN103199021 B CN 103199021B
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China
Prior art keywords
banding
layer
pad
trace
metal
Prior art date
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Active
Application number
CN201210583531.9A
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English (en)
Chinese (zh)
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CN103199021A (zh
Inventor
T·S·尤林
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN103199021A publication Critical patent/CN103199021A/zh
Application granted granted Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
CN201210583531.9A 2012-01-04 2012-12-28 半导体晶片镀总线以及形成方法 Active CN103199021B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/343,318 2012-01-04
US13/343,318 US8519513B2 (en) 2012-01-04 2012-01-04 Semiconductor wafer plating bus

Publications (2)

Publication Number Publication Date
CN103199021A CN103199021A (zh) 2013-07-10
CN103199021B true CN103199021B (zh) 2017-04-12

Family

ID=48694186

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210583531.9A Active CN103199021B (zh) 2012-01-04 2012-12-28 半导体晶片镀总线以及形成方法

Country Status (3)

Country Link
US (2) US8519513B2 (enExample)
JP (1) JP6137832B2 (enExample)
CN (1) CN103199021B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269622B2 (en) * 2013-05-09 2016-02-23 Deca Technologies Inc. Semiconductor device and method of land grid array packaging with bussing lines
TWI559413B (zh) 2014-07-25 2016-11-21 力智電子股份有限公司 可攜式裝置及其積體電路的封裝結構、封裝體與封裝方法
US10566268B1 (en) 2018-09-26 2020-02-18 Nxp Usa, Inc. Package to die connection system and method therefor
US12500197B2 (en) 2022-12-23 2025-12-16 Deca Technologies Usa, Inc. Encapsulant-defined land grid array (LGA) package and method for making the same
US12424450B2 (en) 2023-11-22 2025-09-23 Deca Technologies Usa, Inc. Embedded component interposer or substrate comprising displacement compensation traces (DCTs) and method of making the same
US12500198B2 (en) 2024-03-01 2025-12-16 Deca Technologies Usa, Inc. Quad flat no-lead (QFN) package with tie bars and direct contact interconnect build-up structure and method for making the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW484216B (en) * 2001-05-09 2002-04-21 Siliconware Precision Industries Co Ltd Singulation method of semiconductor package
US6566736B1 (en) * 2001-11-30 2003-05-20 Advanced Micro Devices, Inc. Die seal for semiconductor device moisture protection
US6692629B1 (en) * 2000-09-07 2004-02-17 Siliconware Precision Industries Co., Ltd. Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3053675B2 (ja) * 1991-09-09 2000-06-19 ローム株式会社 半導体装置およびその製造方法
US5648661A (en) * 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
US5659189A (en) * 1995-06-07 1997-08-19 Lsi Logic Corporation Layout configuration for an integrated circuit gate array
US6136517A (en) * 1998-03-06 2000-10-24 Raytheon Company Method for photo composition of large area integrated circuits
JP2000012589A (ja) * 1998-06-18 2000-01-14 Toyota Motor Corp バンプ電極形成方法
US6479887B1 (en) * 1998-08-31 2002-11-12 Amkor Technology, Inc. Circuit pattern tape for wafer-scale production of chip size semiconductor packages
JP3813562B2 (ja) * 2002-03-15 2006-08-23 富士通株式会社 半導体装置及びその製造方法
SG142115A1 (en) * 2002-06-14 2008-05-28 Micron Technology Inc Wafer level packaging
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
JP2004153015A (ja) * 2002-10-30 2004-05-27 Fujitsu Ltd 半導体装置及びその製造方法
US7435990B2 (en) * 2003-01-15 2008-10-14 International Business Machines Corporation Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer
US6744067B1 (en) * 2003-01-17 2004-06-01 Micron Technology, Inc. Wafer-level testing apparatus and method
US6995462B2 (en) * 2003-09-17 2006-02-07 Micron Technology, Inc. Image sensor packages
US7181837B2 (en) 2004-06-04 2007-02-27 Micron Technology, Inc. Plating buss and a method of use thereof
US8461675B2 (en) * 2005-12-13 2013-06-11 Sandisk Technologies Inc. Substrate panel with plating bar structured to allow minimum kerf width
WO2007074529A1 (ja) * 2005-12-27 2007-07-05 Fujitsu Limited 半導体装置
WO2008021125A2 (en) * 2006-08-14 2008-02-21 Dow Corning Corporation Method of preparing a patterned film with a developing solvent
US7829998B2 (en) * 2007-05-04 2010-11-09 Stats Chippac, Ltd. Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US7898066B1 (en) * 2007-05-25 2011-03-01 Amkor Technology, Inc. Semiconductor device having EMI shielding and method therefor
US7679384B2 (en) * 2007-06-08 2010-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Parametric testline with increased test pattern areas
JP2010087354A (ja) * 2008-10-01 2010-04-15 Fujitsu Microelectronics Ltd 半導体ウエハ及び半導体装置
US20100301398A1 (en) * 2009-05-29 2010-12-02 Ion Torrent Systems Incorporated Methods and apparatus for measuring analytes
US8168529B2 (en) * 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8349666B1 (en) * 2011-07-22 2013-01-08 Freescale Semiconductor, Inc. Fused buss for plating features on a semiconductor die

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6692629B1 (en) * 2000-09-07 2004-02-17 Siliconware Precision Industries Co., Ltd. Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer
TW484216B (en) * 2001-05-09 2002-04-21 Siliconware Precision Industries Co Ltd Singulation method of semiconductor package
US6566736B1 (en) * 2001-11-30 2003-05-20 Advanced Micro Devices, Inc. Die seal for semiconductor device moisture protection

Also Published As

Publication number Publication date
US20130309860A1 (en) 2013-11-21
US8519513B2 (en) 2013-08-27
JP2013140982A (ja) 2013-07-18
US20130168830A1 (en) 2013-07-04
CN103199021A (zh) 2013-07-10
US8895409B2 (en) 2014-11-25
JP6137832B2 (ja) 2017-05-31

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Address after: Texas in the United States

Patentee after: NXP America Co Ltd

Address before: Texas in the United States

Patentee before: Fisical Semiconductor Inc.

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