CN103199021B - Semiconductor wafer plating bus and molding method thereof - Google Patents
Semiconductor wafer plating bus and molding method thereof Download PDFInfo
- Publication number
- CN103199021B CN103199021B CN201210583531.9A CN201210583531A CN103199021B CN 103199021 B CN103199021 B CN 103199021B CN 201210583531 A CN201210583531 A CN 201210583531A CN 103199021 B CN103199021 B CN 103199021B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Abstract
The disclosure relates to a semiconductor wafer plating bus and a molding method thereof. A semiconductor wafer (10) includes a die (16), an edge seal (26, 266), a bond pad (36, 236), a plating bus (24, 224), and trace (30, 230). The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer (108, 308) of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.
Description
Technical field
The disclosure relates generally to semiconductor machining, more specifically it relates to semiconductor wafer plating bus
（semiconductor wafer plating bus）.
Background technology
In semiconductor machining, plating can be used to form wire bond pads, and in wire bond pads, metal level is plated in most
Forming pad on latter metal level.Plating can utilize electroless plating or electrolysis depositing process to carry out.In order that plating work with electrolysis
Feature is plated on the semiconductor wafer by skill, and plating bus layer is firstly applied on final passivation layer and subsequent after feature is plated
It is removed.However, the technique that the technique for applying and removing plating bus is to increase cost.Electroless plating is relatively inexpensive compared with electrolysis plating
Technique, in electroless plating, be not to form plating bus, but be activated for by the exposed metal surface of final passivation layer
Plating.However, electroless plating is more difficult to control and therefore causes yield reduction than electrolysis plating.
The content of the invention
According to an aspect of the present invention, a kind of semiconductor wafer may include：The tube core adjacent with swage set；Along the tube core
Periphery banding, wherein the banding includes the first conductive layer being formed in the last interconnection layer of the tube core；Pad, shape
Become the part of in the group including the metal deposition layer on the last interconnection layer and the last interconnection layer；Institute
State the plating bus in swage set；And be connected to the pad in such manner and be connected to the trace of the plating bus, the mode
Including one in the group comprising following item：（1）Above the banding, and banding insulation, and it is formed in the gold
In category sedimentary；And（2）Insulate through the banding and with the banding.
According to another aspect of the invention, a kind of method for forming semiconductor element may include：Existed using multiple interconnection layers
The semiconductor element is formed on semiconductor wafer；The banding around the tube core is formed in using the plurality of interconnection layer；Make
With a weldering formed on the tube core in the group including metal deposition layer and last interconnection layer in the plurality of interconnection layer
Disk；Plating bus is formed in swage set, wherein the banding is adjacent with the swage set；And using in including the plurality of interconnection layer
One and the metal deposition layer group in one form trace so that the pad is couple to the plating bus.
In accordance with a further aspect of the present invention, a kind of weldering that semiconductor element is plated on the chip with multiple semiconductor elements
The method of disk may include：The tube core is formed using multiple interconnection layers；Plating bus is formed in swage set, wherein the tube core and institute
State swage set adjacent；Pad is formed on the tube core；Form trace the pad is conductively coupled to the plating bus；And it is logical
Cross and the chip is immersed in plating liquor and is applied voltage to the plating bus, plate the pad.
Description of the drawings
The present invention is illustrated by way of example and is not limited to accompanying drawing, and in accompanying drawing, similar reference represents similar element.
Element in accompanying drawing is illustrated for simplicity and clarity, is not necessarily drawn to scale.
Fig. 1 illustrates the top view of semiconductor wafer according to an embodiment of the invention.
Fig. 2 illustrates the top view of a block of the semiconductor wafer of Fig. 1 according to an embodiment of the invention.
Fig. 3 illustrates the part according to one embodiment of the invention in the semiconductor wafer block of starting stage Fig. 2 of processing
Sectional view.
Fig. 4 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Fig. 3 of processing.
Fig. 5 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Fig. 4 of processing.
Fig. 6 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Fig. 5 of processing.
Fig. 7 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Fig. 6 of processing.
Fig. 8 illustrates the top view of a block of the semiconductor wafer according to one embodiment of the invention Fig. 1.
Fig. 9 illustrates the part according to one embodiment of the invention in the semiconductor wafer block of starting stage Fig. 8 of processing
Sectional view.
Figure 10 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Fig. 9 of processing.
Figure 11 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Figure 10 of processing.
Figure 12 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Figure 11 of processing.
Figure 13 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Figure 12 of processing.
Figure 14 illustrates the sectional view according to one embodiment of the invention in the part of the latter half Figure 13 of processing.
The sectional view of the part of Figure 14 when Figure 15 is illustrated according to one embodiment of the invention from terms of different sectional positions.
Specific embodiment
In one embodiment, being electrolysed depositing process is used to form pad on the semiconductor wafer, wherein by using last
Interconnecting metal layer, forms plating bus during the manufacture of semiconductor wafer.Last interconnecting metal layer deposited pad metal it
The front and formation before final passivation layer is deposited.Form metallurgical on disk being plated in using electrolysis in pad metal（OPM）Afterwards, always
Line is cut off and is abandoned during being connected to tube core singulation process.In this way, plate bus be not formed on final passivation layer with
In plating OPM in pad metal, and bus is plated without the need for remove after plating.Therefore, it is used for by using last interconnecting metal layer
Plating bus is formed, cost can be reduced.
Fig. 1 illustrates the top view of semiconductor wafer according to an embodiment of the invention 10.Semiconductor wafer 10 includes multiple
Semiconductor element 12, which is manufactured during the manufacture of semiconductor wafer 10 simultaneously.The plurality of tube core 12 includes semiconductor element 14
And the semiconductor element 16 adjacent with tube core 14.Block（section）18 represent semiconductor wafers 10 by reference picture 2-15 more
The block being discussed in detail.
Fig. 2 illustrates the top view of the block 18 of semiconductor wafer according to an embodiment of the invention 10.Block 18 includes pipe
A part for the part and tube core 16 of core 14, dotted line 22 represent the centrage between tube core 14 and 16 part（Corresponding to Fig. 1
The black solid line between tube core 14 and 16 in middle block 18）.Therefore, when the page is seen, the part of tube core 14 on 22 left side of dotted line,
The part of tube core 16 is on the right of dotted line 22.Tube core 16 includes pad 34,36 and 38, plates bus 24, trace 28,30 and 32 and side
Envelope 26.Tube core 16 also includes circuit 58, and its border is represented by dotted line 59.Therefore, the circuit 58 of tube core 16 is located on the right of border 59.
Banding 26 is positioned at the periphery along tube core 16.Banding 26 is located between border 59 and plating bus 24.In one embodiment, banding 26
Surround completely border 59 and tube core 16 circuit 58 and can be used as crack stop sealing, moisture seal or the two.Additionally, banding
26 may include any amount of concentric ring.Being each electrically coupled in pad 34,36 and 38 is plated total by trace 28,30 and 32 respectively
Line 24.In the embodiment shown, trace 28,30 and 32 is located on banding 26 and including the last metal interconnection in part of tube core 16
Layer, as the sectional view of reference picture 3-7 is more fully described.Trace 28,30 and 32 is located at the final passivation of tube core 16
Layer lower section.Tube core 14 includes pad 52,54 and 56, plates bus 42, trace 46,48 and 50 and banding 44.Tube core 14 also includes
Circuit 60, its border are represented by dotted line 61.Therefore, the circuit 60 of tube core 14 is located at 61 left side of border.Banding 44 is positioned at along pipe
The periphery of core 14.Banding 44 is located between border 61 and plating bus 42.In one embodiment, banding 44 surrounds 61 He of border completely
The circuit 60 of tube core 14, and can be used as crack stop sealing, moisture seal or the two.Additionally, banding 44 may include any number
The concentric ring of amount.Being each electrically coupled in pad 52,54 and 56 is plated bus 42 by trace 46,48 and 50 respectively.In shown reality
Apply in example, trace 46,48 and 50 is located on banding 44 and including the last metal interconnecting layer in part of tube core 14.Trace 46,48
It is located at below the final passivation layer of tube core 14 with 50.Note, the discussion with regard to tube core 16 being provided below also similarly is suitable for
In tube core 14.Swage set area 20 is located between the banding 44 and the banding 26 of tube core 16 of tube core 14.Banding 26 and 44 each and swage set
20 is adjacent.Additionally, chip 10 includes the Bussing connector 40 for electrically connecting plating bus 42 and 24.In this way, in electrolysis depositing process
Period, by using plating bus, all pads of chip 10 are plated simultaneously.During chip singulation, chip 10 will be in swage set
（Such as swage set 20）It is cut between inherent banding 44 and plating bus 42 and between banding 26 and plating bus 24, so as to cut off
Trace 46,48 and 50, trace 28,30 and 32 and Bussing connector 40.
Fig. 3 illustrates the sectional view of semiconductor structure 100, and which is represented in the processing starting stage along the intercepting of position 62 of Fig. 2
The sectional view of the part of the tube core 16 shown in Fig. 2.Semiconductor structure 100 includes Semiconductor substrate 102, is formed on the substrate 102
Active circuit layer 104, the interconnection layer 106 formed on active circuit layer 104 and the last gold formed on interconnection layer 106
Category interconnection layer 108.Substrate 102 can be any semi-conducting material or combination of materials, such as GaAs, SiGe, silicon-on-insulator
（SOI）, silicon, monocrystal silicon etc., and combinations of the above.Active circuit layer 104 represents the active circuit for wherein forming structure 100
Layer, and may include to perform any types circuit of any types function, active circuit is may be formed on substrate 102 and substrate 102
It is interior.With reference to Fig. 2, the active circuit of active circuit layer 104 is formed on the right of border 59.Interconnection layer 106 may include any amount of
Interconnection layer, wherein each interconnection layer may include interconnection layer（Also referred to as metal level）And being electrically connected between interconnection layer is provided
The path for connecing（via）Layer, interconnection layer may include the metal part of route signal in articulamentum internally（For example, pattern
Metal level）.In one embodiment, the metal part and path of interconnection layer 106 can be copper.Interconnection layer 106 is additionally included in interconnection
The banding 26 formed in the various metal levels and passage layers of layer 106.Banding 26 forms vertically extending continuous through interconnection layer 106
Metal level.Interconnection layer 106 also includes the insulant 107 of the metal part and path around interconnection layer 106.Last metal interconnection
Layer 108（Which is alternatively referred to as last interconnection layer）Including patterned metal layer, which includes can be in the pattern of last metal interconnecting layer 108
Change the metal part 114 and 112 of route signal in metal level.Top section of the last metal interconnecting layer 108 also including banding 26,
Which is connected to the passage portion immediately below of the banding 26 in interconnection layer 106.Metal part 114 in last metal interconnecting layer 108
Final metal layer is alternatively referred to as with the top metal part of 112 and banding 26 and can be formed by copper.Last metal interconnecting layer 108
It is additionally included on final metal layer（In metal part 114 and 112 and on banding 26）The first passivation layer 110.
Fig. 4 illustrates the sectional view of the part of the tube core 16 of the latter half Fig. 3 in processing.First passivation layer 110 is by pattern
Change to form opening 116,118 and 120.Be open 116 exposing metal parts 114, and be open 118 and 120 exposing metal parts 112
Zones of different.
Fig. 5 illustrates the sectional view of the part of the tube core 16 of the latter half Fig. 4 in processing.Patterned metal layer is formed in
On one passivation layer 110 and in opening 116,118 and 120.The Part I 122 of patterned metal layer is formed in opening 116
With in opening 118 and extend above banding 26.In this way, the electrical connection of part 122 metal part 114 and 112.Part 122
It is formed on the first passivation layer 110 and banding 26 and passivation layer 110 is located between part 122 and banding 26 so as to by banding 26
Electrically insulate with metal part 122.The Part II of patterned metal layer is formed in opening 120 and corresponding to the pad 36 of Fig. 2.
Note, patterned metal layer is alternatively referred to as pad metal layer, pad 36 is alternatively referred to as pad metal 36.Additionally, as shown in figure 5,
Plating bus 24 includes a block of part 122, and the part 123 of the remaining block and metal part 112 of part 122 is corresponding to figure
2 trace 30.Trace 30 is isolated with banding 26.
Fig. 6 illustrates the sectional view of the part of the tube core 16 of the latter half Fig. 5 in processing.Final passivation layer 124 is formed in
On first passivation layer 110 and in pad metal layer.Therefore, final passivation layer 110 is formed in metal part 122 and pad 36
On.Opening is formed in final passivation layer 124 expose pad 36, then metallurgy on disk（OPM）126 are formed in the sudden and violent of pad 36
On dew part.In one embodiment, during plating, voltage is applied to plating bus 24 and causes electric current by means of metal part 112, gold
Category part 122 and plating bus 24（Wherein metal part 122 and 112 corresponds to trace 30）It is applied to pad 36.In this way,
OPM126 can be electrolysed and be plated on pad 36.In one embodiment, by chip 10 to be immersed in plating liquor and apply a voltage to
Plating bus 24, OPM126 is plated on pad 36.OPM126 can be described as coating and may include any amount of coating.Implement one
In example, OPM126 includes nickel coating.Therefore, as shown in Figure 6, trace 30 and plating bus 24 are all located under final passivation layer 124
Side.Trace 30 includes extending in above banding 26 but still the part below final passivation layer 110（Corresponding to metal part
122 block）.Notice that swage set 20 is expressed as in figure 6 on the dotted line left side, wherein banding 26 is located in tube core 16, plate bus
24 are located in swage set 20.
Fig. 7 illustrates the sectional view of the part of the tube core 16 of the latter half Fig. 6 in processing.Chip 10 is singulated into, and this will pipe
Core 16 is separated with chip 10.Singulation occurs in swage set 20 and cuts off plating bus connection.That is, plating bus 24 and part mark
Line 30 is cut off from tube core 16.In this way, referring back to Fig. 2, as Bussing connector 40 is also turned off, so each pad
34th, 36 and 38 plating bus 24 is no longer electrically connected to, and plates bus 24 and be no longer attached to plate bus 42.
Therefore, in the embodiment shown in Fig. 2-7, without the need for increasing plating bus on final passivation layer 110 so that OPM to be electrolysed
It is plated in pad metal 36.Further, since plating bus is without the need for increasing on final passivation layer 110, so also without subsequent
Remove.
Fig. 8 illustrates the top view of the block 18 of semiconductor wafer according to another embodiment of the present invention 10.Block 18 includes
A part for the part and tube core 16 of tube core 14, dotted line 222 represent the centrage between tube core 14 and 16 part（Correspond to
Black solid line in Fig. 1 in block 18 between tube core 14 and 16）.Therefore, when the page is seen, the part of tube core 14 is left in dotted line 222
Side, the part of tube core 16 is on the right of dotted line 222.Tube core 16 includes pad 234,236 and 238, plates bus 224, trace 228,230
With 232, and banding 226.Tube core 16 also includes circuit 258, and its border is represented by dotted line 259.Therefore, the circuit of tube core 16
258 are located on the right of border 259.Banding 226 is positioned at the periphery along tube core 16.Banding 226 is located at border 259 and plating bus 224
Between.In one embodiment, banding 226 entirely around border 259 and tube core 16 circuit 258 and to can be used as crack stop close
Envelope, moisture seal or the two.Additionally, banding 226 may include any amount of concentric ring.Trace 228,230 and 232 respectively will weldering
Being each electrically coupled in disk 234,236 and 238 plates bus 224.In the embodiment shown, trace 228,230 and 232 is located at side
In envelope 226 and including the last metal interconnecting layer in part of tube core 16, such as the sectional view of reference picture 9-15 is discussed in more detail
Like that.Trace 228,230 and 232 is located at below the final passivation layer of tube core 16.Tube core 14 includes pad 252,254 and 256, plating
Bus 242, trace 246,248 and 250, and banding 244.Tube core 14 also includes circuit 260, and its border is represented by dotted line 261.
Therefore, the circuit 260 of tube core 14 is located at 261 left side of border.Banding 244 is positioned at the periphery along tube core 14.Banding 244 is located at side
Between boundary 261 and plating bus 242.In one embodiment, banding 244 entirely around border 261 and tube core 14 circuit 260 and
Can be used as crack stop sealing, moisture seal or the two.Additionally, banding 244 may include any amount of concentric ring.Trace 246,
Being each electrically coupled in pad 252,254 and 256 is plated bus 242 by 248 and 250 respectively.In the embodiment shown, trace
246th, 248 and 250 it is located on banding 244 and including the last metal interconnecting layer in part of tube core 14.Trace 246,248 and 250
Below the final passivation layer of tube core 14.Note, the discussion with regard to tube core 16 being presented below also is similarly applicable for tube core
14.Swage set region 220 is located between the banding 244 and the banding 226 of tube core 16 of tube core 14.Banding 226 and 244 each and swage set
220 is adjacent.Additionally, chip 10 includes Bussing connector 240, its electrical connection plating bus 242 and 224.In this way, in electrolysis plating
During technique, by using plating bus, all pads of chip 10 are plated simultaneously.During chip singulation, chip 10 will be
Swage set（Such as swage set 220）Cut between inherent banding 244 and plating bus 242 and between banding 226 and plating bus 224
Cut, so as to cut off trace 246,248 and 250, trace 228,230 and 232 and Bussing connector 240.
In the present example, trace 228,230,232,246,248 and 250 is located at below final passivation layer and is formed as
Through banding 226 or 244, rather than above banding.In one embodiment, for contact plating bus, some traces can be formed
On banding, and other are formed as through banding.
Fig. 9 illustrates the sectional view of semiconductor structure 300, and which represents and intercepts along the position 262 of Fig. 8 in the starting stage of processing
Fig. 8 shown in tube core 16 part sectional view.Semiconductor structure 300 includes Semiconductor substrate 302, is formed in substrate 302
On active circuit layer 304 and the interconnection layer 306 being formed on active circuit layer 104.Substrate 302 can be any quasiconductor
Material or combination of materials, such as GaAs, SiGe, silicon-on-insulator（SOI）, silicon, monocrystal silicon etc., and combinations of the above.Have
Source circuit layer 304 represents the layer of the active circuit for wherein forming structure 300, and can include performing any of any types function
Type circuit, active circuit are may be formed on substrate 302 and in substrate 302.With reference to Fig. 8, the active circuit of active circuit layer 304
It is formed on the right of border 259.Interconnection layer 306 may include any amount of interconnection layer, and wherein each interconnection layer may include that inside connects
Connect layer（Also referred to as metal level）And the passage layers of electrical connection between interconnection layer are provided, interconnection layer may include internally
The metal part of route signal in articulamentum（For example, patterned metal layer）.In the section of Fig. 9, the formation of interconnection layer 306 is not
Completely, so as to will be formed an at least extra play.Interconnection layer 306 also includes banding 226, and which is formed in the various gold of interconnection layer 306
In category layer and passage layers.In the section of Fig. 9, the formation of banding 226 is imperfect so as to form additional interconnection layer, and which will continue
The formation of banding 226.Interconnection layer 306 also includes the insulant 307 of the metal part and path around interconnection layer 306.In Fig. 9
In, interconnection layer 306 is additionally included in the metal part 310 and 312 of the top surface of interconnection layer 306.These routing sections 310 and 312
Can be described as tracking routing section, which will allow pad 236 is electrically connected to the formation of the trace 228 for plating bus 224.
Figure 10 illustrates the sectional view of the part of the tube core 16 of the latter half Fig. 9 in processing.308 shape of last metal interconnecting layer
Into above interconnection layer 306.Last metal interconnecting layer 308（Which is alternatively referred to as last interconnection layer）Including patterned metal layer, its
Including metal part 314,316 and 318.Metal part 314 and 318 can be in the patterned metal layer of last metal interconnecting layer 308
Interior route signal.Metal part 316 is the top section of banding 226.Note, metal part 314,316 and 318 can be described as finally
Metal level.Additionally, metal part 314 is connected at least one path 315 metal part 310 of interconnection layer 306, at least one
Metal part 318 is connected to path 317 metal part 310 of interconnection layer 306.At least one path 319,321 is by metal portion
Divide 318 metal parts 312 for being connected to interconnection layer 306.Last metal interconnecting layer 308 also includes insulant 309, metal part
It is formed in insulant 309 with path.Note, in the embodiment shown, banding 226 can still form continuous metal layer, and which is worn
Cross interconnection layer 106 to extend vertically；However, as will with reference to as figure 15 below is best seen from, banding 226 include opening,
Trace is formed as through opening.For example, metal part 318, at least one path 317, metal part 310, at least one are led to
Road 315 and metal part 314 form through banding 226 what is extended rather than isolate with banding 226 above banding 226 and still
Trace 230.In one embodiment, the metal part and path and last metal interconnecting layer 308 of interconnection layer 306 includes copper.
Figure 11 illustrates the sectional view of the part of the tube core 16 of the latter half Figure 10 in processing.First passivation layer 320 is formed
On final metal layer 308.Therefore, the first passivation layer 320 is formed in metal part 314,316 and 318.First passivation layer
320 are patterned to form opening 322,324 and 326.322 exposing metal part 314 of opening in first passivation layer 320, the
324 exposing metal part 316 of opening in one passivation layer 320（Which is a part for banding 226, therefore exposes banding 226）, the
326 exposing metal part 318 of opening in one passivation layer 320.In an alternative embodiment, opening 324 is not formed.
Figure 12 illustrates the sectional view of the part of the tube core 16 of the latter half Figure 11 in processing.Metal deposition layer（Which also may be used
Referred to as pad metal layer）It is formed on the first passivation layer 320, which includes the metal part being formed in opening 322, is formed in out
Mouth 324 is interior and makes electrical contact with metal parts 316（And therefore make electrical contact with banding 226）Metal part 330, and in opening 326
Metal part, be formed in opening 322 in metal part corresponding to plating bus 224 a part and make electrical contact with metal part
314, the metal part in opening 326 corresponds to pad 236 and makes electrical contact with metal part 318.Note, metal part 330 can
Referred to as banding part.Metal deposition layer can be formed by aluminum, in this case, can be described as al deposition layer.Note, last metal interconnection
The metal part 318 of layer 308（As shown in figure 12, its can extend laterally beyond metal deposition layer with 236 corresponding metal of pad
Part）A part for pad 236 can be also considered.Note, the metal part 310 in one of interconnection layer 306 is formed in direction
First side of tube core 16 extends transversely through banding 226 and is extending transversely through banding towards the second side of plating bus 224
226。
Figure 13 illustrates the sectional view of the part of the tube core 16 of the latter half Figure 12 in processing.Final passivation layer 328 is formed
Above the first passivation layer 320, and above pad metal layer.Therefore, final passivation layer 328 is formed in 224 He of metal part
330 and pad 236 above.Opening is formed in final passivation layer 328 to expose pad 236, then metallurgical on disk（OPM）
336 are formed on the expose portion of pad 236.In one embodiment, during plating, voltage is applied to plating bus 224 and causes electricity
Stream is by means of metal part 318, at least one path 317, metal part 310, at least one path 315,314 and of metal part
Plating bus 224（The metal part 318 that wherein extends from pad 236, path 317 and 315, metal part 310, and extend to
The metal part 314 of plating bus 224 corresponds to trace 230）.In this way, OPM336 can be electrolysed and be plated on pad 236.
In one embodiment, by chip 10 being dipped in plating liquor and applied voltage is to plating bus 224, OPM336 is plated to pad 236
On.OPM336 can be described as coating and may include any amount of coating.In one embodiment, OPM336 includes nickel coating.Therefore,
As shown in Figure 13, trace 230 and plating bus 224 are all located at below final passivation layer 328.Trace 230 includes extending through side
Envelope 226 and therefore the part that is still located at below final passivation layer 328（Corresponding to metal part 310）.Note, swage set 220 is in figure
The dotted line left side is shown in 13, wherein banding 226 is located in tube core 16, and plating bus 224 is located in swage set 220.
Figure 14 illustrates the sectional view of the part of the tube core 16 of the latter half Figure 13 in processing.Chip 10 is singulated into, and this will
Tube core 16 is separated from chip 10.Singulation occurs in swage set 220 and cuts off plating bus connection.That is, plating 224 He of bus
Partial trace 230 is cut off from tube core 16.In this way, referring back to Fig. 8, as Bussing connector 240 is also turned off, so often
Individual pad 234,236 and 238 is no longer electrically connected to plating bus 224, and plating bus 224 is no longer attached to plate bus 242.
Figure 15 illustrates the sectional view of the banding 226 of the Figure 14 intercepted along the direction vertical with the cross-wise direction of Figure 14.Also
To say, the section of Figure 15 illustrate just as in tube core 16 towards tube core 16 the edge in 226 opposition side of banding（Towards swage set
Where 220 is be located at）Banding 226 when looking out.As shown in Figure 15, interconnection layer 306 includes multiple paths of banding 226
Layer 340,342 and 344, and multiple metal levels 341,343 and 345 of banding 226.Final metal layer 308 includes banding 226
The metal level 316 of passage layers 346 and banding 226.Therefore, the metal of layer 340-346 shown in each and 316 expression bandings 226,
As described above, the metal may include copper.Opening is formed in layer 344-346, and metal part 310 extends through opening, is such as joined
According to as Fig. 9-14 descriptions.Therefore, although banding 226 is vertical continuous, but it be not it is solid continuous because it
Including opening, trace may pass through opening and extend to produce contact between pad and plating bus.
Therefore, in the embodiment shown in Fig. 8-15（As the embodiment in Fig. 2-7）, it is not necessary in final passivation layer
Increase plating bus on 328 with the electrolysis plating OPM in pad metal 236.Further, since without the need for increasing on final passivation layer 328
Plating bus, so removing also without subsequent.
So far it should be understood that having been provided for plating bus, which can be used for the pad below final passivation layer
A part for last metal interconnecting layer is plated and be make use of in electrolysis.Subsequent singulation has cut off the connection of plating bus.In this way, nothing
Plating bus need to be increased on final passivation layer and removed without the need for subsequent.
Additionally, term "front", "rear", " top ", " bottom " in specification and claims, " on ", D score etc., if
If, for descriptive purpose and not necessarily for description permanent relative positions.It should be understood that the term for so using is appropriate
In the case of be interchangeable so that embodiments of the invention described herein for example can with shown or in addition description here
Other different orientation operations of orientation.
Although describing the present invention referring herein to specific embodiment, can be carry out various modifications and variations without departing from
The scope of the present invention that claims are illustrated.For example, every trace can extend through banding in any interconnection layer, or
Person can be formed in above banding and remain at below final passivation layer.Therefore, will it is exemplary and in non-limiting sense
Treat specification and drawings, and all such modifications are intended to be included within the scope of this invention.Herein in relation to specific reality
Any benefit, advantage or the solution to problem for applying example description is all not intended to be interpreted the pass of any or all claim
Key, needs or essential feature or element.
Used here as when term " coupling " to be not intended to limit be directly coupling or machinery coupling.
Additionally, used here as when term "a" or "an" be defined as one or more.Additionally, introducing in claims
The use of property phrase such as " at least one " and " one or more " is should be not construed as to imply that by indefinite article " " or " one
It is individual " any specific rights requirement containing the claim element so introduced is restricted to by another claim element for introducing
Invention only containing a this element, even if identical claim includes introductory phrase " one or more " or " at least one
It is individual " and indefinite article such as "a" or "an".This is equally applicable to the use of definite article.
Unless otherwise stated, term such as " first " and " second " are for arbitrarily distinguishing the unit of these term descriptions
Element.Therefore, these terms are not necessarily intended to time or other orders of priority for representing these elements.
Various embodiments of the present invention are presented herein below.
Project 1 includes a kind of semiconductor wafer, and the semiconductor wafer includes：The tube core adjacent with swage set；Along the pipe
The banding of the periphery of core, wherein the banding includes the first conductive layer being formed in the last interconnection layer of the tube core；Pad,
Be formed as the part of in the group being made up of the metal deposition layer on the last interconnection layer and the last interconnection layer；
Plating bus, in the swage set；Trace, is connected to pad in one way and is connected to plating bus, and which is included by following
One in the group of composition：（1）Above the banding, insulate with the banding, and be formed in the metal deposition layer；With
And（2）Insulate through the banding and with the banding.Project 2 includes the semiconductor wafer of project 1, wherein the pad is also
The coating being included on the metal deposition layer of the pad.Project 3 includes the semiconductor wafer of project 2, wherein the plating
Layer includes nickel.Project 4 includes the semiconductor wafer of project 2, wherein the trace is connected to the pad and company by a mode
The plating bus is connected to, which is included on the banding, insulate with the banding, and be formed as the metal deposition layer
A part.Project 5 includes the semiconductor wafer of project 4, wherein the last interconnection layer includes copper.Project 6 includes the half of project 5
Conductor chip, wherein the pad is the last interconnection layer and the part both the metal deposition layer and including described
The Part I of last metal interconnecting layer.Project 7 includes the semiconductor wafer of project 6, wherein the pad have it is described last
A part for a part for metal interconnecting layer and the metal deposition layer, wherein the part of the last metal interconnecting layer is horizontal
To the part for extending beyond the metal deposition layer.Project 8 includes the semiconductor wafer of project 7, wherein the trace coupling
It is connected to the part of the last metal interconnecting layer.Project 9 includes the semiconductor wafer of project 2, wherein the trace is with one
Mode is connected to the pad and is connected to the plating bus, and which includes through the banding and with the banding insulating.
Project 10 includes the semiconductor wafer of project 9, wherein the banding is included from the multiple metals including the last interconnection layer
A part for each in sedimentary.Project 11 includes the semiconductor wafer of project 10, wherein the trace includes additional metal
A part for interconnection layer, wherein the part of the additional metal interconnection layer is extending laterally Jing towards the first side of the tube core
Cross the banding and the banding is being extended transversely through towards the second side of the plating bus.Project 12 includes the half of project 11
Conductor chip, wherein the trace also includes the first path of the Part I for being connected to the last interconnection layer and is connected to institute
The alternate path of the Part II of last interconnection layer is stated, wherein the Part I of the last interconnection layer is connected to the weldering
The Part II of disk and the last interconnection layer is connected to the plating bus.
Project 13 includes a kind of method for forming semiconductor element, including：Using multiple interconnection layers on the semiconductor wafer
Form the semiconductor element；Banding is formed around the tube core using the plurality of interconnection layer；Using by the plurality of interconnection layer
In metal deposition layer and last interconnection layer constitute group in one form pad on the tube core；Plating is formed in swage set
Bus, wherein the banding is adjacent with the swage set；And using by one of the plurality of interconnection layer and the metal deposition layer
One in the group of composition forms trace the pad is couple to the plating bus.Project 14 includes the method for project 13,
Also include the plating pad.Project 15 includes the method for project 14, wherein there is institute to the plating bus in response to applied voltage
State plating.Project 16 includes the method for project 15, is additionally included in the side of swage set described in the tailing edge of the plating by the banding and institute
State plating bus physical to separate, thus interrupt the trace and the pad and the plating bus are gone into coupling thus.Project 17
Including the method for project 16, wherein form the trace including using the metal deposition layer so as to the trace crosses the side
Seal and insulate with the banding.Project 18 includes the method for project 16, wherein form the trace including using the plurality of
One of interconnection layer is so as to the trace passes through the banding and insulate with the banding.
Project 19 includes a kind of method of the pad that semiconductor element is plated on the chip with multiple semiconductor elements, bag
Include：The tube core is formed using multiple interconnection layers；Plating bus is formed in swage set, wherein the tube core is adjacent with the swage set；
Pad is formed on the tube core；Form trace the pad is conductively coupled to the plating bus；By the chip is soaked
In plating liquor and apply voltage to the plating bus, plate the pad.Project 20 includes the method for project 19, also includes utilizing
The plurality of interconnection layer forms banding along the periphery of the tube core between the pad and the swage set；And make the trace
Interrupt to connect the pad and the plating bus electrically decoupling.
Claims (19)
1. a kind of semiconductor wafer, including：
The tube core adjacent with swage set；
Along the banding of the periphery of the tube core, wherein the banding includes first be formed in the last interconnection layer of the tube core
Conductive layer；
Pad, is formed as one in the group for include the metal deposition layer on the last interconnection layer and the last interconnection layer
A part；
Plating bus in the swage set；And
The pad is connected in such manner and the trace of the plating bus is connected to, and the mode includes the group comprising following item
In one：(1) above the banding, and banding insulation, and be formed in the metal deposition layer；And (2)
Insulate through the banding and with the banding.
2. semiconductor wafer as claimed in claim 1, wherein, the pad is additionally included in the metal deposit of the pad
Coating on layer.
3. semiconductor wafer as claimed in claim 2, wherein, the coating includes nickel.
4. semiconductor wafer as claimed in claim 2, wherein, the trace by being included in above the banding, it is and described
Banding insulation, and the mode of the part that is formed as the metal deposition layer be connected to the pad and be connected to the plating
Bus.
5. semiconductor wafer as claimed in claim 4, wherein, the last interconnection layer includes copper.
6. semiconductor wafer as claimed in claim 5, wherein, the pad is the last interconnection layer and the metal deposit
Layer the two a part and the Part I including the last metal interconnecting layer.
7. semiconductor wafer as claimed in claim 6, wherein, the pad has a part for the last metal interconnecting layer
With a part for the metal deposition layer, wherein the parts transversely of the last metal interconnecting layer extends beyond the metal
The part of sedimentary.
8. semiconductor wafer as claimed in claim 7, wherein, the trace is couple to the described of the last metal interconnecting layer
Part.
9. semiconductor wafer as claimed in claim 2, wherein, the trace with include through the banding and with the side
The mode of envelope insulation is connected to the pad and is connected to the plating bus.
10. semiconductor wafer as claimed in claim 9, wherein, the banding is included from including the last interconnection layer
The part of each in multiple metal deposition layers.
11. semiconductor wafers as claimed in claim 10, wherein, the trace includes a part for additional metal interconnection layer,
The part of wherein described additional metal interconnection layer towards the first side of the tube core extend transversely through the banding and
The banding is being extended transversely through towards the second side of the plating bus.
12. semiconductor wafers as claimed in claim 11, wherein, the trace also includes being connected to the last interconnection layer
First path of Part I and be connected to the last interconnection layer Part II alternate path, wherein the last interconnection
The Part I of layer is connected to the pad, and the Part II of the last interconnection layer is connected to the plating bus.
A kind of 13. methods for forming semiconductor element, including：
The semiconductor element is formed on the semiconductor wafer using multiple interconnection layers；
The banding around the tube core is formed in using the plurality of interconnection layer；
The tube core is formed using in the group including metal deposition layer and last interconnection layer in the plurality of interconnection layer
On pad；
Plating bus is formed in swage set, wherein the banding is adjacent with the swage set；And
Trace is formed with by institute using in the group including in the plurality of interconnection layer and the metal deposition layer
State pad and be couple to the plating bus.
14. methods as claimed in claim 13, also include：
Plate the pad.
15. methods as claimed in claim 14, wherein, the plating is carried out to the plating bus in response to applied voltage.
16. methods as claimed in claim 15, be additionally included in the side of swage set described in the tailing edge of the plating by the banding and
The plating bus physical is separated, and the trace is interrupted and the pad and the plating bus is gone coupling thus.
17. methods as claimed in claim 16, wherein, forming the trace is included using the metal deposition layer so as to described
Trace is passed through above the banding and is insulated with the banding.
18. methods as claimed in claim 16, wherein, forming the trace is included using in the plurality of interconnection layer
So as to the trace passes through the banding and insulate with the banding.
A kind of 19. methods of the pad that semiconductor element is plated on the chip with multiple semiconductor elements, including：
The tube core is formed using multiple interconnection layers；
Plating bus is formed in swage set, wherein the tube core is adjacent with the swage set；
Pad is formed on the tube core；
Banding is formed using periphery of the plurality of interconnection layer along the tube core between the pad and the swage set；
Form trace the pad is conductively coupled to the plating bus；
By the plating bus being immersed in plating liquor and applying voltage to by the chip, plate the pad；And
The trace is made to interrupt so that the pad and the plating bus electrically decoupling to be connect.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/343,318 US8519513B2 (en) | 2012-01-04 | 2012-01-04 | Semiconductor wafer plating bus |
| US13/343,318 | 2012-01-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103199021A CN103199021A (en) | 2013-07-10 |
| CN103199021B true CN103199021B (en) | 2017-04-12 |
Family
ID=48694186
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210583531.9A Active CN103199021B (en) | 2012-01-04 | 2012-12-28 | Semiconductor wafer plating bus and molding method thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US8519513B2 (en) |
| JP (1) | JP6137832B2 (en) |
| CN (1) | CN103199021B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9269622B2 (en) * | 2013-05-09 | 2016-02-23 | Deca Technologies Inc. | Semiconductor device and method of land grid array packaging with bussing lines |
| TWI559413B (en) | 2014-07-25 | 2016-11-21 | 力智電子股份有限公司 | Portable apparatus, ic packaging structure, ic packaging object, and ic packaging method thereof |
| US10566268B1 (en) | 2018-09-26 | 2020-02-18 | Nxp Usa, Inc. | Package to die connection system and method therefor |
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| US6136517A (en) * | 1998-03-06 | 2000-10-24 | Raytheon Company | Method for photo composition of large area integrated circuits |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20130168830A1 (en) | 2013-07-04 |
| US20130309860A1 (en) | 2013-11-21 |
| JP2013140982A (en) | 2013-07-18 |
| JP6137832B2 (en) | 2017-05-31 |
| CN103199021A (en) | 2013-07-10 |
| US8895409B2 (en) | 2014-11-25 |
| US8519513B2 (en) | 2013-08-27 |
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