TW484216B - Singulation method of semiconductor package - Google Patents

Singulation method of semiconductor package Download PDF

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Publication number
TW484216B
TW484216B TW090111004A TW90111004A TW484216B TW 484216 B TW484216 B TW 484216B TW 090111004 A TW090111004 A TW 090111004A TW 90111004 A TW90111004 A TW 90111004A TW 484216 B TW484216 B TW 484216B
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TW
Taiwan
Prior art keywords
semiconductor package
cutting
item
singulating
blade
Prior art date
Application number
TW090111004A
Other languages
Chinese (zh)
Inventor
Ji-Chiuan Wu
Jian-Ping Huang
Original Assignee
Siliconware Precision Industries Co Ltd
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Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW090111004A priority Critical patent/TW484216B/en
Application granted granted Critical
Publication of TW484216B publication Critical patent/TW484216B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Dicing (AREA)

Abstract

A singulation method of semiconductor package comprises the steps of providing a substrate and using a packaging party line with several palings to previously define several package units; disposing several temporal plating buses on the substrate along the extension direction of the packaging party line; after attaching die, soldering, encapsulation and solder ball implantation processes, disposing the substrate in a sickle machine to define several cutting line parallel to the extension direction of the plating bus so that the sickle head with double knife-edge can aim the lines for singulation. The two knifes of the sickle head are parallel to each other and the distance between them are larger than the predetermined width of the cutting line without touching the most outside solder ball. Therefore, the plating bus can be totally excised to avoid the package from the short circuit caused by remaining plating bus. Since the stress is reduced by using double knife-edge, the uniformity of the cutting edge after sigulation can be maintained.

Description

484216 A7 五、發明說明（1 ) 【發明領域】： 本發明係、關於-種半導禅封袭件之切早方法 指-種使用雙刀刃㈣頭切割機台之半導趙封裝件切單 方法。 平 【發明背景】： 現今微型半導體封裝件之製作多採成批方式，即 於一整片晶片承載件（ChipCarrier)表面藉由多條格 栅狀交錯之封裝分界線預先定義出複數個呈矩陣排列之 封裝單元’經過上片（DieBond)、銲接（WireB〇nd) 及膠體封裝（Encapsulation)等程序，最後施以切單作 業（Singulation)去除任相鄰半導體封裝單元間之連結 部而形成多個獨立的半導體封裝件。另一方面，隨著半 導體製程技術之進步，以及晶片電路功能的不斷提昇， 球柵陣列（BGA)半導體封裝件藉由植佈於基板底面上 之銲球（Solder Ball)提供該半導體晶片更多輸出增 入連接端以切合半導體裝置高度集積化之發展趨勢，因 此蔚為今後之封裝主流。 然製造BGA半導體封裝件係以一基板作為晶片承 載件，該基板為一環氧樹脂、聚亞醯胺樹脂、FR4樹脂、 陶瓷材料或耐高溫紙材構成之不導電材質，為使銲線作 業以及知球植置製程執行時得提供較佳之銲接環境，需 於基板表面敷設之導電跡線始端提供禽線銲接之銲接銲 墊（FingerPad)與該導電跡線末端得供該銲球植接之 銲球銲墊（Ball Pad )表面電鑛一鎳/金金属薄膜以作為 16005 訂 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製484216 A7 V. Description of the invention (1) [Field of invention]: The present invention relates to the early cutting method of a kind of semi-conductive Zen seal, which refers to a kind of semi-conductive Zhao package cutting using a double-edged hoe cutting machine. method. Flat [Background of the Invention]: Today, the production of micro-semiconductor packages is usually done in batches, that is, a plurality of grid-shaped interleaved packaging boundaries are used to define a plurality of matrixes on the surface of a chip carrier (ChipCarrier). The arrayed packaging units have undergone procedures such as DieBond, WireBond, and Encapsulation. Finally, Singulation is performed to remove any connection between adjacent semiconductor packaging units to form multiple independent units. Semiconductor package. On the other hand, with the advancement of semiconductor process technology and the continuous improvement of chip circuit functions, ball grid array (BGA) semiconductor packages provide the semiconductor chip with a solder ball that is implanted on the bottom surface of the substrate. The output is added to the connection terminal to meet the development trend of highly integrated semiconductor devices, so it will become the mainstream of packaging in the future. However, the manufacturing of BGA semiconductor packages uses a substrate as a wafer carrier. The substrate is an electrically non-conductive material composed of epoxy resin, polyurethane resin, FR4 resin, ceramic material or high temperature resistant paper material. And a better soldering environment can be provided during the implementation of the knowledge ball implantation process. A solder pad (FingerPad) for bird line welding and the end of the conductive trace need to be provided at the beginning of the conductive traces laid on the substrate surface can be used for the solder ball implantation. Ball pad surface nickel-gold metal film on the surface of the electric pad is used as the 16005 standard paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

484216 A7 ___________B7 五、發明說明（2 ) ^ -- 广銲連界面。沿著該等聽分界線方向佈設有多條臨時 陡之電鍍導線（Hating Bus )，該些電鍍導線側邊並分 枝有多條與該電鍵導線垂直地分布之側枝配線（Τγ^) 俾供電鍍電流得以經由該等側枝配線同時配送至基板各 個銲接銲墊及銲球銲墊上。待該電鍍作業完成以^，此 等電鑛導線與其分枝之側枝配線遂為一無用構件，需於 半導體封裝件進行切單作業時一併切割去除。 惟習知之半導體封裝件切單方法，係以一具有固 定寬度（約0.3mm) W3之單刃刀具進行定位切割 (Sawing ):亦即將該封裝完成具有複數個半導體封裝 裝置之基板置入切割機台内，該基板於機台上自動定位 一寬度W2之裁切道，該裁切道寬度之計算係依據該電 鍍導線寬度加減一定位精度容許偏差值（p〇siti〇n Tolerance)來決定，該定位精度容許偏差值愈大係顯 示自動定位之信賴性（Credibility)愈差，相對地不良 。口發生率將會提鬲。習知單刃刀具之刀片厚度界3 一般 係設計等寬於該裁切道寬度W2俾使定位完成後該刀具 得以對正該裁切道進行切割；然而，實際作業中往往因 為切割刀具之定位偏差、基板定位偏位或該裁切道對正 偏移等因素，致使該定位精度容許偏差值往往高達15% 以上造成切割位置顯著地偏誤，切單後之半導體封裝件 其電鍍導線因而難以完整地去除，如第1A圖所示。具 有部分殘存電鍍導線之半導體封裝件（參閱第1B圖） 造成電訊傳遞之短路。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） . Μ ----- i ί—----線 (請先閱讀背面之注意事項再填寫本頁) 16005 484216 A7 五、發明說明（3 ) 另者’由於習知之刀具係為一單刃刀具盆刀片 厚度又與該裁切道寬度相當，故而進行切割時:、基板裁 切部遭受刀片施壓之單位面積應力過強，切㈣力向兩 側延伸導致切單完叙半導體封裝件其邊緣部分發生裂 損’亦會造成產品不良率之增加。 【發明概述ί : 本發明之首要目的係提供一種利用具有雙刀刃切 割頭之77具切割半導體封裝件外圍之連接部，俾使該連 接部之電鍍導線得完全去除以避免切割不全之殘存電鍍 導線引#電訊短路之半導體封裝件切單方法。 ， 本發明之另一目的係提供一種藉由具有雙刀刃切 割頭之刀具切割半導髏封裝件外圍之連接部，避免刀具 產生定位偏差，造成該連接部之電鍍導線難以完整地去 除之半導體封裝件切單方法。 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 本發明之再一目的係提供一種藉由具有雙刀刃切 割頭之刀具切割半導體封裝#外圍之連接部以便降低該 切割頭施予該連接部之應力，使得切割完成之封裝件最 外側不致損傷之半導體封裝件切單方法。484216 A7 ___________B7 V. Description of the invention (2) ^-Wide welding interface. A plurality of temporarily steep plating wires (Hating Bus) are arranged along the direction of the audio demarcation lines, and the side of the plating wires are branched with a plurality of side branch wires (Tγ ^) distributed perpendicularly to the key wire. The plating current can be distributed to the solder pads and solder ball pads of the substrate at the same time through the side branch wiring. When the electroplating operation is completed, these electric smelting wires and their branched side branches are a useless component, which needs to be cut and removed together when the semiconductor package is singulated. However, the conventional method of singulating a semiconductor package is to perform positioning (Sawing) with a single-edged cutter having a fixed width (about 0.3 mm) W3: that is, the package is completed. A substrate with a plurality of semiconductor packaging devices is placed in the cutting machine. Inside the table, the substrate automatically positions a cutting path with a width W2 on the machine. The calculation of the cutting path width is based on the plated wire width plus or minus a positioning accuracy tolerance (p0). The larger the tolerance value of the positioning accuracy is, the worse the reliability of the automatic positioning (Credibility) is, which is relatively poor. Mouth incidence will increase. The blade thickness boundary 3 of the conventional single-edged cutter is generally designed to be as wide as the width of the cutting path W2, so that after the positioning is completed, the tool can cut the cutting path; however, the actual operation is often due to the positioning of the cutting tool. Deviations, substrate positioning misalignment, or the offset of the cutting path alignment, etc., the allowable deviation of the positioning accuracy is often as high as 15% or more, which results in significant deviations in the cutting position, and it is difficult to singulate semiconductor packages with plated wires. Completely removed, as shown in Figure 1A. A semiconductor package with some remaining plated wires (see Figure 1B) caused a short circuit in telecommunications transmission. The size of this paper applies to Chinese National Standard (CNS) A4 (210 X 297 mm). Μ ----- i ί —---- line (please read the precautions on the back before filling this page) 16005 484216 A7 V. Description of the invention (3) In addition, because the conventional cutter is a single-edged cutter, the blade thickness is equal to the width of the cutting path, so when cutting: the substrate cutting part is subject to the unit area stress of the blade pressure If the cutting force is too strong, the edge part of the semiconductor package will be cracked when the cutting order is extended to both sides, which will also increase the product defect rate. [Summary of the invention: The primary purpose of the present invention is to provide a connection portion of 77 cutting semiconductor packages with a double-edged cutting head, so that the plated wires of the connection portion can be completely removed to avoid incomplete cutting of the remaining plated wires. Induction #Single method of semiconductor package for short circuit. Another object of the present invention is to provide a semiconductor package that cuts the peripheral portion of a semiconductor package with a cutter having a double-edged cutting head to avoid positioning deviation of the cutter, which makes it difficult to completely remove the plated wires of the connection portion. Piece cut method. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Another object of the present invention is to provide a cutting portion with a double-edged cutting head for cutting a semiconductor package # peripheral portion so as to reduce the stress imposed on the connecting portion by the cutting head, so that A method of singulating a semiconductor package without damaging the outermost package after the dicing is completed.

鑒於上揭及其他目的，本發明之半導癍封裝件切 單方法係包括：先備一球栅陣列基板，並以多條格柵分 布之封裝分界線預先定義出複數個基板單元，且於該基 板上沿著該等封裝分界線設置有多條電鑛導線及其分枝 之側枝配線；經過上片、銲接、膠體封裝及銲球植接等 程序’於該基板上建構多數個半導體封裝裝置後，旋即 邮 4216 五、發明說明（4 ) 覃入一切割機台内進行切單。In view of the above disclosure and other purposes, the method for singulating a semiconductor device package according to the present invention includes: preparing a ball grid array substrate, and predefining a plurality of substrate units with a plurality of grid-distributed packaging boundaries, and A plurality of electrical and mining wires and their side branches are arranged on the substrate along the packaging demarcation lines; a plurality of semiconductor packages are constructed on the substrate through procedures such as wafer loading, welding, gel packaging, and solder ball implantation. After installation, immediately post 4216 V. Description of the invention (4) Tan entered a cutting machine and cut the order.

該切割機台順應電鍵導線伸展方向自動定位一適 當寬度之裁切道俾供一雙刀刃切割頭對正切割。此一雙 刀刃切割頭具有兩片相互平行之刀片，且二刀片旋轉切 割方向係平行於電鍍導線之伸展方向，並且其刀片寬度 小於該裁切道寬度之半；另外，切割實際寬度乃取決於 兩平行刀片之間距’該間距須大於該裁切道之預設寬度 但以不觸及半導體封裝件之最外側銲球為限P 本發明半導體封裝件之切單方法採用之該雙刀刃 切割頭其兩刀片間距（即實際之切割寬度）大於該裁切 道預設寬度，因此即使實際作業中刀具或基板產生定位 偏誤，該電鍍導線仍然含括於實際切割寬度範圍内，故 而該基板上佈設之電鍍導線能夠徹底地切除乾淨，避免 切單完成之半導體封裝件含有任何殘存之電鍍導線，確 保該半導體封裝件内殘餘之側枝配線殘部皆為斷路狀 態，有效地防止短路發生。 此外，由於該切割頭兩刀片之間距係小於兩相鄰 半導體封裝件最外側銲球之相隔距離故可避免切割時破 壞最外側銲球結構，且該相互平行之二刀片厚度俱相 同，皆係小於該裁切道厚度之半，致使切割作業進行時 該基板承受之早位面積應力得以分攤，俾使切單完成之 半導體封裝件之邊緣部分可保持結構完整性，降低封裝 製品不良率。 【圖式簡單說明】： --------------I---- (請先閱讀背面之注意事項再填寫本頁) 訂- 丨線 經濟部智慧財產局員工消費Θ作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 16005 484216 A7The cutting machine automatically locates an appropriate width cutting path in accordance with the extension direction of the key wire for a pair of blade cutting heads to align. This double-edged cutting head has two blades that are parallel to each other, and the rotating direction of the two blades is parallel to the extension direction of the electroplated wire, and the blade width is less than half of the width of the cutting path; in addition, the actual cutting width depends on The distance between two parallel blades must be greater than the preset width of the cutting path, but is limited to the outermost solder ball that does not touch the semiconductor package. The double-blade cutting head used in the method for singulating a semiconductor package of the present invention has The distance between the two blades (that is, the actual cutting width) is larger than the preset width of the cutting path. Therefore, even if the positioning error of the cutter or substrate occurs in the actual operation, the plated wire is still included in the actual cutting width. Therefore, the substrate is laid on the substrate. The plated wires can be completely cut off to avoid any remaining plated wires in the finished semiconductor package, ensuring that the remaining side branch wiring residues in the semiconductor package are all open, effectively preventing short circuits. In addition, because the distance between the two blades of the cutting head is less than the distance between the outermost solder balls of two adjacent semiconductor packages, the outermost solder ball structure can be avoided from being damaged during cutting, and the thickness of the two blades that are parallel to each other is the same. It is less than half the thickness of the cutting path, so that the early area stress on the substrate when the cutting operation is performed can be shared, so that the edge portion of the semiconductor package completed after the singulation can maintain the structural integrity and reduce the defective rate of the packaging products. [Schematic description]: -------------- I ---- (Please read the notes on the back before filling out this page) Order-丨 Line of Economic Affairs Intellectual Property Bureau Staff Consumption Printed by Θ. The size of this paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 4 16005 484216 A7

五、發明說明（5 ) 以下兹以較佳具體例配合所附圖式進一步詳述本 發明之特點及功效： 第1A圖及第1B圖係為習知刀具切割BGA基板時 發生定位偏誤之上視周； 第2圖係為一 BGA基板利用本發明之切單方法進 行定位之上視圖； 第3圖係為本發明之雙刀刃切割頭及其刀片之剖 撓圖； 第4圖係為本發明之雙刀刃切割頭及其刀片之立 體圖； 第5A至5C圖係利用本發明之半導體封裝件切單 方法之整體流程示意圖；以及， 第6圖係為使用本發明之切單方法切割完成之β^α 半導體封裝件上視圖。 【發明詳細說明】： 以下即配合第2至6圖詳細揭露使用本發明半導 體封裝件切單方法製得複數個BGA半導體封裝單元。 然需強調一點，下述實施例僅係針對直向方向之切割程 序進行說明，惟半導體封裝件外圍連結部之橫向部分如 若分佈有電鏡導線與其分枝之侧枝配線，則本發明亦適 用於切除橫向部分之該電鍍導線及其側枝配線。 請參閱第2圖，於一整片之薄型球栅陣列（Thiil & Fine Ball Grid Array, TFBGA)基板1上藉由多條格柵 分布之封裝分界線L〇預先定義出複數個呈矩陣列置之 (請先閱讀背面之注意事項再填寫本頁) 裝 —"訂-— 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5 16005 484216 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（6 ) 封裝區域2，每一封裝區域2内預設有一提供至少一値 半導體晶片4安置之晶片接置區20，並於該晶片接置 區20外圍敷設有多數之導電跡線2 1 ;另外，沿著該等 封裝分界線L〇之基板1表面設置有多條格栅狀之電鍍 導線3 (該導線直徑約01 mm)，且該等電鍍導線3側 邊並分枝有複數條垂直於所屬電鍍導線3之側枝配線 3〇’以提供電鍍電流同時配送至各封裝區域2之多數導 電跡線2 1内。經過上片、銲諫，以及膠體封裝等製程， 於該基板1上一體形成有藉由一封裝膠體5包覆該半導 體晶片4而構成之半導體封裝裝置6，最後實施植球製 程’於該基板1背面形成有複數個電性導通之銲球7， 即可採用本發明之切單方法進行切割。 本發明之半導體封裝件切單方法係先將該.封裝完 成之基板1置入一切割機台（未圖示），該切割刀具9 銜接一雙刀刃切割頭90，如第3圖（剖視圖）與第4 圖（立體圖）所示，該切割頭9〇係安裝有一第一刀片 91與一平行於該第一刀片91之第二刀片92,兩刀片 91，92旋轉切割方向係平行於該電鍍導線3之伸展方向 且該第一及第二刀片91，92具有相同之厚度W3，即小 於該裁切道22寬度W2之半；而該切割頭9〇得視需要 調整該第一刀片91與第二刀片92之間距％俾決定實 際切割寬度’兩刀片91，92間距w須大於該定位預設 之裁切道22寬度W?，但尚未觸及半導體封裝件6最外 側銲球7為⑯，兩相鄰半導體封裝件6最外側銲球7間 度適用t國國家標準(CNS)XJ^各⑽χ 297公釐） 16005 --------------裝---i ! -----訂 ---線 (請先閱讀背面之注意事項再填寫本頁) 484216 A7 五、發明說明（7 ) 之距離係以表示（如第3圖中半導體封裝件最外側 球界線L i ’ L i ’之相隔距離W!所示）。 第5A至5C圖係明確表示利用本發明之半導體封 裝件切單方法切割薄型球栅陣列基板1形成多數個切單 完成之獨立BGA半導體封裝件的整體流程示意圖，所 有切割製程倶如習知，故於此不再贅述。經過本發明之 切單方法分割之BGA半導體封裝件6,如第6圖所示， 由於該箄刀刃切割頭90之兩刀片91，92間距W (即實 際之切割寬度）係大於該預設之裁切道寬度w2，因此 即使實際作業中刀具或基板發生定位偏誤，該電鍍導線 3仍然含括於實際切射寬度範圍之内俾使該基板丨上佈 设之電錢導線3能夠徹底地切除乾淨，避免切單完成之 BGA半導體封裝件6含有任何殘存之電鍍導線3，確保 該BGA半導體封裝件内殘餘之側枝配線3〇殘部3〇〇皆 為斯路狀態，有效地防止短路發生。同時，該第一與第 二刀片91，92係相互年行且其刀片厚度W3係小於該裁 切道22厚度W2冬半，致使切割作業進行時該基板i 承艾之單位面積應力得以分攤不致使封裝結構外側受 損。 以上所述者僅為本發明之較佳具體實例，並非用 以限定本發明可實施之範圍。其他任何未脫離本發明所 揭示之精神或原理下所完成之等效改變或修飾，均應視 作包含於後述之本發明申請專利範圍涵蓋範疇内。 【元件符號標示】： (請先閱讀背面之注音？事項再填寫本頁) 裝---------,101/11 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印V. Description of the invention (5) The following is a detailed description of the features and effects of the present invention with better specific examples and the attached drawings: Figures 1A and 1B are examples of positioning errors that occur when a conventional cutter cuts a BGA substrate. Top view week; Figure 2 is a top view of the positioning of a BGA substrate using the cutting method of the present invention; Figure 3 is a cross-sectional view of the double-blade cutting head and its blade of the present invention; Figure 4 is Three-dimensional views of the double-blade cutting head and its blades of the present invention; Figures 5A to 5C are schematic diagrams of the overall process of using the semiconductor package cutting method of the present invention; and, Figure 6 is completed using the cutting method of the present invention Top view of β ^ α semiconductor package. [Detailed description of the invention]: A plurality of BGA semiconductor packaging units made by using the semiconductor package cutting method of the present invention are disclosed in detail below with reference to FIGS. 2 to 6. However, it should be emphasized that the following embodiments are only described for the cutting process in the vertical direction. However, if the lateral portion of the semiconductor package's peripheral connection is distributed with the wire of the microscope and the side branches of the branches, the present invention is also suitable for cutting A lateral portion of the plated wire and its side branch wiring. Please refer to FIG. 2, a plurality of grid-arranged packaging boundary lines L0 are predefined on a whole thin-ball grid array (Thiil & Fine Ball Grid Array, TFBGA) substrate 1 in a matrix form. Set it (please read the precautions on the back before filling this page) Packing— " Order --- Printed by the Employee Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297 mm) ) 5 16005 484216 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (6) Packaging areas 2, each packaging area 2 is preset with a wafer receiving area 20 that provides at least one stack of semiconductor wafers 4 And a plurality of conductive traces 2 1 are laid on the periphery of the wafer receiving area 20; in addition, a plurality of grid-shaped plated wires 3 (the diameter of the wires are provided along the surface of the substrate 1 along the packaging boundary lines L0) About 01 mm), and the side of the plated wires 3 are branched with a plurality of side branch wires 30 ′ perpendicular to the corresponding plated wires 3 to provide the plating current to the majority of the conductive traces 21 in each packaging area 2 . After the processes of wafer loading, soldering, and colloid packaging, a semiconductor packaging device 6 formed by encapsulating the semiconductor wafer 4 with an encapsulant 5 is integrally formed on the substrate 1, and finally a ball-implanting process is performed on the substrate. 1. A plurality of electrically conductive solder balls 7 are formed on the back surface, and the cutting method of the present invention can be used for cutting. The method for cutting a semiconductor package according to the present invention is to first place the packaged substrate 1 into a cutting machine (not shown), and the cutting tool 9 is connected to a double-blade cutting head 90, as shown in FIG. 3 (cross-sectional view). As shown in FIG. 4 (perspective view), the cutting head 90 is provided with a first blade 91 and a second blade 92 parallel to the first blade 91. The two blades 91 and 92 rotate in a cutting direction parallel to the plating. The extension direction of the wire 3 and the first and second blades 91, 92 have the same thickness W3, that is, less than half of the width W2 of the cutting path 22; and the cutting head 90 may adjust the first blade 91 and The distance between the second blades 92% 俾 determines the actual cutting width. The distance w between the two blades 91 and 92 must be greater than the width W of the cutting path 22 of the positioning preset, but the outermost solder ball 7 of the semiconductor package 6 is ⑯. The distance between the outermost solder balls 7 of two adjacent semiconductor packages 6 is applicable to the national standard (CNS) XJ ^ each ⑽χ 297 mm) 16005 -------------- packing --- i ! ----- Order --- line (please read the precautions on the back before filling this page) 484216 A7 V. The description of invention (7) is based on (Shown as the separation distance W! Of the outermost ball boundary line L i ′ L i ′ of the semiconductor package in FIG. 3). Figures 5A to 5C are schematic diagrams showing the overall flow of cutting the thin ball grid array substrate 1 using the semiconductor package singulation method of the present invention to form a plurality of singulated independent BGA semiconductor packages. All cutting processes are as known, Therefore, I will not repeat them here. The BGA semiconductor package 6 divided by the singulation method of the present invention, as shown in FIG. 6, because the pitch W of the two blades 91, 92 of the guillotine cutting head 90 is greater than the preset cutting width. The width of the cutting path w2, so even if the positioning error of the cutter or the substrate occurs in actual operation, the plated wire 3 is still included in the actual cutting width range, so that the electric money wire 3 laid on the substrate can be completely The BGA semiconductor package 6 that has been cut off completely to avoid any remaining electroplated wires 3 is ensured, and the remaining side branch wirings 30 and 300 in the BGA semiconductor package are all in a sway state, which effectively prevents a short circuit from occurring. At the same time, the first and second blades 91, 92 are running each other and their blade thickness W3 is smaller than the thickness W2 of the cutting path 22 in the winter half, so that the unit area stress of the substrate i Cheng Ai is not shared during the cutting operation. As a result, the outside of the package structure is damaged. The above are merely preferred specific examples of the present invention and are not intended to limit the scope of the present invention. Any other equivalent changes or modifications made without departing from the spirit or principle disclosed by the present invention shall be deemed to be included in the scope of patent application of the present invention described later. [Component symbol indication]: (Please read the phonetic on the back? Matters and then fill out this page) Install ---------, 101/11 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperatives

484216 A7 B7 五、發明說明（8) 1 BGA基板 2 封裝區域 21 導電跡線 3 電鍍導線 4 半導體晶片 6 半導體封裝件 9 刀具 ❿91第一刀片 W 兩刀片間鉅 W2裁切道寬戽 L〇 封裝分界線 20 晶片接置區 22 截切道 3 0 側枝配線 5 封裝膠體 7 銲球 90 雙刀刃切割頭 92 第二刀片 Wx 最外側銲球相隔距離 W3 刀片厚度 -------------裝------ ί !訂-—— (請先閱讀背面之注意事項再填寫本頁) •線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 8 16005^484216 A7 B7 V. Description of the invention (8) 1 BGA substrate 2 Package area 21 Conductive traces 3 Plating wires 4 Semiconductor wafers 6 Semiconductor packages 9 Tool 第一 91 First blade W Giant W2 cutting path width between two blades 戽 L0 package Demarcation line 20 Wafer receiving area 22 Cutting path 3 0 Side branch wiring 5 Packaging gel 7 Solder ball 90 Double-blade cutting head 92 Second blade Wx The outermost solder ball is separated by a distance W3 Blade thickness ---------- --- Pack -------- ί! Order -—— (Please read the notes on the back before filling in this page) • The paper size printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard (CNS ) A4 size (210 X 297 mm) 8 16005 ^

Claims (1)

484216 六、申請專利範圍 > •一種半導體封裝件之切單方法，係包括下列步驟： 先備一晶片承載件，藉以多條格栅分布之封裝分 界線預設有複數個矩陣列置之封裝單元，且沿該封裝 分界線之該晶片承載件本設置多锋臨時性之導電線； 之後將該封裝元成之晶片承載件置入^一切割機 台内以定位出多條順應該等電線伸展方向之裁切道俾 供一裝設有雙刀刃切割頭之刀具對正切割，其中，連 接該切割頭之兩刀片之間鉅係大於該裁切道寬度且不 觸及半導體封裝件最外側之導電元件為限。 2·如申請專利範圍第1項之半導體封裝件之切單方法， 其中’該半導體封裝單元係為一 BGa半導體封裝單 元。 3·如申請專利範圍第i項、之半導體封裝件之切單方法， 其中，該晶片承載件係為一薄型球柵陣列基板。 線 4·如申請專利範圍第1項之半導體封裝件之切單方法， 其中，該導電線係為一電鍍導線（plating Bus )，該電 鍍導線之側邊並分枝有複數條側枝配線（Trace)俾利 電鍍電流同時配送至各半導體封裝單元内。 方 徑 5.如申請專利範圍第！或4項之半導體封裝件之切單 法，其中，該裁切道寬度係取決於該電鍍導線之直 寬度加減一定位精度容許偏差值計算所得之預設值< 6·如申請專利範圍第i項之半導體封裝件之切單方法， 其中，該雙刀刃切割頭上安置之兩刀片係相互平行。 申請專利範圍第半導體封裝件之切單方法, 人㈣用，，標準（CNS)、規格（21G X 297公望） 16005 9 484216 A8 B8 C8 D8 、申請專利範圍 其中，該雙刀刃切割頭上安置之兩刀片其旋轉切割方 向係平行於該電鍍導線之伸展方向。 如申請專利範圍苐1項之半導體封裝件之切單方法， 其中，該雙刀刃切割頭上安置之兩刀片其厚度相同， 且該刀片厚度係小於該截切道預設寬度之半。 9·如申請專利範圍第i項之半導體封裝件之切單方法， 其中’該雙刀刃切割頭上安置之兩刀片間距係用以決 定一切割實際寬度。 、 10·如申請專利範圍帛1項<半導體封裝件之切單方法， 其中，該導電元件，係為銲球。 裝-----.！1訂丨.---!!線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公.¾ ) 1600S484216 VI. Scope of Patent Application > • A method for cutting a semiconductor package, including the following steps: Prepare a wafer carrier first, and use a plurality of grid-arranged packaging boundaries to preset a plurality of matrix array packages. Unit, and the chip carrier along the boundary line of the package is provided with multiple frontal temporary conductive wires; then the chip carrier formed by the package element is placed into a cutting machine to locate a plurality of compliant wires The cutting path in the extending direction is used for a cutting tool equipped with a double-edged cutting head, in which the distance between the two blades connecting the cutting head is larger than the width of the cutting path and does not touch the outermost side of the semiconductor package. The number of conductive elements is limited. 2. The method of singulating a semiconductor package according to item 1 of the scope of application, wherein the semiconductor package unit is a BGa semiconductor package unit. 3. The method for singulating a semiconductor package according to item i of the application, wherein the wafer carrier is a thin ball grid array substrate. Line 4: The method for singulating a semiconductor package as described in item 1 of the scope of patent application, wherein the conductive line is a plating bus, and the side of the plated lead is branched with a plurality of side branch wirings (Trace ) Lili plating current is distributed to each semiconductor packaging unit at the same time. Path 5. If the scope of patent application is the first! Or the method of singulating a semiconductor package according to item 4, wherein the width of the cutting path is a preset value calculated based on the straight width of the plated wire plus or minus a positioning accuracy tolerance value < 6 · The method for singulating a semiconductor package according to item i, wherein the two blades arranged on the double-blade cutting head are parallel to each other. The patent application scope of the semiconductor package cutting method, for human use, standard (CNS), specifications (21G X 297 public hope) 16005 9 484216 A8 B8 C8 D8, in the patent application scope, the two blade cutting head is placed two The rotating cutting direction of the blade is parallel to the extending direction of the plated wire. For example, the method for singulating a semiconductor package according to item 1 of the patent application, wherein the two blades arranged on the double-blade cutting head have the same thickness, and the blade thickness is less than half of the preset width of the cutting path. 9. The method for singulating a semiconductor package according to item i of the application, wherein 'the distance between the two blades placed on the double-blade cutting head is used to determine the actual width of a cut. 10. If the scope of the patent application: Item 1 < Singulation method of a semiconductor package, wherein the conductive element is a solder ball. Install -----.! 1 Order 丨 .--- !! Line (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297) .¾) 1600S
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103199021A (en) * 2012-01-04 2013-07-10 飞思卡尔半导体公司 Semiconductor wafer plating bus and molding method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103199021A (en) * 2012-01-04 2013-07-10 飞思卡尔半导体公司 Semiconductor wafer plating bus and molding method thereof
CN103199021B (en) * 2012-01-04 2017-04-12 飞思卡尔半导体公司 Semiconductor wafer plating bus and molding method thereof

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