TWI841393B - Method for reducing solder joints in semiconductor package structures - Google Patents
Method for reducing solder joints in semiconductor package structures Download PDFInfo
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- TWI841393B TWI841393B TW112118975A TW112118975A TWI841393B TW I841393 B TWI841393 B TW I841393B TW 112118975 A TW112118975 A TW 112118975A TW 112118975 A TW112118975 A TW 112118975A TW I841393 B TWI841393 B TW I841393B
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- lead frame
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 24
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000004806 packaging method and process Methods 0.000 claims abstract description 16
- 238000009713 electroplating Methods 0.000 claims abstract description 13
- 239000000084 colloidal system Substances 0.000 claims abstract description 6
- 238000005476 soldering Methods 0.000 claims abstract description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 1
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 210000002435 tendon Anatomy 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
一種減少半導體封裝結構發生連錫的方法，其步驟包括：使用完成封裝且未切割的封裝導線架，封裝導線架包括導線架及封裝膠體，導線架包括晶粒座、數個引腳以及與數個引腳相連的連接肋，連接肋為具有雙層且由不同尺寸的底層筋及連筋所構成，連筋相接於引腳且連接處的寬度小於引腳的最大寬度；進行第一次切割，切除連接肋的底層筋，僅殘留連筋，每個連筋仍相連於引腳；進行電鍍作業，使引腳、連筋外露表面形成金屬層；進行第二次切割，去除連接肋的連筋，形成已封裝完成的單一半導體結構，藉此減少發生連錫的機會，提升製程良率。A method for reducing soldering of semiconductor packaging structure, the steps of which include: using a packaged and uncut package lead frame, the package lead frame includes a lead frame and a package colloid, the lead frame includes a die seat, a plurality of pins and a connecting rib connected to the plurality of pins, the connecting rib is double-layered and composed of bottom ribs and connecting ribs of different sizes, the connecting ribs are connected to the pins and the connecting ribs are The width is smaller than the maximum width of the lead; the first cutting is performed to remove the bottom ribs of the connecting ribs, leaving only the connecting ribs, and each connecting rib is still connected to the lead; the electroplating operation is performed to form a metal layer on the exposed surface of the lead and the connecting ribs; the second cutting is performed to remove the connecting ribs of the connecting ribs to form a packaged single semiconductor structure, thereby reducing the chance of solder joints and improving the process yield.
Description
本發明為一種半導體封裝製程之技術領域，尤其指一種減少半導體封裝結構發生連錫的方法。 The present invention relates to a technical field of semiconductor packaging process, and in particular to a method for reducing solder joints in semiconductor packaging structures.
方形扁平無引脚封裝(Quad Flat No-lead Package,QFNP)，為現今半導體業界的晶片封裝中越來越普遍的趨勢，QFN封裝的優點是體積小，足以媲美CSP(Chip Scale Package)封裝，而且成本也相對便宜，生產製程良率高，能為高速和電源管理電路提供較佳的共面性以及散熱能力等優點。此外，QFN封裝不必從四側引出接腳，因此電氣效能更勝必須從側面引出多接腳等傳統封裝。 Quad Flat No-lead Package (QFNP) is an increasingly common trend in chip packaging in the semiconductor industry today. The advantages of QFN packaging are small size, comparable to CSP (Chip Scale Package) packaging, relatively low cost, high production process yield, and better coplanarity and heat dissipation for high-speed and power management circuits. In addition, QFN packaging does not require pins to be led out from the four sides, so the electrical performance is better than traditional packaging that must lead out multiple pins from the side.
隨著電子技術和半導體封裝技術的發展，半導體尺寸越來越小，積體電路引腳之間的間距也愈來愈小，方形扁平無引腳封裝(QFNP，Quad Flat No-lead Package)的半導體結構最能滿足此要求，但因相鄰引腳間距更小，常發生連錫問題，造成成品存在短路的風險。此連錫問題的發生時機是在將大面積的封裝導線架切割成個別的半導體結構的過程中，其主要原因是為了使引腳安裝在電路板上能獲得良好的電性連接效果，會事先以電鍍方式於引腳表面附著一層錫層。作業方式如圖1A所示，為已封裝完成且經第一次切割之數引腳所在處的局部放大圖，圖中數引腳91由連接部92所相連，數引腳91周圍為封裝膠體93，切割道94的寬度為鄰近連接部92如圖面中的上下兩側實線區域。如圖1B所示， 施作電鍍作業後會於金屬的引腳91及連接部92表面形成錫層95，圖中錫層95以斜線表示。如圖中可發現，錫層95的面積涵蓋整個連接部92，第二次切割是沿切割道94將連接部92去除，然而在進行第二切割時，因引腳91間隔小，於連接部92表面的錫層95面積過大，切割刀片切割時也會容易將延展佳的錫層95向外延伸，讓部份錫沾黏於相鄰兩引腳91間，出現連錫問題，進而造成成品存在短路的風險。 With the development of electronic technology and semiconductor packaging technology, the size of semiconductors is getting smaller and smaller, and the spacing between integrated circuit pins is also getting smaller and smaller. The semiconductor structure of the Quad Flat No-lead Package (QFNP) can best meet this requirement, but because the spacing between adjacent pins is smaller, soldering problems often occur, resulting in the risk of short circuits in the finished product. This soldering problem occurs when the large-area package lead frame is cut into individual semiconductor structures. The main reason is that in order to obtain a good electrical connection effect when the pins are installed on the circuit board, a layer of solder will be attached to the surface of the pins by electroplating in advance. The operation method is shown in FIG1A, which is a partial enlarged view of the location of the digital pins that have been packaged and cut for the first time. In the figure, the digital pins 91 are connected by the connecting part 92, and the digital pins 91 are surrounded by the packaging gel 93. The width of the cutting path 94 is the solid line area on the upper and lower sides of the figure adjacent to the connecting part 92. As shown in FIG1B, after the electroplating operation, a tin layer 95 will be formed on the surface of the metal pins 91 and the connecting part 92. The tin layer 95 is represented by a slash in the figure. As can be seen in the figure, the area of the tin layer 95 covers the entire connection part 92. The second cutting is to remove the connection part 92 along the cutting path 94. However, during the second cutting, due to the small spacing between the pins 91, the area of the tin layer 95 on the surface of the connection part 92 is too large. The cutting blade will easily extend the well-extended tin layer 95 outward during cutting, allowing part of the tin to adhere between two adjacent pins 91, resulting in a solder joint problem, which in turn causes the risk of short circuit in the finished product.
本發明之主要目的是提供一種減少半導體封裝結構發生連錫的方法，主要降低電鍍作業後連接於相對應兩引腳之的金屬層面積，如此在進行第二次切割時，就能大幅減少連錫發生的機會，進而提昇製程良率。 The main purpose of the present invention is to provide a method to reduce the occurrence of solder joints in semiconductor packaging structures, mainly by reducing the area of the metal layer connected to the two corresponding pins after the electroplating operation. In this way, when performing the second cutting, the chance of solder joints can be greatly reduced, thereby improving the process yield.
為實現前述目的，本發明採用了如下技術方案： In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:
本發明為一種減少半導體封裝結構發生連錫的方法，其步驟包括：使用完成封裝且未切割的封裝導線架，該封裝導線架包括導線架及包覆該導線架的封裝膠體，該導線架包括數個單元，每個單元包括至少一晶粒座、分佈於該晶粒座周圍的數個引腳，以及連接於數個引腳的連接肋，該連接肋為具有不同尺寸的雙層結構，分別為底層筋及連筋，該連筋相接於該引腳且連接處的寬度小於該引腳的最大寬度；進行第一次切割，切除該連接肋的該底層筋，僅殘留該連筋，每個該連筋仍相連於該引腳；進行電鍍作業，使該引腳、該連筋表面形成金屬層；進行第二次切割，去除該連接肋的該連筋，形成已封裝完成的單一半導體結構。 The present invention is a method for reducing soldering of semiconductor packaging structure, the steps of which include: using a packaged and uncut package lead frame, the package lead frame includes a lead frame and a package glue covering the lead frame, the lead frame includes a plurality of units, each unit includes at least one die seat, a plurality of pins distributed around the die seat, and a connecting rib connected to the plurality of pins, the connecting rib is a double-layered bonding rib with different sizes. The structure is divided into a bottom rib and a connecting rib, wherein the connecting rib is connected to the pin and the width of the connection is less than the maximum width of the pin; the first cutting is performed to remove the bottom rib of the connecting rib, leaving only the connecting rib, and each connecting rib is still connected to the pin; the electroplating operation is performed to form a metal layer on the surface of the pin and the connecting rib; the second cutting is performed to remove the connecting rib of the connecting rib to form a packaged single semiconductor structure.
作為較佳優選實施方案之一，每個該晶粒座設置至少一晶粒，另設有多個引線連接於該晶粒及所對應的該引腳。 As one of the preferred implementation schemes, each die seat is provided with at least one die, and a plurality of leads are provided to connect the die and the corresponding pins.
作為較佳優選實施方案之一，該底層筋及該連筋呈堆疊相連的雙層結構，該連筋相連於相鄰兩個該單元對應的該引腳之間，該底層筋相連於數個該連筋及數個該引腳。 As one of the preferred implementation schemes, the bottom layer ribs and the connecting ribs are stacked and connected in a double-layer structure, the connecting ribs are connected between the pins corresponding to two adjacent units, and the bottom layer ribs are connected to several connecting ribs and several pins.
作為較佳優選實施方案之一，該連筋連接於該引腳的寬度小於該引腳的連接處寬度。 As one of the preferred implementation schemes, the width of the connecting rib connected to the pin is smaller than the width of the connection point of the pin.
作為較佳優選實施方案之一，該金屬層為錫層或錫合金層。 As one of the preferred implementation schemes, the metal layer is a tin layer or a tin alloy layer.
作為較佳優選實施方案之一，該導線架具有位置對的第一面及第二面，該連接肋的該連筋位於該第一面，該底層筋位於該第二面，進行切割時皆由該第二面的方向進行。 As one of the preferred implementation schemes, the wire frame has a first surface and a second surface in a positional pair, the connecting rib of the connecting rib is located on the first surface, and the bottom rib is located on the second surface, and the cutting is performed from the direction of the second surface.
與現有技術相比，本發明減少半導體封裝結構發生連錫的方法是在第一次切割去除連接肋的大部份結構，僅殘留與小面積的連筋與引腳相連，如此後續電鍍時讓金屬層的錫或錫合金面積縮小，例如金屬層由大面積附著於習用該連接部表面，改為現今小面積於該連筋表面，如此可減少切斷時發生錫沾黏現象，消除成品可能造成引腳短路問題，提昇製程良率及生產效率。 Compared with the prior art, the method of reducing the occurrence of solder joints in the semiconductor package structure of the present invention is to remove most of the structure of the connecting ribs in the first cutting, leaving only the small area of the connecting ribs connected to the pins, so that the area of tin or tin alloy in the metal layer is reduced during the subsequent electroplating. For example, the metal layer is changed from being attached to the surface of the connecting part in a large area to being attached to the surface of the connecting rib in a small area. This can reduce the occurrence of solder sticking during cutting, eliminate the problem of short circuit of the pins in the finished product, and improve the process yield and production efficiency.
91:引腳 91: Pin
92:連接部 92:Connection part
93:封裝膠體 93: Packaging colloid
94:切割道 94: Cutting Road
95:錫層 95:Tin layer
10:封裝導線架 10: Encapsulating lead frame
20:導線架 20: Conductor frame
21:晶粒座 21: Die seat
22:引腳 22: Pins
23:連接肋 23: Connecting ribs
231:底層筋 231: Bottom reinforcement
232:連筋 232: Connecting tendons
30:封裝膠體 30: Packaging colloid
40:晶粒 40: Grain
50:引線 50: Lead wire
60:切割道 60: Cutting Road
80:金屬層 80:Metal layer
90:半導體結構 90:Semiconductor structure
L1:連筋寬度 L1: Width of connecting bars
L2:最大寬度 L2: Maximum width
L3:連接處寬度 L3: Width of connection
圖1A為習用已封裝之導線架進行第一切割後的局放大圖。 Figure 1A is a partial enlarged view of the packaged lead frame after the first cut.
圖1B為習用已封裝之導線架進行電鍍後的局放大圖。 Figure 1B is a partial enlargement of the encapsulated lead frame after electroplating.
圖2為本發明所使用的封裝導線架的立體圖。 Figure 2 is a three-dimensional diagram of the package lead frame used in the present invention.
圖3為圖2之AA面的剖面圖。 Figure 3 is a cross-sectional view of the AA surface in Figure 2.
圖4為本發明導線架之局部放大的立體圖。 Figure 4 is a partially enlarged three-dimensional diagram of the lead frame of the present invention.
圖5為本發明導線架之仰視角的立體圖。 Figure 5 is a three-dimensional diagram of the lead frame of the present invention from an upward angle.
圖6為本發明連筋與引腳連接處的平面放大圖。 Figure 6 is an enlarged plan view of the connection between the connecting rib and the lead pin of the present invention.
圖7為本發明之流程圖。 Figure 7 is a flow chart of the present invention.
圖8為本發明之封裝導線架的仰視圖。 Figure 8 is a bottom view of the package lead frame of the present invention.
圖9A為本發明之封裝導線架進行第一次切割後的立體圖。 FIG. 9A is a three-dimensional diagram of the package lead frame of the present invention after the first cutting.
圖9B為本發明之封裝導線架進行第一次切割後的平面圖。 FIG9B is a plan view of the package lead frame of the present invention after the first cutting.
圖10為本發明之封裝導線架進行電鍍作業的平面圖。 Figure 10 is a plan view of the electroplating process of the package lead frame of the present invention.
圖11為本發明之封裝導線架進行第二次切割後的平面示意圖。 Figure 11 is a schematic plan view of the package lead frame of the present invention after the second cutting.
下面將結合具體實施例和附圖，對本發明的技術方案進行清楚、完整地描述。需要說明的是，當元件被稱為「安裝於或固定於」另一個元件，意指它可以直接在另一個元件上或者也可以存在居中的元件。當一個元件被認為是「連接」另一個元件，意指它可以是直接連接到另一個元件或者可能同時存在居中元件。在所示出的實施例中，方向表示上、下、左、右、前和後等是相對的，用於解釋本案中不同部件的結構和運動是相對的。當部件處於圖中所示的位置時，這些表示是恰當的。但是，如果元件位置的說明發生變化，那麼認為這些表示也將相應地發生變化。 The technical solution of the present invention will be described clearly and completely below in conjunction with specific embodiments and drawings. It should be noted that when an element is referred to as being "mounted on or fixed to" another element, it means that it can be directly on the other element or there can also be a central element. When an element is considered to be "connected" to another element, it means that it can be directly connected to the other element or there can be a central element at the same time. In the embodiments shown, the directions of up, down, left, right, front and back are relative, and are used to explain that the structure and movement of different components in this case are relative. These representations are appropriate when the components are in the positions shown in the figures. However, if the description of the position of the components changes, it is believed that these representations will also change accordingly.
除非另有定義，本文所使用的所有技術和科學術語與屬於本發明技術領域的技術人員通常理解的含義相同。本文中所使用的術語只是為了描述具體實施例的目的，不是旨在限制本發明。本文所使用的術語「和/或」包括一個或多個相關的所列項目的任意的和所有的組合。 Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field of the present invention. The terms used in this article are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and/or" used in this article includes any and all combinations of one or more of the relevant listed items.
本發明減少半導體封裝結構發生連錫的方法，會使用完成封裝且未切割的封裝導線架10。如圖2及3所示，封裝導線架10包括導線架20及封裝膠體 30，導線架20包括數個單元，每個單元為包括一個晶粒座21、分佈於晶粒座21周圍的數個引腳22，以及連接於數個引腳22的連接肋23。在圖2及圖3的實施例中僅畫出四個單元，單元的實際數目可依廠商設計而定。最後切割成型後每個單元即構成一個半導體結構。晶粒座21上設置至少一個晶粒40，每個晶粒40經由數個引線50與對應的引腳22相接，本實施例中封裝導線架10是採用現有封裝製程，故不再詳加描述，本發明採用的導線架20與現有技術略為不同，以下特此說明。 The method of reducing soldering in semiconductor package structures of the present invention uses a package lead frame 10 that has been packaged and not cut. As shown in FIGS. 2 and 3 , the package lead frame 10 includes a lead frame 20 and a package colloid 30. The lead frame 20 includes a plurality of units, each of which includes a die seat 21, a plurality of pins 22 distributed around the die seat 21, and a connecting rib 23 connected to the plurality of pins 22. In the embodiments of FIGS. 2 and 3 , only four units are drawn, and the actual number of units can be determined according to the manufacturer's design. After cutting and forming, each unit constitutes a semiconductor structure. At least one die 40 is arranged on the die seat 21, and each die 40 is connected to the corresponding pin 22 via a plurality of leads 50. The package lead frame 10 in this embodiment adopts the existing packaging process, so it will not be described in detail. The lead frame 20 used in the present invention is slightly different from the existing technology, which is specially explained below.
如圖4及圖5為導線架不同角度的結構放大圖。導線架20包括數個單元，為了便於說明，後續圖面中僅於導線架20中畫出一個單元結構，圖中假想線所示區域即為一個單元涵蓋之區域。每個單元由一個晶粒座21、分佈於晶粒座21周圍的數個引腳22，以及連接於數個引腳22的連接肋23所構成。連接肋23為具有不同尺寸的雙層結構，分別為底層筋231及連筋232。連筋232相連於相鄰兩個單元的所對應的兩個引腳22之間，底層筋231相連於數個連筋232及數個引腳22。導線架20具有位置相對的第一面及第二面，第一面俗稱正面，為晶粒座21上置放晶粒40的表面，也是引腳22供引線50連接晶粒40的表面，連筋232也是形成於此面連接於相鄰兩引腳22之間(如圖4所示)。第二面俗稱背面，底層筋231位於第二面(如圖5所示)，在切割時將整個結構翻轉，由第二面方向進行切割。另外如圖6所示，連筋232的連筋寬度L1是小於引腳22的最大寬度L2，在本實施例連筋232連接於引腳22的連筋寬度L1甚至小於引腳22的連接處寬度L3。在本實施例中是利用半蝕刻方式將導線架20加工形成連筋232的形狀及引腳22的形狀，也因為連筋232面積最小，有助於後續電鍍層的面積減少。 FIG4 and FIG5 are enlarged views of the structure of the lead frame at different angles. The lead frame 20 includes several units. For the convenience of explanation, only one unit structure is drawn in the lead frame 20 in the subsequent drawings. The area indicated by the imaginary line in the figure is the area covered by one unit. Each unit is composed of a die seat 21, several pins 22 distributed around the die seat 21, and connecting ribs 23 connected to the several pins 22. The connecting ribs 23 are double-layer structures with different sizes, including bottom ribs 231 and connecting ribs 232. The connecting ribs 232 are connected between two corresponding pins 22 of two adjacent units, and the bottom ribs 231 are connected to several connecting ribs 232 and several pins 22. The lead frame 20 has a first surface and a second surface that are positioned opposite to each other. The first surface is commonly known as the front surface, which is the surface on which the die 40 is placed on the die seat 21, and is also the surface of the lead 22 for the lead 50 to connect the die 40. The connecting rib 232 is also formed on this surface and connected between two adjacent pins 22 (as shown in FIG. 4 ). The second surface is commonly known as the back surface, and the bottom rib 231 is located on the second surface (as shown in FIG. 5 ). When cutting, the entire structure is turned over and cut from the second surface direction. In addition, as shown in FIG. 6 , the connecting rib width L1 of the connecting rib 232 is smaller than the maximum width L2 of the pin 22. In this embodiment, the connecting rib width L1 where the connecting rib 232 is connected to the pin 22 is even smaller than the width L3 of the connection point of the pin 22. In this embodiment, the lead frame 20 is processed by semi-etching to form the shape of the connecting rib 232 and the shape of the lead 22. Because the connecting rib 232 has the smallest area, it helps to reduce the area of the subsequent electroplating layer.
接著就本發明減少半導體封裝結構發生連錫的方法作一詳細的說明，如圖7所示，為本發明之流程圖，其步驟包括： Next, a detailed description is given of the method of reducing solder joints in semiconductor package structures according to the present invention. As shown in FIG7 , it is a flow chart of the present invention, and the steps include:
步驟701，使用完成封裝且未切割的封裝導線架10，封裝導線架10的結構如上所述，封裝導線架10包括導線架20及包覆於導線架20的封裝膠體30，導線架20包括數個單元，每個單元包括一晶粒座21、分佈於晶粒座21周圍的數個引腳22，以及連接於數個引腳22的數個連接肋23。連接肋23為具有不同尺寸的雙層結構，分別為底層筋231及連筋232，連筋232相接於引腳22且連接處的寬度小於引腳22的最大寬度；如圖8所示，為封裝導線架10的底視圖，因封裝膠體30已封裝於導線架20上方，導線架20之第二面僅露出晶粒座21、數引腳22及底層筋231，圖中假想線為預定的切割道60位置及寬度。 In step 701, a packaged and uncut package lead frame 10 is used. The structure of the package lead frame 10 is as described above. The package lead frame 10 includes a lead frame 20 and a package gel 30 coated on the lead frame 20. The lead frame 20 includes a plurality of units, each of which includes a die seat 21, a plurality of leads 22 distributed around the die seat 21, and a plurality of connecting ribs 23 connected to the plurality of leads 22. The connecting rib 23 is a double-layer structure with different sizes, which is composed of a bottom rib 231 and a connecting rib 232. The connecting rib 232 is connected to the lead 22 and the width of the connection is less than the maximum width of the lead 22. As shown in FIG8, it is a bottom view of the package lead frame 10. Since the package colloid 30 has been packaged on the lead frame 20, only the die pad 21, a few leads 22 and the bottom rib 231 are exposed on the second side of the lead frame 20. The imaginary line in the figure is the predetermined position and width of the cutting path 60.
步驟702，進行第一次切割，切除連接肋23的底層筋231，僅殘留連筋232，每個連筋232仍相連於引腳22，如圖9A及圖9B所示，沿切割道60進行第一次切割後，亦對相鄰於連筋232的引腳22作小部份的切除，最後僅留連筋232連接於對應的兩引腳22之間。 Step 702, the first cutting is performed to remove the bottom rib 231 of the connecting rib 23, leaving only the connecting rib 232, each connecting rib 232 is still connected to the lead 22, as shown in Figures 9A and 9B, after the first cutting is performed along the cutting path 60, a small portion of the lead 22 adjacent to the connecting rib 232 is also removed, and finally only the connecting rib 232 is left connected between the corresponding two leads 22.
步驟703，進行電鍍作業，使引腳22、連筋232表面形成金屬層80。此作業須將封裝導線架10取下，另置於電鍍槽內進行電鍍，使如圖10所示，於晶粒座21、引腳22及連筋232所在位置的裸露表面皆形成一層金屬層80，在本實施例中金屬層80為錫層或錫合金層。由圖中可知，因連筋232寬度小於引腳22的寬度，因此附著於連筋232的金屬層80較於習用方式(如圖1B所示)減少了許多。 Step 703, electroplating is performed to form a metal layer 80 on the surface of the lead 22 and the connecting rib 232. This operation requires the package lead frame 10 to be removed and placed in a plating tank for electroplating, so that as shown in FIG10, a metal layer 80 is formed on the exposed surface of the die seat 21, the lead 22 and the connecting rib 232. In this embodiment, the metal layer 80 is a tin layer or a tin alloy layer. As can be seen from the figure, because the width of the connecting rib 232 is smaller than the width of the lead 22, the metal layer 80 attached to the connecting rib 232 is much reduced compared to the conventional method (as shown in FIG1B).
步驟704，進行第二次切割，去除連接肋23的連筋232，形成已封裝完成的單一半導體結構90。如圖11所示，使用切割刀片將封裝導線架10 完全切斷，亦同時切除連筋232及此處的封裝膠體30，形成單獨的半導體結構90，半導體結構90底部僅留晶粒座21及分佈於周圍的數個引腳22。本發明因僅留小面積的連筋232表面附著金屬層80，第二次切割(完全切斷)時，小面積金屬層80不容易被拉伸擴散，就不容易發生錫沾黏於相鄰引腳22，因此以本發明方法加工而成的成品，就不容易發生的引腳短路問題，本發明方法能有效解決連錫問題，讓製程良率提昇。 Step 704, a second cutting is performed to remove the connecting ribs 232 of the connecting ribs 23, forming a packaged single semiconductor structure 90. As shown in FIG11, the package lead frame 10 is completely cut off using a cutting blade, and the connecting ribs 232 and the packaging gel 30 therein are also removed to form a single semiconductor structure 90, with only the die pad 21 and several pins 22 distributed around the bottom of the semiconductor structure 90 remaining. The present invention only leaves a small area of the connecting rib 232 with the metal layer 80 attached to the surface. During the second cutting (complete cutting), the small area of the metal layer 80 is not easily stretched and diffused, and it is not easy for the solder to adhere to the adjacent pins 22. Therefore, the finished product processed by the method of the present invention is not prone to the problem of pin short circuit. The method of the present invention can effectively solve the problem of solder connection and improve the process yield.
綜合以上所述，本發明減少半導體封裝結構發生連錫的方法是採用特殊形狀的導線架，即導線架中連接相鄰兩引線的連接肋為具有不同尺寸的雙層結構，有利於第一次切割去除大部份的結構，僅殘留與小面積的連筋與引腳相連，藉此後續電鍍時讓鍍錫面積縮小，如此可減少切斷時發生錫沾黏現象，消除成品可能造成引腳訊號短路的問題，提昇製程良率。 In summary, the method of reducing the occurrence of solder joints in semiconductor packaging structures of the present invention is to use a lead frame of a special shape, that is, the connecting ribs connecting two adjacent leads in the lead frame are double-layer structures with different sizes, which is conducive to removing most of the structure in the first cutting, leaving only the small area of the connecting ribs connected to the pins, thereby reducing the tinning area during subsequent electroplating, thereby reducing the occurrence of solder sticking during cutting, eliminating the problem of short circuit of the pin signal in the finished product, and improving the process yield.
以上所述者，僅為本發明之較佳實施例而已，並非用來限定本發明實施例之範圍。即凡依本發明申請專利範圍所作的均等變化及修飾，皆為本發明之專利範圍所涵蓋。 The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the embodiments of the present invention. That is, all equivalent changes and modifications made according to the scope of the patent application of the present invention are covered by the patent scope of the present invention.
701~704:步驟 701~704: Steps
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| CN202310565208.7A CN116682740A (en) | 2023-05-18 | 2023-05-18 | Method for reducing tin connection of semiconductor packaging structure |
| CN2023105652087 | 2023-05-18 |
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|---|---|---|---|---|
| US20120292755A1 (en) * | 2011-05-18 | 2012-11-22 | Freescale Semiconductor, Inc. | Flank wettable semiconductor device |
| TWM534433U (en) * | 2016-09-30 | 2016-12-21 | Chang Wah Technology Co Ltd | Separated-type pre-formed packaging lead frame |
| CN109950159A (en) * | 2019-03-11 | 2019-06-28 | 嘉盛半导体(苏州)有限公司 | A kind of method for packaging semiconductor |
| CN111987002A (en) * | 2020-09-04 | 2020-11-24 | 长电科技（滁州）有限公司 | Package forming method |
| TW202228254A (en) * | 2021-01-05 | 2022-07-16 | 南茂科技股份有限公司 | Leadframe strip and its manufacturing method applied to semiconductor package structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120292755A1 (en) * | 2011-05-18 | 2012-11-22 | Freescale Semiconductor, Inc. | Flank wettable semiconductor device |
| TWM534433U (en) * | 2016-09-30 | 2016-12-21 | Chang Wah Technology Co Ltd | Separated-type pre-formed packaging lead frame |
| CN109950159A (en) * | 2019-03-11 | 2019-06-28 | 嘉盛半导体(苏州)有限公司 | A kind of method for packaging semiconductor |
| CN111987002A (en) * | 2020-09-04 | 2020-11-24 | 长电科技（滁州）有限公司 | Package forming method |
| TW202228254A (en) * | 2021-01-05 | 2022-07-16 | 南茂科技股份有限公司 | Leadframe strip and its manufacturing method applied to semiconductor package structure |
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