CN109950159A - A kind of method for packaging semiconductor - Google Patents
A kind of method for packaging semiconductor Download PDFInfo
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- CN109950159A CN109950159A CN201910179715.0A CN201910179715A CN109950159A CN 109950159 A CN109950159 A CN 109950159A CN 201910179715 A CN201910179715 A CN 201910179715A CN 109950159 A CN109950159 A CN 109950159A
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- connection strap
- metal substrate
- cutting road
- metal
- road connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention discloses a kind of method for packaging semiconductor, comprising the following steps: provides a metal substrate；Metal substrate has opposite obverse and reverse, and metal substrate includes multiple operating units, and operating unit includes pin, and the pin of two neighboring operating unit is connected by Cutting Road connection strap；Semiconductor chip is pasted and is conductively connected；Semiconductor chip is fixed on to the front of metal substrate, pin is electrically connected with semiconductor chip；Plastic packaging；Plastic packaging layer is formed in metal substrate front, plastic packaging layer coats the front of semiconductor chip and metal substrate comprehensively；Hemisect；The Cutting Road connection strap is cut in metal substrate reverse side, forms groove, adjacent operating unit is after completing hemisect still in conductive interconnection state；Cutting Road connection strap generates metal burr in half-cut process；Remove metal burr；Form the first protective layer；Full cutting.Method for packaging semiconductor provided herein can be effectively removed the metal fragment formed in cutting step or wire residual.
Description
Technical field
This application involves technical field of semiconductor encapsulation more particularly to a kind of method for packaging semiconductor.
Background technique
The description of this part, which is only provided, discloses relevant background information to the present invention, without constituting the prior art.
In order to meet requirement of the certain industries (such as auto electronics product) to semiconductor package product higher performance, need
Protective layer is formed on the side of semiconductor package product pin, prevents pin side from aoxidizing, to improve semiconductor package product
Reliability and solderability when being connect with other components.
Notification number for CN204834611U provide it is a kind of can be formed in the side of semiconductor package product pin it is anti-oxidation
The known embodiments of protective layer, the known embodiments the specific implementation process is as follows:
As shown in FIG. 1A and 1B, leadframe strip is provided.The leadframe strip includes multiple leadframes units, is drawn
Wire frame unit includes central pad area 16 and the multiple pins 12 for being arranged in central 16 surrounding of pad area, central 16 He of pad area
The centre of pin 12 is equipped with gap 18, and design has connection strap 14 at two neighboring leadframes unit, so that multiple lead frames
Unit is connected to each other.
As shown in Figure 1 C, semiconductor chip adherency and wire bonding.Then the glue coated layer 20 on central pad area 16 will
Semiconductor chip 22 is adhered on glue-line 20, and the miniature weld pad on semiconductor chip 22 and the pin of leadframe strip 12 are utilized
Lead 24 connects.
As shown in figure iD, plastic packaging.Semiconductor chip 22 and the whole claddings of lead 24 are got up using plastic packaging material 26, pin 12
Plastic packaging material 26 is also filled in gap 18 between central pad area 16, and pin 12 and the back side of central pad area 16 are exposed.
As referring to figure 1E, hemisect.Hemisect is carried out to the connection strap 14 of leadframe strip, depth of cut is lead frame
The 70%-80% of thickness, most preferably 75%, so that forming groove 32 at leadframe strip connection strap 14.
As shown in fig. 1F, protective layer is formed.By way of plating, at the back side of pin 12 and central pad area 16, with
And additional metal layer 28 is formed on the side wall and roof of groove 32.
As shown in Figure 1 G, full cutting separation.It carries out leadframe strip on the basis of hemisect to cut entirely, full cutting openings
Width is less than hemisect opening width but is greater than the width of leadframe strip connection strap 14.L is formed in the side edge of pin 12
The groove 32 of shape is coated on the side wall of groove 32 with pin 12 in the identical of package bottom and the additional gold of plating that is integrally connected
Belong to layer 28, the final semiconductor packages unit obtained as shown in fig. 1H.
Due to when implementing half cutting process as referring to figure 1E, easily forming a large amount of metal fragments or wire residual.
This, which will lead to, forms bridge joint between the pin of finally obtained semiconductor packages unit, so as to cause short circuit, cause product failure,
Production yield is low.
It should be noted that the above description of the technical background be intended merely to it is convenient to technical solution of the present invention carry out it is clear,
Complete explanation, and facilitate the understanding of those skilled in the art and illustrate.Cannot merely because these schemes of the invention
Background technology part is expounded and thinks that above-mentioned technical proposal is known to those skilled in the art.
Summary of the invention
In view of the deficiencies in the prior art, the first purpose of the application is to provide a kind of method for packaging semiconductor, can have
The metal fragment or wire residual formed in effect ground removal cutting technique, to eliminate the semiconductor packages list therefore caused
It is short-circuit caused by the bridge joint formed between first adjacent leads, while guaranteeing semiconductor packages element solder reliability, improve
Product quality promotes yields, realizes mass production.
In order to achieve the above objectives, the application adopts the following technical scheme that
A kind of method for packaging semiconductor, comprising the following steps:
One metal substrate is provided；The metal substrate has opposite obverse and reverse, and the metal substrate includes multiple
Operating unit, the operating unit include pin, and the pin of the two neighboring operating unit is connected by Cutting Road connection strap
It connects；
Semiconductor chip is pasted and is conductively connected；The semiconductor chip is fixed on to the front of the metal substrate, it will
The pin is electrically connected with the semiconductor chip；
Plastic packaging；Plastic packaging layer is formed in the front of the metal substrate, the plastic packaging layer coats the semiconductor chip comprehensively
And the front of the metal substrate；
Hemisect；The Cutting Road connection strap is cut in the reverse side of the metal substrate, forms groove, the adjacent operation
Unit is after completing the hemisect still in conductive interconnection state；The Cutting Road connection strap produces in the half-cut process
Raw metal burr, the metal burr are attached on the wall of the groove；
Remove the metal burr；
The first protective layer is formed in the reverse side of the metal substrate；
Full cutting；Correspond to the groove in the reverse side of the metal substrate to be cut entirely, to make adjacent described
Operating unit is separated from each other, and obtains semiconductor packages unit.
As a preferred embodiment, the thickness of the Cutting Road connection strap cut when the full cutting is less than described
The thickness of the Cutting Road connection strap cut when hemisect.
As a preferred embodiment, the depth of the hemisect is less than described cut in the hemisect step
Cut the thickness of connection strap.
As a preferred embodiment, multiple operating units are arranged in multiple rows of multiple row, the adjacent two column behaviour
Make to be connected between unit by the first Cutting Road connection strap, the second Cutting Road is formed between operating unit described in adjacent rows
Connection strap；
Each operating unit includes: the multiple pins being connected with the first Cutting Road connection strap, the pin
Equipped with pin connection strap, the pin connection strap is connected with the second Cutting Road connection strap；
Wherein, the two neighboring second Cutting Road connection strap is conductively connected item by Cutting Road and is connected；
Correspondingly, only cutting the first Cutting Road connection strap in the hemisect step, depth of cut is greater than institute
It states the thickness of the first Cutting Road connection strap but is less than the sum of the thickness of the first Cutting Road connection strap and the plastic packaging layer.
As a preferred embodiment, in the full cutting step, described in the reverse side edge of the metal substrate
The direction of first Cutting Road connection strap cuts through the plastic packaging layer, cuts through second Cutting Road in the reverse side of the metal substrate and connects
Narrow bars and the plastic packaging layer.
As a preferred embodiment, the recess width of formation is greater than described in the hemisect step
The width of Cutting Road connection strap but the sum of the width for being less than the two neighboring pin.
As a preferred embodiment, full cutting openings width is less than or equal to institute in the full cutting step
State the recess width of hemisect formation.
As a preferred embodiment, before hemisect step after the plastic packaging step, in the Metal Substrate
The reverse side of plate forms the second protective layer；
In the step of removing the metal burr, the metal burr passes through the side that chemically reacts with the first reagent
Formula is dissoluted, and first reagent is not chemically reacted with second protective layer.
As a preferred embodiment, formed after removing the metal burr step first protective layer it
Before, remove second protective layer.
As a preferred embodiment, second protective layer is logical in the step of removing second protective layer
It crosses the mode chemically reacted with the second reagent to be dissoluted, the second reagent not metal layer with the metal substrate reverse side
It chemically reacts.
The utility model has the advantages that
Method for packaging semiconductor provided by the application embodiment is effectively gone by the step of removing metal burr
Except metal fragment or the wire residual formed in hemisect step, to eliminate the semiconductor packages unit phase therefore caused
Short circuit problem caused by the bridge joint formed between adjacent pin while guaranteeing semiconductor packages element solder reliability, improves
Product quality promotes yields, realizes mass production.
Referring to following description and accompanying drawings, only certain exemplary embodiments of this invention is disclosed in detail, specifies original of the invention
Reason can be in a manner of adopted.It should be understood that embodiments of the present invention are not so limited in range.In appended power
In the range of the spirit and terms that benefit requires, embodiments of the present invention include many changes, modifications and are equal.
The feature for describing and/or showing for a kind of embodiment can be in a manner of same or similar one or more
It uses in a other embodiment, is combined with the feature in other embodiment, or the feature in substitution other embodiment.
It should be emphasized that term "comprises/comprising" refers to the presence of feature, one integral piece, step or component when using herein, but simultaneously
It is not excluded for the presence or additional of one or more other features, one integral piece, step or component.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those skilled in the art without any creative labor, can be with root
Other attached drawings are obtained according to these attached drawings.
Figure 1A is the planar structure schematic diagram of the leadframe strip of the prior art；
Figure 1B is schematic cross-sectional view of the leadframe strip in Figure 1A along the direction A-A '；
Fig. 1 C is the leadframe strip in Figure 1B and the structural schematic diagram after semiconductor chip stickup and wire bonding；
Fig. 1 D is that leadframe strip shown in Fig. 1 C executes the structural schematic diagram after plastic packaging；
Fig. 1 E is that leadframe strip shown in Fig. 1 D implements the structural schematic diagram after hemisect；
Fig. 1 F is that leadframe strip shown in Fig. 1 E plates the structural schematic diagram after additional metal layer；
Fig. 1 G is that leadframe strip shown in Fig. 1 F implements the structural schematic diagram after cutting separation；
Fig. 1 H is the structural schematic diagram that leadframe strip implements the semiconductor packages unit obtained after cutting in Fig. 1 G；
Fig. 2 is a kind of flow chart for method for packaging semiconductor that the application embodiment provides；
Fig. 3 A is the schematic cross-sectional view for the metal substrate through-thickness that the application embodiment provides；
Fig. 3 B is that the metal substrate and semiconductor chip in Fig. 3 A paste the structural schematic diagram after simultaneously wire bonding；
Fig. 3 C is that the structure after another metal substrate is pasted with semiconductor chip and is conductively connected by metal salient point is shown
It is intended to；
Fig. 3 D is that metal substrate shown in Fig. 3 B executes the structural schematic diagram after plastic packaging；
Fig. 3 E is that metal substrate shown in Fig. 3 D forms the structural schematic diagram after the second protective layer；
Fig. 3 F is that metal substrate shown in Fig. 3 D or Fig. 3 E implements the structural schematic diagram after hemisect；
Fig. 3 G is that metal substrate shown in Fig. 3 F removes the structural schematic diagram after metal burr；
Fig. 3 H is that metal substrate shown in Fig. 3 G removes the structural schematic diagram after the second protective layer；
Fig. 3 I is that metal substrate shown in Fig. 3 H forms the structural schematic diagram after the first protective layer；
Fig. 3 J is that metal substrate shown in Fig. 3 I implements the structural schematic diagram after full cutting；
Fig. 3 K is the structural schematic diagram that metal substrate shown in Fig. 3 I implements the semiconductor packages unit obtained after full cutting；
Fig. 4 is the flow chart for another method for packaging semiconductor that the application embodiment provides；
Fig. 5 is the structural schematic diagram of metal substrate shown in Fig. 3 A；
Fig. 6 is the structural schematic diagram for another metal substrate that the application embodiment provides；
Fig. 6 A is the schematic cross-sectional view after metal substrate hemisect shown in fig. 6 along the direction C-C '；
Fig. 6 B is the structural schematic diagram that metal substrate shown in fig. 6 implements the semiconductor packages unit obtained after full cutting.
Description of symbols:
12, pin；14, connection strap；16, central pad area；18, gap；20, glue-line；22, semiconductor chip；24, draw
Line；26, plastic packaging material；28, additional metal layer；32, groove；101, positive；102, reverse side；103, central pad area；104, pin；
105, semiconductor chip；106, lead；107, plastic packaging layer；108, the second protective layer；109, groove；110, metal burr；111,
First protective layer；112, stairstepping；113, Cutting Road connection strap；203, central heat sink disk；206, salient point；301, the first cutting
Road connection strap；302, the second Cutting Road connection strap；303, pin connection strap；304, Cutting Road is conductively connected item.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, below in conjunction with of the invention real
The attached drawing in example is applied, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described implementation
Example is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
Technical staff's every other embodiment obtained without making creative work, all should belong to guarantor of the present invention
The range of shield.
It should be noted that it can directly on the other element when element is referred to as " being set to " another element
Or there may also be another elements placed in the middle.When an element is considered as " connection " another element, it be can be directly
It is connected to another element in succession or may be simultaneously present another element placed in the middle.Term as used herein " vertically ", " water
It is flat ", "left", "right" and similar statement for illustrative purposes only, be not meant to be the only embodiment.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein "and/or" includes one or more
Any and all combinations of relevant listed item.
Such as the prior art that Figure 1A to Fig. 1 H is presented, there are adjacent for finally obtained semiconductor package and its unit
It is easily bridged between pin 12, is due to easily forming a large amount of metal fragments or wire in half cutting process.And the pin provided
Architectural characteristic, semiconductor package product requirement and the electroplating technology of sheth itself require also to result in above-mentioned ask indirectly
Topic.It is specifically described as follows:
The needs that finally obtained semiconductor package is normally played for properties of product, it is desirable that semiconductor package
Included in the pin 12 of leadframes unit surrounding should be mutually isolated (electrical isolation, or, non-conductive connection), otherwise will appear
Short-circuit conditions.
As shown in Figure 1A, there are multiple (Figure 1A is illustrated as 4) pins 12 in each side of leadframes unit.This is in
After multiple pins 12 of same side undergo hemisect (as referring to figure 1E) and full cutting separation (as shown in Figure 1 G), final
Semiconductor package (as shown in Figure 1 G) and semiconductor packages unit (as shown in fig. 1H) in, it is necessary to be mutually isolated.
This requires in hemisect and in full the step of cutting, the width of cutting is greater than the width of connection strap 14.This
Sample, connection strap 14 are cut off and have not existed.To make 12 script of multiple pins on same side be in conductive communication state
Conductive connection medium-connection strap 14 lose, and then multiple pins 12 are mutually isolated no longer conductive communication.
However, forming the technique requirement of (as shown in fig. 1F) of additional metal layer 28 for plating, implementing hemisect
After technique, it is necessary to retain a part of connection strap 14, so that entire nead frame item is in conductive communication state.
The reason is that plating (Electroplating) is to plate other metal or alloy in metal surface using electrolysis principle
The process of thin layer is the technique for making the surface adhesion metal film of metal or other materials product using electrolysis.If making exposed
Metallic region all plate metal, then need to guarantee all metallic regions be connection.
Therefore, the requirement that can be realized for electroplating technology, when implementing hemisect, two neighboring leadframes unit is opposite
Multiple pins 12 on side, it is still necessary to which mutual conduction is realized by the connection strap 14 not cut.Otherwise, subsequent galvanizer
Skill will be unable to implement, and the side wall and roof at the back side and groove 32 of pin 12 and central pad area 16 also will be unable to be formed attached
Add metal layer 28.
However the step of just because of hemisect, it easily generates a large amount of metal fragments or wire is adhered in groove 32,
I.e. on the lateral wall of pin 12.So as to cause bridge joint is formed between finally obtained semiconductor packages unit adjacent leads, occur
Short circuit.
Therefore, embodiment of the present invention provides a kind of method for packaging semiconductor, can preferably solve above-mentioned existing skill
The defect of art.
It should be noted that indicating that " upper and lower " in orientation can be with the Metal Substrate in the description of the application embodiment
The front of plate, reverse side are corresponding, specifically, "upper" corresponds to the front of the metal substrate, "lower" corresponds to the metal substrate
" reverse side ".
Please refer to Fig. 2.Fig. 2 is a kind of flow chart of method for packaging semiconductor provided by embodiment of the present invention.Although
The present invention provides as the following examples or method operating procedure described in flow chart, but based on conventional or without creativeness
Labour, in the method may include more or less operating procedure.In addition, the method is not deposited in logicality
In the necessary causality the step of, it is suitable that the execution sequence of these steps is not limited to execution provided in the application embodiment
Sequence.
As shown in Fig. 2, providing a kind of method for packaging semiconductor in the application embodiment, may comprise steps of:
Step S10: a metal substrate is provided.
As shown in figs. 3 a and 5, Fig. 3 A is schematic cross-sectional view of the metal substrate in Fig. 5 along the direction B-B '.It is described
Metal substrate has opposite front 101 and reverse side 102, and the metal substrate includes multiple operating units, each operation
Unit corresponds to a semiconductor packages unit finally obtained described hereinafter.The operating unit includes pin 104, and adjacent two
The pin 104 of a operating unit is connected by Cutting Road connection strap 113, and Cutting Road connection strap 113 and pin 104 can be with
It is made of identical metal material.Specifically, each operating unit may include a central pad area 103, multiple pins 104
It is arranged in the surrounding of central pad area 103.
Metal substrate provided by the application embodiment can be as shown in Figure 5.Metal substrate includes multiple behaviour at this time
Make unit, each operating unit includes central pad area 103 and the multiple pins 104 for being arranged in central 103 surrounding of pad area, in
The centre of pad area 103 and pin 104 is entreated to be equipped with gap, design has Cutting Road connection strap 113 at two neighboring operating unit, with
Multiple operating units are made to be connected to each other.The metal substrate is consistent with leadframe strip structure shown in figure 1A.Central pad area
103, Cutting Road connection strap 113 and pin 104 can be made of identical metal material.
In the another embodiment of the application, the metal substrate provided can be as shown in Figure 6.Metal substrate at this time
Multiple operating units are arranged in multiple rows of multiple row, are formed with the first Cutting Road connection strap between the adjacent two column operating unit
301, the second Cutting Road connection strap 302 is formed between operating unit described in adjacent rows.Each operating unit include with
Multiple pins 104 that the first Cutting Road connection strap 301 is connected, the pin 104 is equipped with pin connection strap 303, described
Pin connection strap 303 is connected with the second Cutting Road connection strap 302.Wherein, the two neighboring second Cutting Road connection
Item 302 is conductively connected item 304 by Cutting Road and is connected.
Step S20: semiconductor chip is pasted and is conductively connected.
As shown in Figure 3B, semiconductor chip 105 is fixed on to the front 101 of the metal substrate, it can be using bonding
Mode is fixed.Jointing material can be epoxide resin polymer, and the fixation of semiconductor chip 105 is pasted on described after hot setting
The front 101 of metal substrate.
The pin 104 is electrically connected with the semiconductor chip 105, semiconductor chip 105 is equipped with several conductive elements
Part.According to the different type of chip, the conducting element may be miniature conductive weld pad either metallic conduction salient point 206.
It as shown in Figure 3B, can be by Wire Bonding Technology by the two of metal lead wire 106 if conducting element is conductive welding pad
End is bonded on conductive welding pad surface respectively on 104 surface of pin in metal substrate front 101, completes conductive interconnection.
It as shown in Figure 3 C, can be by face-down bonding technique by salient point if conducting element is metallic conduction salient point 206
206 direct upside-down mountings are on the pin 104 of metal substrate.Such metal substrate can be without central pad area 103, or has
Entreat heat dissipation plate 203.
When the application embodiment uses metal substrate as shown in Figure 5, the corresponding interconnection mode for selecting wire bonding.
Step S30: plastic packaging.
As shown in Figure 3D, it is formed with insulating materials (such as epoxide resin polymer) in the front 101 of the metal substrate
Plastic packaging layer 107, the plastic packaging layer 107 coat the semiconductor chip 105, metal lead wire 106 and the metal substrate comprehensively
Front 101, metal substrate reverse side 102 is exposed.
Step S50: hemisect.
As illustrated in Figure 3 F, the Cutting Road connection strap 113 is cut in the reverse side of metal substrate 102, forms groove 109.Phase
The adjacent operating unit is after completing the hemisect still in conductive interconnection state.
The Cutting Road connection strap 113 generates metal burr 110, the metal burr 110 in the half-cut process
It can be metal fragment or wire, the metal burr 110 is attached on the wall of the groove 109.Positioned at two pins 104
Between metal burr 110 can cause adjacent semiconductor encapsulation unit formed bridge joint, so as to cause short circuit, cause product failure,
Production yield is low.
When carrying out hemisect to metal substrate as shown in Figure 5, the depth of the hemisect connects less than the Cutting Road
The thickness of narrow bars 113, to guarantee the adjacent operating unit after completing the hemisect still in conductive interconnection state.
In Fig. 3 F, W1 indicates the width of groove 109, is greater than the width of the Cutting Road connection strap 113 but is less than adjacent
The sum of the width of two pins 104.
When carrying out hemisect to metal substrate as shown in FIG. 6, the first Cutting Road connection strap 301 is only cut.?
The reverse side of the metal substrate cuts the first Cutting Road connection strap 301, and the depth of the hemisect is greater than described first and cuts
It cuts the thickness of connection strap 301 but is less than the sum of the thickness of the first Cutting Road connection strap 301 and the plastic packaging layer 107, such as
Shown in Fig. 6 A.
It is conductively connected since the two neighboring second Cutting Road connection strap 302 is conductively connected item 304 by Cutting Road,
After the first Cutting Road connection strap 301 is cut through, the Cutting Road, which is conductively connected item 304, can be used as conductive connection medium,
The two neighboring second Cutting Road connection strap 302 is connected, and then realizes that the adjacent operating unit completes the hemisect
Afterwards still in conductive interconnection state.
Moreover, the depth of the hemisect guarantee the first Cutting Road connection strap 301 be cut through but the plastic packaging layer simultaneously
It is not cut through, to keep the pin side wall of the metal substrate completely exposed.In this way, when being subsequently formed the first protective layer, institute
The entire lateral wall for stating pin can be covered by first protective layer.
Fig. 6 A is the schematic cross-sectional view after the metal substrate hemisect in Fig. 6 along the direction C-C ', and W1 indicates groove 109
Width, be greater than the first Cutting Road connection strap 301 width but be less than the two neighboring pin 104 width it
With.
Step S60: removal metal burr.
As shown in Figure 3 G, the metal burr 110 on 109 surface of groove is removed, to avoid semiconductor packages unit
Bridge joint is formed between pin, to avoid the problem of short circuit.
The application embodiment without limitation, can such as use drum by the way of purging to the mode for removing metal burr
Blower blows or is cleared away with hairbrush.
As a kind of feasible embodiment, the metal burr 110 can be by chemically reacting with the first reagent
Mode and be dissoluted.Preferably, the first reagent can be sprayed using machine, makes first reagent and the metal burr
110 obtain preferably contact, concurrent biochemical reaction, thus the metal burr 110 being effectively removed in groove 109.
Metal burr is removed afterwards in hemisect (step S50), and metal substrate is not cut open all also at this time, and each operation is single
Member is still in connection status, convenient for efficiently removing metal burr 110.Metal burr is removed again with after full cutting (step S90)
110 compare, and efficiency significantly improves.This is because what is obtained after full cutting is separated semiconductor packages unit one by one,
And metal burr 110 can move into other surface, this will be unfavorable for efficiently removing metal burr 110.
Step S80: the first protective layer is formed.
As shown in fig. 31, the first protective layer 111 is formed on the metal layer of metal substrate reverse side 102, generallys use plating
Technique.By abovementioned steps, after hemisect, the adjacent operating unit is electroplating technology still in conductive interconnection state
Provide implementation condition.To in electroplating technology, make the lower surface of central pad area 103, the lower surface of pin 104 and
The first protective layer 111 can be formed on the exposed metal surface of groove 109.
First protective layer can be 100% pure tin, with a thickness of 10um-25um.
Step S90: full cutting.
As shown in figure 3j, correspond at the groove 109 in the reverse side 102 of the metal substrate and cut entirely, thus
It is separated from each other the adjacent operating unit, obtains semiconductor packages unit.
In the application embodiment, the thickness for the Cutting Road connection strap 113 that when full cutting cuts is less than described half
The thickness of the Cutting Road connection strap 113 cut when cutting.
Specifically, the depth of hemisect can be Cutting Road connection strap when carrying out hemisect to metal substrate shown in Fig. 5
The 70%-80% of 113 thickness, then the depth for cutting metal substrate entirely is the 20%-30% of 113 thickness of Cutting Road connection strap.Cause
This, generated metal burr when the metal burr that when hemisect generates is far more than full cutting.
When carrying out hemisect to metal substrate shown in Fig. 6, it will generate the first Cutting Road connection strap of metal burr 110
301 all cut through.The the first Cutting Road connection strap 301 cut when full cutting with a thickness of 0, cutting is plastic packaging layer 107.Cause
This, will not generate metal burr when cutting entirely.
To which the metal burr that full cutting generates is very small, is not enough to influence the quality of encapsulating products, therefore negligible
Disregard.So the application after hemisect step, i.e., is removed metal burr 110, without the ability after full cutting step
Metal burr is removed.
If not removing metal burr 110 after hemisect step, the first protective layer 111 is directly electroplated, will lead to and generated
A large amount of metal burrs 109 surface of groove is fixed on by first protective layer 111, adjacent semiconductor encapsulation still can be caused single
Member forms bridge joint, so as to cause short circuit.
When being cut entirely to metal substrate as shown in Figure 5, need to cut off the remainder of the Cutting Road connection strap 113
Part and the plastic packaging layer 107.
As shown in figure 3j, W2 indicates the opening width cut entirely.The opening width W2 cut entirely is less than the opening of hemisect
Width, i.e. W2 are less than the width W1 of groove.
In this way, obtaining the semiconductor packages unit as shown in Fig. 3 K after full cutting, ladder is formed in 104 side edge of pin
Shape 112 is also formed with the first protective layer 111 on the stairstepping 112, helps to improve the electrical connection of semiconductor packages unit
Performance.
When being cut entirely to metal substrate as shown in FIG. 6, the metal substrate reverse side 102 along described first
The direction of Cutting Road connection strap 301 cuts through the plastic packaging layer 107, cuts through described second in the reverse side 102 of the metal substrate and cuts
Cut connection strap 302 and the plastic packaging layer 107.
Preferably, full cutting openings width is equal to the recess width that the hemisect is formed.In this way, pin can be obtained
The more smooth semiconductor packages unit of 104 lateral walls.The semiconductor packages unit is as shown in Figure 6B.
Method for packaging semiconductor provided by the application embodiment is effectively gone by the step of removing metal burr
Except metal fragment or the wire residual formed in cutting step, so that it is adjacent to eliminate the semiconductor packages unit therefore caused
It is short-circuit caused by the bridge joint formed between pin, while guaranteeing semiconductor packages element solder reliability, improve product matter
Amount promotes yields, realizes mass production.
In the application embodiment, as shown in figure 4, after the plastic packaging step (step S30), hemisect step
Before (step S50), it can also include the following steps:
Step S40: the second protective layer is formed.
As shown in FIGURE 3 E, the second protective layer 108 is formed on the metal layer of metal substrate reverse side 102, generallys use plating
Technique.The metallic region (central pad area 103 and pin 104) of entire metal substrate conductive communication each other, is galvanizer
Skill provides implementation condition.To which in electroplating technology, the lower surface of the lower surface and pin 104 that make central pad area 103 is equal
The second protective layer 108 can be formed.
In view of in subsequent step S60, when removing metal burr, due to the material and pin 104 of metal burr 110
Material is the same, removes metal burr 110, the lower surface of central pad area 103 and the lower surface of pin 104 according to the first reagent
Also it can react and be dissoluted with the first reagent.
Therefore, by forming second protective layer 108, Ke Yibao on the metal layer of metal substrate reverse side 102 in advance
The central lower surface of pad area 103 and the lower surface of pin 104 are protected, metal substrate lower surface and the first reagent are completely cut off, to keep away
It reacts and is destroyed with the first reagent in the lower surface of the lower surface and pin 104 of exempting from central pad area 103.
In the application embodiment, the first reagent can choose organic acid, concretely citric acid.First reagent
Can be by metal burr 110 described in chemical reaction corrosion, but with second protective layer 108 chemistry does not occur for first reagent
Reaction.
Specifically, second protective layer can be 100% pure tin, with a thickness of 10um-25um.
It is corresponding, as shown in figure 4, after removing the metal burr step (step S60), forming first protection
Before layer (step S80), it can also include the following steps:
Step S70: the second protective layer of removal.
Hemisect step (step S50), hemisect shape have been carried out due to being formed after the second protective layer (step S40)
At the surface of groove 109 fail to form protective layer.
It is formed since protective layer generallys use electroplating technology, for the needs of electroplating technology, removes the second protective layer 108
(as shown in figure 3h), so that entirely conduction connects the metallic region (central pad area 103 and pin 104) of metal substrate each other
It is logical, condition is provided to be subsequently formed the first protective layer (step S80).
Specifically, second protective layer 108 is dissoluted by way of chemically reacting with the second reagent, described
Metal layer of two reagents not with the metal substrate reverse side 102 chemically reacts.
In the application embodiment, the second reagent can choose inorganic acid, concretely nitric acid.Preferably, it can adopt
The second reagent is sprayed with machine, second reagent is obtained with second protective layer 108 and preferably contacts, it is concurrent biochemical
Reaction, to be effectively removed the second protective layer 108.
It should be noted that term " first ", " second " etc. are used for description purposes only and distinguish in the description of the present application
Similar object between the two and is not present sequencing, can not be interpreted as indication or suggestion relative importance.In addition,
In the description of the present application, unless otherwise indicated, the meaning of " plurality " is two or more.
Herein cited any digital value all include between lower limit value to upper limit value with the lower value of an incremented and
The all values of upper value, there are the intervals of at least two units between any lower value and any much higher value.For example, such as
Fruit elaborates that the quantity an of component or the value of process variable (such as temperature, pressure, time etc.) are from 1 to 90, preferably from 20
To 80, more preferably from 30 to 70, then purpose is arrived in order to illustrate also clearly listing such as 15 to 85,22 in the specification
68,43 to 51,30 to 32 is equivalent.For the value less than 1, suitably think that a unit is 0.0001,0.001,0.01,0.1.
These are only intended to the example clearly expressed, it is believed that all possibility for the numerical value enumerated between minimum and peak
Combination is all expressly set forth in the specification in a similar manner.
Unless otherwise indicated, all ranges all include all numbers between endpoint and endpoint.It is used together with range
" about " or " approximation " be suitable for two endpoints of the range.Thus, " about 20 to 30 " are intended to cover that " about 20 to about
30 ", including at least the endpoint indicated.
All articles and reference disclosed, including patent application and publication, for various purposes by quoting knot
Together in this.Describing combined term " substantially by ... constitute " should include identified element, ingredient, component or step and reality
Other elements, ingredient, component or the step of the basic novel feature of the combination are not influenced in matter.Using term "comprising" or
" comprising " describes the combination of element here, ingredient, component or step it is also contemplated that substantially by these elements, ingredient, component
Or the embodiment that step is constituted.Here by using term " can with ", it is intended to illustrate that " can with " includes described any
Attribute is all optional.
Multiple element, ingredient, component or step can be provided by single integrated component, ingredient, component or step.Optionally
Ground, single integrated component, ingredient, component or step can be divided into multiple element, ingredient, component or the step of separation.It is used to
The open "a" or "an" for describing element, ingredient, component or step is not said to exclude other elements, ingredient, component
Or step.
It should be understood that above description is to illustrate rather than to be limited.By reading above-mentioned retouch
It states, many embodiments and many applications except provided example all will be aobvious and easy for a person skilled in the art
See.Therefore, the range of this introduction should not be determined referring to foregoing description, but should referring to appended claims and this
The full scope of the equivalent that a little claims are possessed determines.For comprehensive purpose, all articles and with reference to including special
The disclosure of benefit application and bulletin is all by reference to being incorporated herein.Theme disclosed herein is omitted in preceding claims
Any aspect is not intended to abandon the body matter, also should not be considered as inventor the theme is not thought of as it is disclosed
A part of subject matter.
Claims (10)
1. a kind of method for packaging semiconductor, which comprises the following steps:
One metal substrate is provided；The metal substrate has opposite obverse and reverse, and the metal substrate includes multiple operations
Unit, the operating unit include pin, and the pin of the two neighboring operating unit is connected by Cutting Road connection strap；
Semiconductor chip is pasted and is conductively connected；The semiconductor chip is fixed on to the front of the metal substrate, it will be described
Pin is electrically connected with the semiconductor chip；
Plastic packaging；Plastic packaging layer is formed in the front of the metal substrate, the plastic packaging layer coats the semiconductor chip and institute comprehensively
State the front of metal substrate；
Hemisect；The Cutting Road connection strap is cut in the reverse side of the metal substrate, forms groove, the adjacent operating unit
Still in conductive interconnection state after completing the hemisect；The Cutting Road connection strap generates gold in the half-cut process
Belong to burr, the metal burr is attached on the wall of the groove；
Remove the metal burr；
The first protective layer is formed in the reverse side of the metal substrate；
Full cutting；Correspond to the groove in the reverse side of the metal substrate to be cut entirely, to make the adjacent operation
Unit is separated from each other, and obtains semiconductor packages unit.
2. method for packaging semiconductor according to claim 1, which is characterized in that the Cutting Road cut when the full cutting
The thickness of connection strap is less than the thickness of the Cutting Road connection strap cut when the hemisect.
3. method for packaging semiconductor according to claim 1, which is characterized in that in the hemisect step, described half
The depth of cutting is less than the thickness of the Cutting Road connection strap.
4. method for packaging semiconductor according to claim 1, which is characterized in that multiple operating units are in multiple rows of multiple row
It arranges, is connected between the adjacent two column operating unit by the first Cutting Road connection strap, operating unit described in adjacent rows
Between be formed with the second Cutting Road connection strap；
Each operating unit includes: the multiple pins being connected with the first Cutting Road connection strap, and the pin is equipped with
Pin connection strap, the pin connection strap are connected with the second Cutting Road connection strap；
Wherein, the two neighboring second Cutting Road connection strap is conductively connected item by Cutting Road and is connected；
Correspondingly, in the hemisect step, the first Cutting Road connection strap is only cut, depth of cut is greater than described the
The thickness of one Cutting Road connection strap but the sum of the thickness for being less than the first Cutting Road connection strap and the plastic packaging layer.
5. method for packaging semiconductor according to claim 4, which is characterized in that in the full cutting step, described
The reverse side of metal substrate cuts through the plastic packaging layer along the direction of the first Cutting Road connection strap, in the reverse side of the metal substrate
Cut through the second Cutting Road connection strap and the plastic packaging layer.
6. method for packaging semiconductor according to claim 1, which is characterized in that in the hemisect step, formation
The recess width is greater than the width of the Cutting Road connection strap but is less than the sum of the width of the two neighboring pin.
7. method for packaging semiconductor according to claim 1, which is characterized in that complete to cut in the full cutting step
Opening width is less than or equal to the recess width that the hemisect is formed.
8. method for packaging semiconductor according to claim 1, which is characterized in that
Before hemisect step after the plastic packaging step, the second protective layer is formed in the reverse side of the metal substrate；
In the step of removing the metal burr, metal burr quilt by way of being chemically reacted with the first reagent
Corrosion, first reagent are not chemically reacted with second protective layer.
9. method for packaging semiconductor according to claim 8, which is characterized in that after removing the metal burr step
It is formed before first protective layer, removes second protective layer.
10. method for packaging semiconductor according to claim 9, which is characterized in that in the step for removing second protective layer
In rapid, second protective layer is dissoluted by way of chemically reacting with the second reagent, second reagent not with institute
The metal layer for stating metal substrate reverse side chemically reacts.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910179715.0A CN109950159A (en) | 2019-03-11 | 2019-03-11 | A kind of method for packaging semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910179715.0A CN109950159A (en) | 2019-03-11 | 2019-03-11 | A kind of method for packaging semiconductor |
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| CN109950159A true CN109950159A (en) | 2019-06-28 |
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| CN201910179715.0A Pending CN109950159A (en) | 2019-03-11 | 2019-03-11 | A kind of method for packaging semiconductor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114783888A (en) * | 2022-06-16 | 2022-07-22 | 合肥矽迈微电子科技有限公司 | Exposed welding leg of chip packaging body and processing method thereof |
| CN115430909A (en) * | 2022-11-10 | 2022-12-06 | 杭州沈氏节能科技股份有限公司 | Laser cutting tool for fins and manufacturing method of laser cutting tool for fins |
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| CN205303418U (en) * | 2015-12-25 | 2016-06-08 | 华天科技（西安）有限公司 | Adoption etches partially technology and forms cascaded frame pin |
| CN107112245A (en) * | 2014-11-20 | 2017-08-29 | 密克罗奇普技术公司 | QFN encapsulation with improved contact pin |
| CN109346454A (en) * | 2018-11-08 | 2019-02-15 | 嘉盛半导体(苏州)有限公司 | Leadframe strip, method for packaging semiconductor, semiconductor package and its unit |
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| CN107112245A (en) * | 2014-11-20 | 2017-08-29 | 密克罗奇普技术公司 | QFN encapsulation with improved contact pin |
| CN205303418U (en) * | 2015-12-25 | 2016-06-08 | 华天科技（西安）有限公司 | Adoption etches partially technology and forms cascaded frame pin |
| CN109346454A (en) * | 2018-11-08 | 2019-02-15 | 嘉盛半导体(苏州)有限公司 | Leadframe strip, method for packaging semiconductor, semiconductor package and its unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114783888A (en) * | 2022-06-16 | 2022-07-22 | 合肥矽迈微电子科技有限公司 | Exposed welding leg of chip packaging body and processing method thereof |
| CN114783888B (en) * | 2022-06-16 | 2022-09-06 | 合肥矽迈微电子科技有限公司 | Chip package external exposure welding leg and processing method thereof |
| CN115430909A (en) * | 2022-11-10 | 2022-12-06 | 杭州沈氏节能科技股份有限公司 | Laser cutting tool for fins and manufacturing method of laser cutting tool for fins |
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