CN108807352B - Novel L ED filament manufacturing method - Google Patents

Novel L ED filament manufacturing method Download PDF

Info

Publication number
CN108807352B
CN108807352B CN201710333795.1A CN201710333795A CN108807352B CN 108807352 B CN108807352 B CN 108807352B CN 201710333795 A CN201710333795 A CN 201710333795A CN 108807352 B CN108807352 B CN 108807352B
Authority
CN
China
Prior art keywords
substrate
chip
electrode
coated
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710333795.1A
Other languages
Chinese (zh)
Other versions
CN108807352A (en
Inventor
申凤仪
王秀瑜
申广
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Rewo Micro Semiconductor Technology Co ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201710333795.1A priority Critical patent/CN108807352B/en
Publication of CN108807352A publication Critical patent/CN108807352A/en
Application granted granted Critical
Publication of CN108807352B publication Critical patent/CN108807352B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Led Device Packages (AREA)

Abstract

The invention provides a novel L ED filament manufacturing technology, in particular to a technology of combining a pre-processed special substrate with a solder paste printing technology, wherein the surface of a L ED chip contacted with the substrate is firstly coated with insulating glue, then a through hole is punched at the position of a P/N electrode of the chip corresponding to the substrate by laser, the electrode surface of the chip faces the surface of the substrate coated with the insulating glue, the electrode of the chip is placed corresponding to the through hole, the solder paste is printed on the electrode surface of the chip by the through hole on the substrate in a printing-missing way, the electrode of the chip is conducted with the substrate by heating and welding, and finally the metal of the middle insulating river channel part of the P/N electrode of the chip corresponding to the substrate is corroded by chemical corrosion or laser cutting, so that the electrode surface of the chip and the substrate form a solder paste welding path, the production efficiency is greatly improved while the.

Description

Novel L ED filament manufacturing method
Technical Field
The invention relates to a novel L ED filament manufacturing technology, in particular to a technology for manufacturing a L ED filament with high efficiency and low cost by adopting a combination of a special pretreated substrate and a solder paste omission printing technology, wherein a through hole is formed in a P/N electrode position of a chip corresponding to a substrate by adopting laser, an electrode surface of the chip faces to a substrate surface coated with insulating glue, and the through hole corresponding to the chip electrode is arranged.
Background
L ED filament has been developed rapidly in recent years, and the market capacity has been increased at a high rate, at present, the main manufacturing technologies of L ED filament are divided into two major categories, one category is the technologies of L ED normal chip matched substrate (glass, sapphire substrate, ceramic substrate, metal substrate) die bonding, routing and mould pressing sealing, and the other category is the technologies of inverted L ED chip matched substrate (PCB, FPC, ceramic substrate of printed circuit, glass substrate, etc.) die bonding, solder paste reflow soldering and mould pressing sealing.
The filament technology that adopts the chip of just installing preparation is the mainstream technology of current L ED filament trade, because L ED solid brilliant machine, bonding wire machine's price are more expensive, cause equipment depreciation cost higher, just install the chip and adopt the sapphire face of L ED chip to paste the combination base plate, because the low coefficient of heat conductivity of the sapphire substrate of L ED chip, cause chip heat dispersion relatively poor.
Flip chip preparation L ED filament, use PCB, FPC, printed circuit's ceramic substrate, glass substrate etc. as the base plate, the interconnecting link that the printing needs on the base plate and the welding point of welding dress flip L ED chip, and etch, paste flip L ED chip on the base plate of the good circuit of etching, cross the reflow soldering solidification, the mould pressing is sealed glues, the coating phosphor powder, then heat the solidification, the advantage can save wire bonder equipment investment, simultaneously because the P/N electrode face of L ED chip switches on through tin cream welding and base plate circuit connection, the chip heat dissipation is better, the shortcoming is that flip chip price is higher than just adorning more than 15%, in addition to the chip below 10 x 30mil because the chip size is too little, when carrying out the tin cream welding, cause the welding short circuit between chip P/N electrode easily.
Disclosure of Invention
The invention provides a manufacturing method of L ED filament, in particular to a method for combining a pre-processed special substrate with a solder paste printing technology, wherein the substrate is contacted with a L ED chip surface and is firstly coated with insulating glue, then the substrate is drilled with through holes corresponding to P/N electrodes of a chip by laser, the electrode surface of the chip is arranged at a corresponding position, the solder paste is printed on the electrode surface of the chip by the through holes on the substrate in a printing-leaking way, the through holes of the substrate are completely filled with the solder paste, the electrode of the chip is heated and welded to be conducted with the substrate, and finally the metal of the insulating river channel part in the middle of the P/N electrode of the chip corresponding to the substrate is corroded by chemical corrosion or laser cutting, which comprises the following:
step one, substrate pretreatment: taking a metal substrate as a substrate for filament packaging, wherein the metal substrate is conductive metal or conductive material, further, the metal substrate is any one of copper, aluminum, iron, tin and lead, the thickness of the substrate is 10-1000 microns, one surface of the substrate is coated with an insulating transparent adhesive with the thickness of 1-1000 microns, and the insulating transparent adhesive can be any one of PTFE (polytetrafluoroethylene), epoxy solid crystal adhesive and transparent silica gel;
step two, laser drilling: performing laser drilling on the pretreated substrate by using a laser drilling machine according to the corresponding positions of a chip electrode (P pole) and a chip electrode (N pole) to form a through hole, wherein the aperture range is 10-200 microns, and laser is injected from one side of the substrate coated with the insulating transparent adhesive;
step three, chip die bonding: the electrode surface of the chip is corresponding to one surface of the substrate coated with the insulating transparent adhesive, two through holes are respectively aligned according to two electrodes of the chip, the chip is placed on the whole substrate at a corresponding position, and after the chip is placed, the surface of the substrate coated with the insulating transparent adhesive is horizontally placed on a flat workbench downwards and fixed;
step four, solder paste missing printing: carrying out screen printing on the solder paste on the surface of the substrate, which is not coated with the insulating transparent adhesive, by using a scraper, and carrying out screen printing on the corresponding electrode of the chip on the surface of the substrate, which is coated with the insulating transparent adhesive, through the through hole on the substrate;
step five, electrode welding: after the missing printing is finished, covering an electric heating plate on one side of the substrate, which is not coated with the insulating transparent adhesive, and electrifying and heating to 230 ℃ plus or minus 5 ℃, or putting the substrate subjected to the missing printing into an electric heating box and heating to 230 ℃ plus or minus 5 ℃;
step six, manufacturing the insulating tape: coating a substrate corrosion protection layer on two sides of a substrate welded by electrodes, wherein the substrate corrosion protection layer is 1-1000 microns of epoxy solid crystal glue, PTFE glue or silica gel or other insulating transparent resin, drying and curing, cutting the substrate corrosion protection layer by adopting laser cutting or mechanical knife cutting along the through holes on the side of the substrate where no chip is arranged and corresponding to the central position of an insulating river channel between chip electrodes, the width of a cutting path is 30-50 microns, placing the substrate into an acid tank, and corroding and penetrating a substrate metal layer of the cutting path by using sulfuric acid, nitric acid or other corrosive solutions to thoroughly form a P pole of a chip electrode and an N pole of the chip electrode to form an insulating fracture path;
step seven, cleaning: cleaning and drying the part which is finished with the step six;
step eight: and coating silica gel or epoxy glue and fluorescent glue on the parts subjected to the step seven, fixing the glue, and cutting and separating the light bars.
The invention has the beneficial effects that: the method adopts the normal chip which is universal in the market, saves the equipment investment of a wire bonder, adopts the common metal substrate to reduce the material cost, and effectively avoids the short circuit problem of the P/N electrodes of the chip during the solder paste welding because the bonding surface of the chip and the substrate is coated with the transparent adhesive tape and the physical barrier is formed between the P/N electrodes of the chip. The chip electrode surface and the substrate form a solder paste welding path, the heat conduction and heat dissipation performance of the chip is improved, and finally, as the insulating river channel in the middle of the P/N electrode of the chip is corroded, the chip electrode surface is not blocked by the light-tight substrate, so that the chip can emit light all around, when the product performance is improved, the production efficiency is greatly improved, and the production cost is greatly reduced.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of a filament structure of the mainstream of the existing market;
FIG. 3 is a rear view of the filament after cutting and separation;
FIG. 4 is a top view of the filament after cutting and separation;
FIG. 5 is a schematic diagram of a circuit structure for etching a substrate;
wherein: 1. the chip electrode comprises a chip electrode P2, a chip electrode insulation riverway 3, a chip sapphire substrate 4, transparent insulation glue 5, a chip electrode N6, substrates 7 and 8, a through hole 9, a die attach glue 10, a gold thread 11, a substrate corrosion protection layer 12 and a substrate insulation fracture path.
Detailed Description
The invention provides a manufacturing method of L ED filament, in particular to a method for manufacturing a pretreated special substrate combined with a missing printing solder paste technology, wherein the substrate is contacted with a L ED chip surface, an insulating adhesive is coated on the substrate surface, then the substrate is punched with a through hole corresponding to a P/N electrode of a chip by laser, the chip electrode surface is arranged at a corresponding position, the solder paste is missed printed on the chip electrode surface by using the missing printing method through the through hole on the substrate, meanwhile, the solder paste completely fills the through hole of the substrate, the chip electrode is heated and welded to be conducted with the substrate, and finally, the metal of the middle insulating river channel part of the chip P/N electrode corresponding to the substrate is corroded by chemical corrosion or laser cutting.
The following figures and examples illustrate the invention in detail.
The drawings and detailed description or examples are exemplary only, and are not intended to limit the invention.
Example 1:
an L ED chip type was selected, which was a blue chip with a chip size of 8 x 15mil, and the product structure is shown in FIG. 1.
Step one, substrate pretreatment: taking a metal substrate (6) (an iron plate, the thickness of the substrate is 100-150 microns) as a substrate for filament packaging, wherein the thickness of the substrate is 200 +/-50 microns, and one surface of the substrate is coated with an insulating transparent adhesive (4) (epoxy die bonding adhesive) with the thickness of 50-100 microns;
step two, laser drilling: performing laser drilling on the pretreated substrate by using a laser drilling machine according to the corresponding positions of a chip electrode P pole (1) and a chip electrode N pole) (5) to form through holes (7) and (8), wherein the aperture range is micrometer, laser is injected from the side of the substrate coated with the insulating transparent adhesive, and the finished part in the second step is shown in figure 3;
step three, chip die bonding: the electrode surface of the chip is coated with an insulating transparent adhesive (4) corresponding to the substrate, two through holes (7) and (8) are respectively aligned according to two electrodes of the chip, the chip is placed on the whole substrate at a corresponding position, and after the chip is placed, the substrate is horizontally placed on a flat workbench and fixed with the insulating transparent adhesive coated side facing downwards;
step four, solder paste missing printing: using a scraper to perform screen printing on the side of the substrate, which is not coated with the insulating transparent adhesive, and screen printing the solder paste on the corresponding electrodes of the chip coated with the insulating transparent adhesive through the through holes (7) and (8) on the substrate;
step five, electrode welding: after the missing printing is finished, covering an electric heating plate on one side of the substrate which is not coated with the insulating transparent adhesive, electrifying and heating to 230 ℃ plus or minus 5 ℃, preserving heat for 3 minutes (or putting the substrate which is finished with the missing printing into an electric heating box and heating to 230 ℃ plus or minus 5 ℃), and then naturally cooling to room temperature;
step six, manufacturing the insulating tape: coating a substrate corrosion protection layer (11) (100 +/-50 microns of epoxy die-bonding adhesive) on two surfaces of a substrate subjected to electrode welding, drying and curing, cutting the substrate corrosion protection layer (exposing substrate metal) by adopting laser cutting or mechanical knife cutting along the through holes (7) and (8) on the surface of the substrate without chips as shown in figure 5 and corresponding to the central position of an insulating river channel (2) between chip electrodes, wherein the width of a scribing channel is 50 +/-20 microns, placing the substrate into an acid tank, and corroding and penetrating the substrate metal layer of the scribing channel by using sulfuric acid, nitric acid or other corrosive solutions to completely form a sheet electrode P pole (1) and a chip electrode N pole (5) insulating fracture channel (12);
step seven, cleaning: cleaning and drying the parts which are finished in the step six, wherein the parts which are finished in the step seven are shown in figure 4;
step eight: and coating silica gel or epoxy glue and fluorescent glue on the parts subjected to the step seven, fixing the glue, and cutting and separating the light bars.

Claims (3)

1. The L ED filament manufacturing method adopts a pretreated substrate and a solder paste printing technology, adopts laser to punch through holes at P/N electrode positions of a substrate corresponding to a chip, and places electrode surfaces of the chip towards the substrate surface coated with insulating glue at corresponding through hole positions, and comprises the following steps:
step one, substrate pretreatment: taking a metal substrate as a substrate for filament packaging, wherein the metal substrate is conductive metal or conductive material, the thickness of the substrate is 10-1000 microns, and one surface of the substrate is coated with insulating transparent adhesive with the thickness of 1-1000 microns;
step two, laser drilling: performing laser drilling on the pretreated substrate by using a laser drilling machine according to the corresponding positions of a chip electrode P pole and a chip electrode N pole, wherein the aperture range of two through holes formed by the laser drilling is 10-200 microns, and laser is injected from one side of the substrate coated with the insulating transparent adhesive;
step three, chip die bonding: the electrode surface of the chip is corresponding to one surface of the substrate coated with the insulating transparent adhesive, two through holes are respectively aligned according to two electrodes of the chip, the chip is placed on the whole substrate at a corresponding position, and after the chip is placed, the surface of the substrate coated with the insulating transparent adhesive is horizontally placed on a flat workbench downwards and fixed;
step four, solder paste missing printing: carrying out screen printing on the solder paste on the surface of the substrate, which is not coated with the insulating transparent adhesive, by using a scraper, and carrying out screen printing on the corresponding electrode of the chip on the surface of the substrate, which is coated with the insulating transparent adhesive, through the through hole on the substrate;
step five, electrode welding: after the missing printing is finished, covering an electric heating plate on one side of the substrate, which is not coated with the insulating transparent adhesive, and electrifying and heating to 230 ℃ plus or minus 5 ℃, or putting the substrate subjected to the missing printing into an electric heating box and heating to 230 ℃ plus or minus 5 ℃;
step six, manufacturing the insulating tape: coating a substrate corrosion protection layer on two sides of a substrate welded by electrodes, wherein the substrate corrosion protection layer is 1-1000 microns and is made of any one of epoxy solid crystal glue, PTFE glue or silica gel, drying and curing, cutting the substrate corrosion protection layer on the side, where no chip is arranged, of the substrate along the position between two through holes and corresponding to the central position of an insulating river channel between chip electrodes by adopting laser cutting or mechanical knife cutting, the width of a scribing channel is 30-50 microns, placing the substrate into an acid tank, and corroding and penetrating a substrate metal layer of the scribing channel by using sulfuric acid, nitric acid or other corrosive solutions to thoroughly form an insulating fracture channel between a chip electrode P pole and a chip electrode N pole;
step seven, cleaning: cleaning and drying the part which is finished with the step six;
step eight: and coating silica gel or epoxy glue and fluorescent glue on the parts subjected to the step seven, fixing the glue, and cutting and separating the light bars.
2. The method as claimed in claim 1, wherein the metal substrate in the first step is selected from copper, aluminum, iron, tin and lead.
3. The method for manufacturing the L ED filament according to claim 1, wherein the insulating transparent adhesive in the first step is any one of PTFE, epoxy solid crystal adhesive and transparent silica gel.
CN201710333795.1A 2017-05-03 2017-05-03 Novel L ED filament manufacturing method Active CN108807352B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710333795.1A CN108807352B (en) 2017-05-03 2017-05-03 Novel L ED filament manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710333795.1A CN108807352B (en) 2017-05-03 2017-05-03 Novel L ED filament manufacturing method

Publications (2)

Publication Number Publication Date
CN108807352A CN108807352A (en) 2018-11-13
CN108807352B true CN108807352B (en) 2020-07-14

Family

ID=64094485

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710333795.1A Active CN108807352B (en) 2017-05-03 2017-05-03 Novel L ED filament manufacturing method

Country Status (1)

Country Link
CN (1) CN108807352B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109817769B (en) * 2019-01-15 2020-10-30 申广 Novel LED chip packaging manufacturing method
CN109817796B (en) * 2019-01-24 2021-07-23 南通沃特光电科技有限公司 LED packaging structure with double fluorescent layers and packaging method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222667A (en) * 2011-07-14 2011-10-19 东莞市邦臣光电有限公司 LED (light-emitting diode) light source module and packaging process thereof
CN103828076A (en) * 2011-08-01 2014-05-28 株式会社Ｓｔｅｑ Semiconductor device and fabrication method for same
CN204011418U (en) * 2014-07-25 2014-12-10 胡溢文 A kind of LED filament that is provided with formal dress inversion chip
CN104900535A (en) * 2015-04-07 2015-09-09 北京理工大学 Solder filling process for ceramic film conductive vias under the background of terahertz flip-chip bonding

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201631808A (en) * 2015-02-25 2016-09-01 隆達電子股份有限公司 LED chip package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102222667A (en) * 2011-07-14 2011-10-19 东莞市邦臣光电有限公司 LED (light-emitting diode) light source module and packaging process thereof
CN103828076A (en) * 2011-08-01 2014-05-28 株式会社Ｓｔｅｑ Semiconductor device and fabrication method for same
CN204011418U (en) * 2014-07-25 2014-12-10 胡溢文 A kind of LED filament that is provided with formal dress inversion chip
CN104900535A (en) * 2015-04-07 2015-09-09 北京理工大学 Solder filling process for ceramic film conductive vias under the background of terahertz flip-chip bonding

Also Published As

Publication number Publication date
CN108807352A (en) 2018-11-13

Similar Documents

Publication Publication Date Title
CN105185752B (en) Semiconductor devices and its manufacturing method
CN100380614C (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
CN102789994B (en) The wettable semiconductor device in side
US10600703B2 (en) Process for packaging circuit component having copper circuits with solid electrical and thermal conductivities and circuit component thereof
CN107275463A (en) A kind of New LED encapsulates manufacturing technology
CN108807352B (en) Novel L ED filament manufacturing method
US9653424B2 (en) Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
US8455303B2 (en) Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
CN112885804A (en) Surface-mounted photovoltaic bypass module and packaging process thereof
CN210958935U (en) Flexible circuit board for LED lamp strip
US20110068457A1 (en) Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
US9515047B2 (en) High performance package and process for making
CN104112673B (en) Chip package base plate and preparation method thereof
CN108110459B (en) High-power IPM module terminal connection structure
JP3096226B2 (en) Method for manufacturing semiconductor device
CN102034781B (en) Semiconductor package for printing bonding material on lead frame and wafer and manufacturing method thereof
WO2008138182A1 (en) Chip type light-emitting diode
CN109979825A (en) The circuit element production method of array batch potted element crystal grain
TWI583282B (en) High performance package and process for making
WO2014063637A1 (en) Cob led module and manufacturing method thereof
TWI517314B (en) Miniature packaging for discrete circuit components
CN203147565U (en) Large and medium-power LED (light-emitting diode) car lamp
CN215600389U (en) Light-emitting diode with non-thermoelectric separation structure
CN211152324U (en) Novel aluminum substrate
CN209693202U (en) A kind of flip-over type LED core chip package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20220829

Address after: 1104-E21, 11th Floor, Life Insurance Building, No. 1001, Fuzhong 1st Road, Fuzhong Community, Lianhua Street, Futian District, Shenzhen, Guangdong 518000

Patentee after: Shenzhen Rewo Micro Semiconductor Technology Co.,Ltd.

Address before: Building 3, Penghui Plaza, No. 48, Heishijiao Street, Shahekou District, Dalian City, Liaoning Province 116023

Patentee before: Shen Guang