JP2006344827A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability in a semiconductor device, to suppress increase in cost in assembling the semiconductor device, and to improve the reliability and quality of the assembling. <P>SOLUTION: A cross-section surface of an edge of a slit continuing into an edge part of a peripheral part of a brade 13 is formed in a circular shape, and a curvature radius of the circular of the cross-setion surface is formed larger as in a direction of a rotation center of the brade 13. This can take in a water for cooling when a multiple pickup substrate 9 including a feeding wire 5d is discretely diced. This can decrease a cutting resistance to suppress an occurrence of a clogging of the brade 13, which decreases burrs, chippings, chips, and cracks of the feeding wire 5d. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing technology, and more particularly to a technology effective when applied to improvement of product reliability.

After mounting multiple semiconductor chips on the main surface of the large substrate via solder bumps, mold each semiconductor chip with epoxy resin, cut the large substrate using a dicing machine, then burn-in test and electrical property evaluation A test is performed to manufacture a plurality of BGAs (Ball Grid Array) (see, for example, Patent Document 1).
JP-A-9-321088 (FIG. 7)

  For example, in a BGA (Ball Grid Array) having a relatively large package size of about 3 mm × 3 mm or more, in resin molding, one device formation region on a wiring board is covered with one cavity of a resin mold. Sealing is performed (such a resin molding method is hereinafter referred to as an individual molding method).

  On the other hand, in order to improve the number of obtained semiconductor devices, a batch molding method in which a plurality of device formation regions on the wiring substrate are covered with one cavity and resin-sealed is effective. However, since the resin has a higher coefficient of linear expansion than the wiring board, the wiring board tends to warp when the resin is formed only on one side of the wiring board. When the collective molding method is employed, the resin forming region and the amount of resin are larger than those of the individual molding method, and thus the warping of the wiring board occurs remarkably. As a result, BGA having a relatively large package size employs an individual molding method to perform resin sealing.

  In assembling a BGA having a relatively large package size as described above, the warpage of the substrate in each device formation region is reduced by adopting an individual molding method. In addition, when individualizing after resin sealing, individualization is performed by dicing, and the cost burden is reduced by capital investment that is cheaper than cutting dies.

  After resin sealing by the individual molding method, only the wiring board is diced into pieces. However, with dicing using a rotating blade, chips such as metal burrs on the wiring board enter the recesses on the blade surface due to cutting resistance during cutting and chatter (vibration) of the cut surface. Cause blade clogging.

  As a result, the metal wiring (copper wiring or copper lead) of the wiring board is not sufficiently cut, and there is a problem that metal burrs (copper burrs) are generated on the cut surface of the wiring board.

  In addition, if metal burrs adhere to the cut surface of the wiring board of the semiconductor device (product), a wiring short-circuit defect is caused, and the reliability of the product is lowered.

  In addition, if metal burrs adhere to the cut surface of the wiring board, it is necessary to perform a burring removal operation for removing the metal burrs after dicing, and there is a problem that the efficiency is low in assembling the semiconductor device.

  In addition, when the metal wiring of the wiring board is electroplated, a power supply wiring (power supply line) is formed from the inner side to the outer side in each device formation region. The problem is that metal burrs (copper burrs) due to wiring tend to appear on the cut surface, resulting in a decrease in product reliability.

  Another problem is that the friction coefficient is increased during dicing and the solder resist (insulating film) on the dicing line is swollen, thereby causing burrs on the power supply line.

  In addition, although this inventor changed and evaluated the braid | blade material, the braid | blade width (0.07-0.30mm), and the cutting speed (40-150mm / s), it suppresses about the burr | flash of a feeder line. I couldn't.

  Furthermore, as a result of studying countermeasures against blade clogging by the present inventor, it has been found that the following countermeasures can obtain the effect of reducing the occurrence of burr in the feeder line.

  For example, the structure of a molding die for resin sealing is changed to intentionally form a resin burr on a dicing line where no resin originally exists, and the resin and the substrate are cut together. At that time, the resin causes a dressing action, and clogging of the blade can be suppressed. As a result, the cutting resistance is reduced, the vibration to the wiring portion of the product is suppressed, and the occurrence of burrs on the power supply line of the substrate can be reduced.

  However, this measure has a problem that it is necessary to change the structure of the molding die and requires investment. Furthermore, when the shape of the semiconductor package changes, the structure of the molding die must be changed accordingly, and there is a problem that there is no adaptability according to the change of the shape of the semiconductor package.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the quality of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the reliability and quality of assembly while suppressing an increase in cost in assembling a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention prepares a wiring board having a plurality of device forming regions and metal wiring, and after resin sealing, the cross section of the edge of the slit that continues to the edge of the outer peripheral portion of the rotary cutting blade is formed in an arc shape. And the wiring board containing metal wiring is cut | disconnected using the rotary cutting blade formed so that the curvature radius of the said circular arc may become large as it goes to the rotation center direction of a rotary cutting blade.

  The present invention also provides a plurality of device formation regions formed on the main surface, a plurality of metal wirings and electrodes, a first insulating film, a first insulating film thicker than the first insulating film and formed on the metal wiring. A wiring board having two insulating films is prepared, and after resin sealing, the metal wiring and the second insulating film are cut together along the device forming region by dicing using a rotary cutting blade and separated into pieces. is there.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  When dividing into individual pieces by dicing, the cross section of the edge of the slit connected to the edge portion of the outer peripheral portion of the rotary cutting blade is formed in an arc shape, and the radius of curvature of the arc increases toward the rotation center of the rotary cutting blade. By using a rotary cutting blade formed so as to be large, the wiring board including the metal wiring is cut, thereby making it easy to take in water for water cooling. Thereby, the cutting resistance of the cutting surface can be reduced, clogging of the rotary cutting blade can be suppressed, and the occurrence of burrs, chipping, chipping and cracks in the metal wiring (feed line) can be reduced. As a result, the reliability of the semiconductor device (product) can be improved. Further, since the occurrence of burrs, chipping, chipping and cracks in the metal wiring can be reduced, the quality of the semiconductor device can be improved.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a manufacturing process flow diagram showing an example of assembly of the semiconductor device shown in FIG. 1, and FIG. 3 is a semiconductor shown in FIG. FIG. 4 is an enlarged partial plan view showing the structure of part A shown in FIG. 3, and FIG. 5 is taken along the line AA shown in FIG. It is a fragmentary sectional view showing an example of the shape of a blade cut by cutting. 6 is a partial sectional view showing an example of the shape of the blade cut along the line BB shown in FIG. 4, and FIG. 7 shows an example of the shape of the blade cut along the line CC shown in FIG. 8 is an enlarged partial plan view showing an example of the structure after resin molding in the assembly of the semiconductor device shown in FIG. 1, and FIG. 9 is an example of the structure at the time of dicing in the assembly of the semiconductor device shown in FIG. FIG.

  10 is a plan view showing an example of the structure after dicing in the assembly of the semiconductor device shown in FIG. 1, FIG. 11 is a plan view showing the shape of the blade of the modification, and FIG. 12 is the structure of part A shown in FIG. 13 is an enlarged partial plan view, FIG. 13 is a partial cross-sectional view showing the structure of a cross section cut along the line AA shown in FIG. 12, and FIG. 14 is a cross-sectional view cut along the line BB shown in FIG. It is a fragmentary sectional view which shows a structure. 15 is a partial cross-sectional view showing the structure of a cross section cut along the line CC shown in FIG. 12, FIG. 16 is a plan view showing the shape of a blade of another modification, and FIG. 17 is shown in FIG. 18 is an enlarged partial plan view showing the structure of part A, FIG. 18 is a partial sectional view showing the structure of a section cut along the line AA shown in FIG. 17, and FIG. 19 is taken along the line BB shown in FIG. FIG. 20 is a partial cross-sectional view showing a cross-sectional structure cut along the line CC shown in FIG. 17.

  21 is a partial cross-sectional view showing the structure of a semiconductor device according to a modification of the first embodiment of the present invention. FIG. 22 is an enlarged partial cross-sectional view showing an example of the structure during dicing in the assembly of the semiconductor device shown in FIG. It is.

  The semiconductor device assembled by the method of manufacturing a semiconductor device according to the first embodiment shown in FIG. 1 is a resin-encapsulated and relatively large semiconductor package having a wiring board. As an example of the semiconductor device, a multi-pin BGA (Ball Grid Array) 4 will be described.

  The configuration of the BGA 4 will be described. The package substrate 5, which is a wiring substrate on which the semiconductor chip 1 is mounted on the main surface 5 a via the die bond agent 6, the plurality of conductive wires 3, the semiconductor chip 1 and the plurality of wires 3 includes a sealing body 2 that seals resin 3 and solder balls 10 that are a plurality of external terminals provided on the back surface 5 b of the package substrate 5.

  Each of the plurality of wires 3 electrically connects a pad (electrode) 1c formed on the main surface 1a of the semiconductor chip 1 and a bonding electrode (electrode) 5e formed on the main surface 5a of the package substrate 5 corresponding thereto. Connected to.

  The sealing body 2 is for sealing the semiconductor chip 1 and the plurality of wires 3 on the main surface 5a of the package substrate 5 with resin. A heat spreader 7 as a heat radiating member is attached to the surface 2 a of the sealing body 2 with an adhesive 8. The semiconductor chip 1 has a quadrangular planar shape that intersects the thickness direction.

  The package substrate (wiring substrate) 5 has a square shape intersecting the thickness direction in the first embodiment, and is square, and the planar shape of the sealing body 2 formed on the main surface 5a of the package substrate 5 is It is a square shape.

  A plurality of solder balls 10 as external terminals are arranged in a lattice pattern on the outer peripheral portion of the back surface 5b of the package substrate 5 with its central portion removed.

  The BGA 4 is a relatively large multi-pin semiconductor package. For example, the BGA 4 has a package size of 33 mm × 33 mm and a size of 520 pins. However, these numerical values are not limited.

  In addition, the heat spreader 7 attached to the surface 2a of the sealing body 2 improves the heat dissipation effect of the BGA 4, but suppresses package warpage during high temperature processing such as reflow when the BGA 4 is mounted on the substrate. Is also possible.

  The package substrate 5 incorporated in the BGA 4 is made of a base material such as glass epoxy resin, for example, and has a multilayer wiring structure. Furthermore, a plurality of bonding electrodes 5e connected to the wires 3 are provided on the main surface 5a of the package substrate 5, while a plurality of lands 5h to which the solder balls 10 are connected are provided on the back surface 5b. Yes.

  Further, the main wiring (metal wiring) 5c, the bonding electrode 5e and the land 5h provided on the package substrate 5 are subjected to electrolytic plating. Therefore, as described in the above problem, the package substrate 5 has Is provided with a feed line 5d which is a metal wiring exposed at the outer peripheral end.

  Since the BGA 4 is a large semiconductor package, the wiring board (multiple substrate 9 shown in FIG. 2) used in the assembly becomes a large thin plate member (substrate, wiring board). At this time, the planar shape of the thin plate member intersecting with the thickness direction is rectangular. Therefore, an individual molding method in which one device region (device forming region) 9c on the multi-piece substrate 9 shown in FIG. 8 is covered with one cavity 12b of the resin molding die 12 shown in FIG. It is assembled by adopting. As a result, the warpage in the individual device regions 9c, that is, the package substrate 5 is reduced, and the individual pieces are separated by dicing using a rotating blade (rotating cutting blade) 13 when the resin is sealed. Since the singulation is performed, it is possible to reduce the cost burden with a lower capital investment as compared with the case where the singulation is performed using a cutting die.

  Since resin sealing is performed by the individual molding method and individualization is performed by dicing, the dicing BGA 4 has a cut surface of the feeder 5d on the side surface of the package substrate 5 as shown in FIG. Exposed.

  Further, the main wiring 5c, the power supply line 5d, the bonding electrode 5e, and the land 5h in the package substrate 5 are made of, for example, a copper alloy, and each surface except the cut surface is subjected to electrolytic plating. The main wiring 5c and the power supply line 5d are also copper wirings or copper leads (conductor leads).

  Further, the regions other than the exposed bonding electrodes 5e and lands 5h on the front and back surfaces of the package substrate 5 are the first solder resist film 5f, which is the first insulating film, or the second insulation thicker than the first solder resist film 5f. The film is covered with one of the second solder resist films 5g which is a film.

  The second solder resist film 5g includes a region corresponding to the dicing line 9g (see FIG. 8) and is formed on the feeder line 5d. The thickness of the second solder resist film 5g is, for example, 40 to 60 μm, and is about twice the thickness of a general solder resist film. The second solder resist film 5g only needs to be formed on the power supply line 5d at least in a region corresponding to the dicing line 9g, and is not necessarily formed on all the power supply lines 5d.

  On the other hand, the first solder resist film 5f is formed in a region where the second solder resist film 5g is not formed in a region other than where the bonding electrode 5e and the land 5h are exposed. The thickness of the first solder resist film 5f is, for example, 20 to 30 μm, which is the same thickness as a general solder resist film. Accordingly, the second solder resist film 5g is approximately twice as thick as the first solder resist film 5f, and at least the region corresponding to the dicing line 9g is provided with the thick second solder resist film 5g. Is preferred.

  Further, as shown in FIG. 8, the multi-chip substrate 9 corresponds to each device region 9c and is subjected to gate Au plating as the gate metal portion 5i.

  In addition, the resin for sealing which forms the sealing body 2 in BGA4 is a thermosetting epoxy resin etc., for example. The semiconductor chip 1 is made of, for example, silicon, and a plurality of pads 1c and semiconductor integrated circuits are formed on the main surface 1a. Furthermore, the wire 3 is a gold wire, for example.

  Next, the manufacturing method of BGA4 of this Embodiment is demonstrated along the manufacturing process flowchart shown in FIG.

  First, the multi-piece substrate 9 shown in FIGS. 2 and 8 is prepared. As shown in FIG. 8, a plurality of device formation regions 9c, which are a plurality of device formation regions, are formed side by side along the substrate longitudinal direction 9e on the multi-chip substrate 9, and each device region 9c has a substrate longitudinal direction. On both sides of 9e, slits 9d are formed along the device region 9c in a direction substantially perpendicular to the substrate longitudinal direction 9e.

  Further, each device region 9c is formed with a plurality of metal wires such as a main wire 5c and a feeder wire 5d made of a copper alloy, and electrodes such as bonding electrodes 5e and lands 5h. Is electroplated. Accordingly, each power supply line 5d is arranged from the inner side toward the outer side across the dicing line 9g.

  Further, the gate Au plating is applied as the gate metal portion 5 i to the corner portion of each device region 9 c of the main surface 9 a of the multi-chip substrate 9. The gate metal portion 5i is for facilitating peeling of the gate resin remaining on the substrate.

  In addition, a plurality of lands 5h as shown in FIG. 1 are arranged in a grid pattern except for the central portion in each device region 9c on the back surface 9b of the multi-chip substrate 9. Further, a plurality of positioning holes 9 f are formed at both ends in the width direction of the multi-piece substrate 9.

  In each package substrate 5 included in the multi-chip substrate 9, a thick second solder resist film 5g having a thickness of about 40 to 60 μm is formed on the power supply line 5d including the dicing line 9g. On the other hand, a thin first solder resist film 5f having a thickness of about 20 to 30 μm is formed in a region where the second solder resist film 5g is not formed in a region other than where the bonding electrode 5e and the land 5h are exposed. Yes.

  Thereafter, die bonding in step S1 shown in FIG. 2 is performed. That is, the package substrate 5 of the multi-chip substrate 9 and the semiconductor chip 1 are connected. Here, the semiconductor chip 1 is fixed to the substantially central portion of each device region 9 c of the multi-chip substrate 9 via the die bond agent 6. Thereby, the back surface 1 b of the semiconductor chip 1 and the multi-chip substrate 9 are connected via the die bond agent 6.

  After die bonding, wire bonding shown in step S2 is performed. That is, as shown in FIGS. 1 and 2, the pad 1 c of the semiconductor chip 1 and the bonding electrode 5 e of the package substrate 5 corresponding thereto are connected by the wire 3 to electrically connect the semiconductor chip 1 and the package substrate 5. To do.

  After wire bonding, resin molding shown in step S3 is performed. Since the BGA 4 is a large semiconductor package, the multi-chip substrate 9 shown in FIG. 8 used for the assembly becomes a large thin plate member. Therefore, as described in the above problem, individual molding for performing resin sealing by covering one device region (device forming region) 9c on the multi-piece substrate 9 with one cavity 12b of the resin molding die 12. By assembling by adopting the method, it is possible to reduce the warpage of each device region 9c, that is, the package substrate 5. Furthermore, when individualizing after resin sealing, by dividing into individual pieces by dicing, the cost burden can be reduced with a lower capital investment compared to performing individualization with a cutting die. be able to.

  Therefore, a plurality of cavities 12b are individually formed in the upper mold 12a of the resin molding die 12 for individual molding in a one-to-one correspondence with the device regions 9c of the multi-cavity substrate 9. Individual molding is performed using the resin molding die 12 having the upper die 12a and the lower die 12c. In that case, first, the multi-chip substrate 9 having been wire-bonded is disposed on the mold surface 12d of the lower mold 12c. Thereafter, the upper mold 12a and the lower mold 12c are clamped to perform clamping, and in this state, the cavity 12b is filled with a sealing resin. The sealing resin is, for example, a thermosetting epoxy resin mixed with a filler.

  The sealing body 2 is formed by completing the filling of the sealing resin into the cavity 12b. Thereafter, the sealing resin is cured, the mold is further opened, and a large number of substrates 9 are taken out from the resin molding die 12. As shown in FIG. 8, the sealing body 2 is formed in each device region 9 c of the multi-cavity substrate 9 taken out from the resin molding die 12.

  After resin molding, ball mounting is performed in step S4 shown in FIG. Here, as shown in FIG. 1, the solder balls 10 are attached to the plurality of lands 5h in each device region 9c on the back surface 9b of the multi-chip substrate 9.

  Thereafter, dicing shown in step S5 is performed. That is, individualization is performed by dicing. At that time, first, as shown in FIG. 9, a multi-piece substrate 9 is arranged with its back surface 9b facing upward with a pressing rubber (jig) 15 interposed on a dicing stage. That is, the multi-piece substrate 9 is disposed on the dicing stage 14 via the pressing rubber 15 with the back surface 9b side to which the solder balls 10 are attached facing upward. More specifically, dicing is performed in a state where the surface 2 a of the sealing body 2 and the side surface (tapered surface) connected from the surface 2 a of the sealing body 2 are in contact with the pressing rubber 15. Furthermore, in a state where the second solder resist film 5g, which is a thick insulating film disposed on both sides of the blade 13 in the rotational axis direction 13f, is supported by the pressing rubber 15, the power supply line 5d and the second solder resist film 5g are supported by the blade 13. Are cut together.

  Accordingly, since the multi-piece substrate 9 can be fixed more securely than the surface 2a of the sealing body 2 by contacting the pressing rubber 15 and fixed, vibrations generated in the multi-piece substrate 9 due to dicing can be suppressed. . That is, since the semiconductor device could not be fixed reliably, the multi-chip substrate 9 vibrates during dicing, and the generated burr of the power supply line 5d can be suppressed.

  Further, since both side portions of the blade 13 in the multi-piece substrate 9 are directly supported by the pressing rubber 15, vibration of the multi-piece substrate 9 during dicing can be suppressed, and as a result, the burr of the power supply line 5d is generated. Can be suppressed.

  In this state, dicing is performed using the blade 13 along the dicing line 9g shown in FIG. In the case of the multi-chip substrate 9 shown in FIG. 8, dicing is performed by moving the blade 13 along the device region 9c and in a direction perpendicular to the slit 9d. At that time, in the multi-chip substrate 9 of the first embodiment, since the power supply line 5d is provided from the inner side to the outer side across the dicing line 9g, it is formed by cutting the power supply line 5d. Burr (copper burr) tends to adhere to the blade 13, and the blade 13 is likely to be clogged by the burr.

  Therefore, in the method of manufacturing the semiconductor device according to the first embodiment, the blade 13 having the shape shown in FIGS. Here, the blade 13 is a disk-shaped rotary cutting blade in which a plurality of slits 13b are formed on the outer peripheral portion thereof as shown in FIG. 3, and the slit 13b is continuous with the edge portion 13a (see FIG. 5) of the outer peripheral portion. The edge of the cross section is formed in an arc shape. Further, the radius of curvature 13d of the arc 13e of the cross section is formed so as to gradually increase toward the rotation center 13c of the blade 13.

  That is, a plurality of slits 13 b as shown in FIG. 4 are formed at substantially equal intervals on the outer peripheral portion of the blade 13. As shown in FIG. 5, since the edge part 13a of an outer peripheral part has the role of the blade for cutting, the cross section of the edge part 13a becomes a sharp shape. Further, the edge of the slit 13b connected to the outer edge 13a is formed in a shape in which the cross section forms an arc 13e (also referred to as an R shape). The curvature radius 13d is formed so as to gradually increase toward the rotation center 13c of the blade 13. For example, FIG. 6 shows the cross-sectional shape of the edge near the outer periphery of the slit 13b, and FIG. 7 shows the cross-sectional shape of the edge of the slit 13b near the rotation center 13c from FIG. Is.

  Accordingly, the curvature radius 13d of the arc 13e shown in FIG. 7 is larger than the curvature radius 13d of the arc 13e shown in FIG. Note that the radius of curvature 13d of the arc 13e in the cross section of the edge of the slit 13b may be formed so as to gradually increase in the direction toward the rotation center 13c of the blade 13, or gradually. You may form so that it may become large smoothly.

  In this way, the edge of the slit 13b connected to the edge 13a of the outer peripheral portion of the blade 13 is formed in an arc shape, and the radius of curvature 13d of the arc 13e in the cross section of the edge is directed toward the rotation center 13c of the blade 13. By performing dicing using the blade 13 formed to be large, it is possible to easily take in water for water cooling at the time of cutting.

  That is, since the radius of curvature 13d of the arc 13e of the cross section at the edge of the slit 13b increases in the direction of the rotation center 13c, water for water cooling is used when cutting the multi-chip substrate 9 including the feeder 5d. It is possible to make it easy to capture, thereby reducing the cutting resistance of the cutting surface. Moreover, as shown in FIG. 4, since the shape of the plane direction is also formed in the circular arc shape in the entrance part (B part) from an outer peripheral part to the slit 13b, it is easy to take in the water for water cooling at the time of dicing Similarly, the cutting resistance of the cutting surface can be reduced.

  As a result, clogging of the blade 13 can be suppressed and the occurrence of burrs, chipping, chipping and cracks in the metal wiring such as the power supply line 5d can be reduced, and therefore the reliability of products such as BGA 4 (semiconductor device) is improved. be able to.

  Further, since the occurrence of burrs, chipping, chipping and cracks in the power supply line 5d can be reduced, the quality of the BGA 4 can be improved.

  Furthermore, since the generation of burrs, chipping, cracks and cracks in the power supply line 5d can be reduced by using the blade 13 having the slit 13b formed on the outer peripheral portion, the reliability and quality of the assembly can be suppressed while suppressing the cost increase in the assembly of the BGA 4. Can be improved.

  In the multi-chip substrate 9 of the first embodiment, a thick second solder resist film 5g having a thickness of about 40 to 60 μm is formed on the power supply line 5d straddling the dicing line 9g on the dicing line 9g. As a result, the strength of the solder resist film is increased, so that the solder resist film can be prevented from curling due to dicing.

  Thereby, generation | occurrence | production of the burr | flash of the feeder 5d can be prevented, generation | occurrence | production of a chipping, a crack, and a crack can be reduced by suppressing clogging of the braid | blade 13. FIG. As a result, it is possible to improve the reliability of products such as BGA4. Furthermore, since the occurrence of burrs, chipping, chipping and cracks in the power supply line 5d can be reduced, the quality of the BGA 4 can be improved as described above.

  When the singulation is completed by dicing, the BGA structure as shown in FIG. 10 is obtained.

  Then, the heat spreader attachment shown in step S6 of FIG. 2 is performed. That is, the heat spreader 7 is fixed to the surface 2a of the sealing body 2 in the separated BGA 4 by the adhesive 8, thereby completing the assembly of the BGA 4 shown in FIG. Note that the heat spreader 7 is not necessarily attached.

  Next, a modification of the first embodiment will be described.

  The blade 13 of the modified example shown in FIG. 11 is formed so that the width of each of the plurality of slits 13b formed in the outer peripheral portion is wider from the inside to the outside (from the C portion to the B portion) as shown in FIG. It is what. Thereby, the discharge efficiency at the time of water cooling and the taken-in water can be improved. As a result, entrainment of cutting waste can be reduced, cutting resistance and clogging can be reduced, and occurrence of burrs, chipping, chipping and cracks in the power supply line 5d can be reduced. Therefore, the quality of the BGA 4 can be improved.

  Also in the blade 13 of the modified example shown in FIG. 11, as shown in FIGS. 13 to 15, the edge of the slit 13 b connected to the edge 13 a of the outer peripheral portion of the blade 13 is formed in an arc shape, and the edge Since the radius of curvature 13d of the arc 13e in the cross section of the portion increases toward the rotation center 13c of the blade 13, water for water cooling at the time of cutting can be obtained similarly to the blade 13 shown in FIG. It can be made easier to capture. Furthermore, since the shape in the plane direction is also formed in an arc shape at the entry portion (B portion) from the outer peripheral portion of the blade 13 to the slit 13b, water for water cooling at the time of dicing can be easily taken in. Like the blade 13 shown in FIG. 3, the cutting resistance of the cutting surface can be reduced.

  Further, in the blade 13 of the modification shown in FIG. 16, the width of each of the plurality of slits 13b formed on the outer peripheral portion is the inside of the slit 13b as shown in FIG. 17 (from the B portion to the C portion, that is, the rotation center of the blade 13). 13c direction) is formed wider. Thereby, the amount of water taken in at the time of water cooling can be increased, the cooling efficiency can be increased, and cutting resistance and clogging can be reduced. As a result, it is possible to reduce the occurrence of burrs, chipping, chipping and cracks in the power supply line 5d, and the quality of the BGA 4 can be improved.

  Also in the blade 13 of the modified example shown in FIG. 16, as shown in FIGS. 18 to 20, the edge of the slit 13 b that continues to the edge 13 a of the outer periphery of the blade 13 is formed in an arc shape, and the edge Since the radius of curvature 13d of the arc 13e in the cross section of the portion increases toward the rotation center 13c of the blade 13, water for water cooling at the time of cutting can be obtained similarly to the blade 13 shown in FIG. It can be made easier to capture. Furthermore, since the shape in the plane direction is also formed in an arc shape at the entry portion (B portion) from the outer peripheral portion of the blade 13 to the slit 13b, water for water cooling at the time of dicing can be easily taken in. Like the blade 13 shown in FIG. 3, the cutting resistance of the cutting surface can be reduced.

  Next, the BGA 4 of the modification shown in FIG. 21 is a thick second solder resist film 5g having a thickness of 40 to 60 μm over the entire surface of the package substrate 5 (multiple substrate 9). When dicing into individual pieces, as shown in FIG. 22, the power supply line 5d and the thick second solder resist film 5g are cut together as in the case of FIG.

  Thereby, since the second solder resist film 5g is formed thick and its strength is increased, it is possible to suppress the bending of the solder resist film due to dicing. As a result, as in the case of FIG. 9, the occurrence of burrs in the power supply line 5d can be prevented, and the occurrence of chipping, chipping and cracks can be reduced by suppressing clogging of the blade 13.

(Embodiment 2)
23 is a plan view showing an example of the structure of the semiconductor device according to the second embodiment of the present invention through a sealing body, FIG. 24 is a cross-sectional view showing an example of the structure of the semiconductor device shown in FIG. 23, and FIG. FIG. 26 is an enlarged partial sectional view showing the structure of part A shown in FIG. 24, FIG. 26 is a manufacturing process flow diagram showing an example of assembly up to the resin mold in the assembly of the semiconductor device shown in FIG. 23, and FIG. It is a manufacturing process flowchart which shows an example.

  The semiconductor device according to the second embodiment shown in FIGS. 23 to 25 is a BGA 18 assembled by adopting a batch molding method, and is structurally similar to the BGA 4 according to the first embodiment. The heat spreader 7 is not attached to the BGA 18.

  Next, a method for manufacturing the BGA 18 according to the second embodiment will be described with reference to manufacturing process flowcharts shown in FIGS.

  First, substrate preparation shown in step S1 of FIG. 26 is performed. Here, a multi-piece substrate 9 in which regions for forming a plurality of package substrates 5 are partitioned is prepared.

  Thereafter, die bonding shown in step S2 is performed to fix the semiconductor chip 1 on the multi-piece substrate 9 via the die bonding agent 6 shown in FIG.

  Thereafter, wire bonding shown in step S3 is performed. Here, as shown in FIG. 23, the pads 1c on the main surface 1a of the semiconductor chip 1 and the bonding electrodes 5e of the package substrate 5 of the multi-chip substrate 9 corresponding to the pads 1c are electrically conductive wires 3 such as gold wires. Electrically connect with.

  Thereafter, resin molding shown in step S4 is performed. Here, on the multi-cavity substrate 9, resin sealing is performed in a state where a plurality of regions (device regions) on the multi-cavity substrate 9 are collectively covered with one cavity 12b of the resin molding die 12. Thereby, the collective sealing body 16 is formed. The sealing resin forming the collective sealing body 16 is, for example, a thermosetting epoxy resin.

  Thereafter, the ball mounting shown in step S5 of FIG. 27 is performed, and the solder balls 10 are connected to the lands 5h as shown in FIG.

  Then, the mark shown in step S6 is performed. Here, the marking 17 is performed by a laser marking method or the like to mark the collective sealing body 16. The marking 17 may be performed by, for example, an ink marking method.

  Thereafter, individualization shown in step S7 is performed. Here, the dicing tape 11 is affixed to the surface of the collective sealing body 16, and is cut into pieces by the dicing blade 13 while being fixed by the dicing tape 11.

  At that time, by adopting the blades 13 having the shapes shown in FIGS. 3 to 7 to separate them, it is possible to easily take in water for water cooling at the time of cutting. Thereby, the cutting resistance of the cutting surface can be reduced, and clogging of the resin into the blade 13 can be suppressed. As a result, the occurrence of burrs, chipping, chipping and cracks in the metal wiring can be reduced, and the reliability of products such as the BGA 18 can be improved.

  When the blade 13 having the shape shown in FIGS. 11 to 15 and the blade 13 having the shape shown in FIGS. 16 to 20 are adopted, clogging of the resin into the blade 13 can be suppressed, and the metal wiring Generation of burrs, chipping, cracks and cracks can be reduced.

  Thereafter, as shown in step S8 of FIG. 27, the assembly of the BGA 18 is completed and the product is completed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first embodiment, as countermeasures against clogging of the blade 13 at the time of singulation by dicing, a countermeasure based on the shape of the blade 13 and a thick solder resist film having a thickness of about 40 to 60 μm (second solder resist film 5g). However, both measures may be combined or only one of them may be taken.

  In the first and second embodiments, the BGAs 4 and 18 are taken up as an example of the semiconductor device. However, the semiconductor device is assembled using a wiring board having metal wiring, and is separated into pieces by dicing. As long as the semiconductor device is used, an LGA (Land Grid Array) other than the BGA may be used.

  Furthermore, in the semiconductor device, the heat spreader 7 does not necessarily have to be attached.

  The present invention is suitable for an electronic device assembly and a semiconductor device manufacturing method.

It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. It is a manufacturing process flowchart which shows an example of the assembly of the semiconductor device shown in FIG. It is a top view which shows an example of the shape of the braid | blade used at the dicing process of the assembly of the semiconductor device shown in FIG. FIG. 4 is an enlarged partial plan view showing a structure of a portion A shown in FIG. 3. It is a fragmentary sectional view which shows an example of the shape of the braid | blade cut | disconnected along the AA line shown in FIG. It is a fragmentary sectional view which shows an example of the shape of the braid | blade cut | disconnected along the BB line shown in FIG. It is a fragmentary sectional view which shows an example of the shape of the braid | blade cut | disconnected along CC line shown in FIG. FIG. 2 is an enlarged partial plan view showing an example of a structure after resin molding in the assembly of the semiconductor device shown in FIG. 1. FIG. 2 is an enlarged partial cross-sectional view illustrating an example of a structure during dicing in the assembly of the semiconductor device illustrated in FIG. 1. It is a top view which shows an example of the structure after the dicing in the assembly of the semiconductor device shown in FIG. It is a top view which shows the shape of the braid | blade of a modification. FIG. 12 is an enlarged partial plan view showing a structure of a portion A shown in FIG. 11. It is a fragmentary sectional view which shows the structure of the cross section cut | disconnected along the AA line shown in FIG. It is a fragmentary sectional view which shows the structure of the cross section cut | disconnected along the BB line shown in FIG. It is a fragmentary sectional view which shows the structure of the cross section cut | disconnected along CC line shown in FIG. It is a top view which shows the shape of the braid | blade of another modification. FIG. 17 is an enlarged partial plan view showing the structure of part A shown in FIG. 16. It is a fragmentary sectional view which shows the structure of the cross section cut | disconnected along the AA line shown in FIG. It is a fragmentary sectional view which shows the structure of the cross section cut | disconnected along the BB line shown in FIG. It is a fragmentary sectional view which shows the structure of the cross section cut | disconnected along CC line shown in FIG. It is a fragmentary sectional view which shows the structure of the semiconductor device of the modification of Embodiment 1 of this invention. FIG. 22 is an enlarged partial cross-sectional view showing an example of a structure during dicing in the assembly of the semiconductor device shown in FIG. 21. It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of Embodiment 2 of this invention. FIG. 24 is a cross-sectional view illustrating an example of the structure of the semiconductor device illustrated in FIG. 23. FIG. 25 is an enlarged partial sectional view showing a structure of a portion A shown in FIG. 24. FIG. 24 is a manufacturing process flow diagram illustrating an example of assembly up to a resin mold in the assembly of the semiconductor device illustrated in FIG. 23. FIG. 24 is a manufacturing process flow diagram illustrating an example of assembly after resin molding in the assembly of the semiconductor device illustrated in FIG. 23.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Main surface 1b Back surface 1c Pad (electrode)
2 Sealed body 2a Surface 3 Wire 4 BGA (Semiconductor device)
5 Package board (wiring board)
5a main surface 5b back surface 5c main wiring (metal wiring)
5d Feed line (metal wiring)
5e Bonding electrode (electrode)
5f First solder resist film (first insulating film)
5g Second solder resist film (second insulating film)
5h Land 5i Gate metal part 6 Die bond agent 7 Heat spreader 8 Adhesive 9 Multi-cavity substrate (wiring substrate)
9a Main surface 9b Back surface 9c Device region (device formation region)
9d Slit 9e Substrate longitudinal direction 9f Positioning hole 9g Dicing line 10 Solder ball 11 Dicing tape 12 Resin molding die 12a Upper die 12b Cavity 12c Lower die 12d Mold surface 13 Blade (Rotating cutting blade)
13a Edge portion 13b Slit 13c Center of rotation 13d Radius of curvature 13e Arc 13f Rotational axis direction 14 Dicing stage 15 Holding rubber (jig)
16 Collective sealing body 17 Marking 18 BGA (Semiconductor device)

Claims (5)

(A) preparing a wiring board having a main surface, a plurality of device forming regions formed on the main surface, and a plurality of metal wirings and electrodes;
(B) connecting the wiring board and the semiconductor chip;
(C) electrically connecting the electrode of the wiring board and the electrode of the semiconductor chip;
(D) resin sealing the semiconductor chip;
(E) cutting the wiring board including the metal wiring into individual pieces by cutting along the device forming region by dicing using a disk-shaped rotary cutting blade having a plurality of slits formed on the outer peripheral portion; Have
The edge of the slit connected to the edge portion of the outer peripheral portion of the rotary cutting blade is formed in an arc shape in cross section, and the radius of curvature of the arc of the cross section becomes larger toward the rotation center direction of the rotary cutting blade. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed. (A) preparing a wiring board having a main surface, a plurality of device forming regions formed on the main surface, and a plurality of metal wirings and electrodes;
(B) connecting the wiring board and the semiconductor chip;
(C) electrically connecting the electrode of the wiring board and the electrode of the semiconductor chip;
(D) resin sealing the semiconductor chip in a state where one device forming region is covered with one cavity of a resin molding die;
(E) cutting the wiring board including the metal wiring into individual pieces by cutting along the device forming region by dicing using a disk-shaped rotary cutting blade having a plurality of slits formed on the outer peripheral portion; Have
The edge of the slit connected to the edge of the outer peripheral portion of the rotary cutting blade is formed in an arc shape in cross section, and the radius of curvature of the arc of the cross section gradually increases toward the rotation center direction of the rotary cutting blade. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed as described above. (A) A main surface, a plurality of device formation regions formed on the main surface, a plurality of metal wirings and electrodes, a first insulating film, and a thicker than the first insulating film and formed on the metal wiring. Preparing a wiring board having a second insulating film;
(B) connecting the wiring board and the semiconductor chip;
(C) electrically connecting the electrode of the wiring board and the electrode of the semiconductor chip;
(D) resin sealing the semiconductor chip;
(E) cutting the wiring board along the device formation region by dicing using a disk-shaped rotary cutting blade,
In the step (e), the metal wiring and the second insulating film are cut together by the rotary cutting blade. (A) A main surface, a plurality of device formation regions formed on the main surface, a plurality of metal wirings and electrodes, a first insulating film, and a thicker than the first insulating film and formed on the metal wiring. Preparing a wiring board having a second insulating film;
(B) connecting the wiring board and the semiconductor chip;
(C) electrically connecting the electrode of the wiring board and the electrode of the semiconductor chip;
(D) resin sealing the semiconductor chip;
(E) cutting the wiring board along the device formation region by dicing using a disk-shaped rotary cutting blade,
In the step (e), in a state where the second insulating film disposed on both sides in the rotation axis direction of the rotary cutting blade is supported by a jig, the metal wiring and the second insulating film are A method for manufacturing a semiconductor device, characterized in that the semiconductor device is cut together. (A) A main surface, a plurality of device formation regions formed on the main surface, a plurality of metal wirings and electrodes, a first insulating film, and a thicker than the first insulating film and formed on the metal wiring. Preparing a wiring board having a second insulating film;
(B) connecting the wiring board and the semiconductor chip;
(C) electrically connecting the electrode of the wiring board and the electrode of the semiconductor chip;
(D) resin sealing the semiconductor chip in a state where one device forming region is covered with one cavity of a resin molding die;
(E) cutting the wiring board along the device formation region by dicing using a disk-shaped rotary cutting blade,
In the step (e), the metal wiring and the second insulating film are cut together by the rotary cutting blade.

Images