JP4477976B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor manufacturing technology, and more particularly to a technology effective when applied to improvement of product reliability.

After mounting multiple semiconductor chips on the main surface of the large substrate via solder bumps, mold each semiconductor chip with epoxy resin, cut the large substrate using a dicing machine, then burn-in test and electrical property evaluation A test is performed to manufacture a plurality of BGAs (Ball Grid Array) (see, for example, Patent Document 1).
JP-A-9-321088 (FIG. 7)

  For example, in a BGA (Ball Grid Array) having a relatively large package size of about 3 mm × 3 mm or more, in resin molding, one device formation region on a wiring board is covered with one cavity of a resin mold. Sealing is performed (such a resin molding method is hereinafter referred to as an individual molding method).

  On the other hand, in order to improve the number of obtained semiconductor devices, a batch molding method in which a plurality of device formation regions on the wiring substrate are covered with one cavity and resin-sealed is effective. However, since the resin has a higher coefficient of linear expansion than the wiring board, the wiring board tends to warp when the resin is formed only on one side of the wiring board. When the collective molding method is employed, the resin forming region and the amount of resin are larger than those of the individual molding method, and thus the warping of the wiring board occurs remarkably. As a result, BGA having a relatively large package size employs an individual molding method to perform resin sealing.

  In assembling a BGA having a relatively large package size as described above, the warpage of the substrate in each device formation region is reduced by adopting an individual molding method. In addition, when individualizing after resin sealing, individualization is performed by dicing, and the cost burden is reduced by capital investment that is cheaper than cutting dies.

  After resin sealing by an individual molding method, only the wiring board is diced into pieces. However, with dicing using a rotating blade, chips such as metal burrs on the wiring board enter the recesses on the blade surface due to cutting resistance during cutting and chatter (vibration) of the cut surface. Cause blade clogging.

  As a result, the metal wiring (copper wiring or copper lead) of the wiring board is not sufficiently cut, and there is a problem that metal burrs (copper burrs) are generated on the cut surface of the wiring board.

  In addition, if metal burrs adhere to the cut surface of the wiring board of the semiconductor device (product), a wiring short-circuit defect is caused, and the reliability of the product is lowered.

  Further, if metal burrs adhere to the cut surface of the wiring board, it is necessary to carry out burrs removal work for removing the metal burrs after dicing, and there is a problem that the efficiency is low in assembling the semiconductor device.

  In addition, when the metal wiring of the wiring board is electroplated, a power supply wiring (power supply line) is formed from the inner side to the outer side in each device formation region. The problem is that metal burrs (copper burrs) due to wiring tend to appear on the cut surface, resulting in a decrease in product reliability.

  An object of the present invention is to provide a semiconductor device manufacturing method capable of improving reliability.

  Another object of the present invention is to provide a semiconductor device manufacturing method capable of improving the assembly efficiency.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a main surface, a back surface facing the main surface, a plurality of device formation regions formed on the main surface, a step of preparing a wiring board having a plurality of wirings, A step of preparing a semiconductor chip having a back surface facing the main surface and a plurality of electrodes formed on the main surface, and mounting the semiconductor chips on the plurality of device formation regions of the wiring board, respectively. A step of electrically connecting a part of the plurality of wirings and a plurality of electrodes of the semiconductor chip, a main surface of the wiring substrate and a first sealing body for resin-sealing the semiconductor chip, A step of integrally forming a second sealing body disposed outside the device forming region, and a step of simultaneously cutting the second sealing body and the plurality of wirings by dicing into individual pieces. It is what you have.

  Further, according to the present invention, a plurality of device forming regions are formed side by side along the substrate longitudinal direction, and slits are formed on both sides of each device forming region in the substrate longitudinal direction. A step of preparing a wiring board having, a step of connecting the wiring board and a semiconductor chip, a step of electrically connecting an electrode of the wiring board and an electrode of the semiconductor chip, and one of resin molding dies Sealing the semiconductor chip with a sealing resin in a state where one device formation region is covered with a cavity, and forming a first sealing body and a second sealing body disposed outside the sealing body; And a step of cutting the second sealing body and the metal wiring together by dicing into individual pieces along the device formation region and in a direction perpendicular to the slit.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  When cutting into individual pieces by dicing, the resin cutting part and the metal wiring are cut together, so that the sealing resin that forms the resin cutting part causes a dressing action on the blade, and the blade is made of metal burrs. Clogging can be suppressed. As a result, the occurrence of metal burrs on the cut surface of the wiring board can be prevented, the occurrence of wiring short-circuit defects can be prevented, and the reliability of the semiconductor device can be improved. Further, since the occurrence of metal burrs can be prevented, the number of times of performing the burr removal work after dicing can be reduced, and the efficiency of assembling the semiconductor device can be improved.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
1 is a plan view showing an example of the structure of the semiconductor device according to the embodiment of the present invention, FIG. 2 is a side view showing an example of the structure of the semiconductor device shown in FIG. 1, and FIG. 3 is the structure of the semiconductor device shown in FIG. 4 is a back view showing an example of the structure of the semiconductor device shown in FIG. 1, FIG. 5 is a manufacturing process flow diagram showing an example of assembling the semiconductor device shown in FIG. 1, and FIG. 7 is a plan view showing an example of the structure of a wiring board used for assembling the semiconductor device shown in FIG. 7, FIG. 7 is a back view showing an example of the back surface structure of the wiring board shown in FIG. 6, and FIG. FIG. 9 is a plan view showing an example of the structure of the upper mold of a resin molding die used in the resin sealing step of assembly, and FIG. 9 is an example of the structure of the resin molding mold cut along the line AA shown in FIG. FIG. 10 is a sectional view of the resin molding die cut along the line BB shown in FIG. FIG. 11 is a partial cross-sectional view showing an example of a structure before mold clamping in the resin sealing process of assembling the semiconductor device shown in FIG. 1, and FIG. 12 is an assembly of the semiconductor device shown in FIG. FIG. 13 is a partial cross-sectional view showing an example of the structure at the time of mold opening in the resin sealing step of assembling the semiconductor device shown in FIG. 14 is a partial plan view showing an example of the structure of the substrate after resin sealing in the assembly of the semiconductor device shown in FIG. 1, FIG. 15 is a partial back view showing the structure of the substrate shown in FIG. 14, and FIG. 16 is shown in FIG. Sectional drawing which shows an example of the structure at the time of dicing in the isolation | separation process of the assembly of a semiconductor device, FIG. 17 is an expanded partial sectional view which shows the structure of the C section shown in FIG. 16, FIG. 18 is a deformation | transformation of embodiment of this invention Example of semiconductor device assembly Enlarged partial sectional view showing the structure of a dicing in fragmented process, FIG. 19 is a sectional view showing a structure of a semiconductor device of a modified example of the embodiment of the present invention.

  The semiconductor device of the present embodiment shown in FIGS. 1 to 4 is a resin-encapsulated and relatively large semiconductor package having a wiring board. In this embodiment, as an example of the semiconductor device, there are many semiconductor devices. A pin BGA (Ball Grid Array) 4 will be described.

  The configuration of the BGA 4 will be described. As shown in FIG. 3, the BGA 4 is formed on the main surface 1 a of the semiconductor chip 1 and the package substrate 5, which is a wiring substrate on which the semiconductor chip 1 is mounted on the main surface 5 a via the die bonding agent 6. On the main surface 5a of the package substrate 5, a plurality of wires 3 for electrically connecting the pads (electrodes) 1c and the bonding electrodes (electrodes) 5e formed on the main surface 5a of the package substrate 5 corresponding thereto A sealing body 2 (first sealing body) for resin-sealing the semiconductor chip 1 and a plurality of wires 3, a solder ball 10 which is a plurality of external terminals provided on the back surface 5b of the package substrate 5, and FIG. As shown in the figure, the heat spreader 7 is attached to the surface 2 b of the sealing body 2 via an adhesive 8. The semiconductor chip 1 has a quadrangular planar shape that intersects the thickness direction.

  Furthermore, the package substrate (wiring substrate) 5 has a square shape that intersects the thickness direction in the present embodiment, and the planar shape of the sealing body 2 formed on the main surface 5a of the package substrate 5 is: It is a square shape. As shown in FIG. 1 and FIG. 3, there are resin cut portions on the outer sides of one of two opposing directions of the sealing body 2, and the semiconductor chip 1 is mounted on the sealing body 2. A resin thin film portion 2a (second sealing body) thinner than the thickness of the region to be formed is formed. As shown in FIG. 3, the resin thin film portion 2 a is formed integrally with the sealing body 2. That is, the sealing body 2 and the resin thin film portion 2a are integrally formed by filling the cavity 12b of the resin molding die 12 with the sealing resin 11 shown in FIG. The resin thin film portion 2a has a thickness of about 70 μm, for example.

  As shown in FIG. 4, the plurality of solder balls 10 that are external terminals are arranged in a grid pattern on the outer peripheral portion of the back surface 5 b of the package substrate 5 excluding the central portion.

  The BGA 4 is a relatively large multi-pin semiconductor package. For example, the BGA 4 has a package size of 33 mm × 33 mm and is 520 pins. However, these numerical values are not limited.

  In addition, the heat spreader 7 attached to the surface 2b of the sealing body 2 improves the heat dissipation effect of the BGA 4, but suppresses package warpage during high temperature processing such as reflow when the BGA 4 is mounted on the substrate. Is also possible.

  The package substrate 5 incorporated in the BGA 4 is made of a base material such as glass epoxy resin, for example, and has a multilayer wiring structure. Further, as shown in FIG. 3, the main surface 5a of the package substrate 5 is provided with a plurality of bonding electrodes 5e connected to the wires 3, while the back surface 5b has solder balls 10 as shown in FIG. Are provided with a plurality of lands 5h.

  Further, the main wiring (metal wiring) 5c, the bonding electrode 5e and the land 5h provided on the package substrate 5 are subjected to electrolytic plating. Therefore, as described in the above problem, the package substrate 5 has Is provided with a feed line 5d which is a metal wiring exposed at the outer peripheral end.

  Since the BGA 4 is a large semiconductor package, the wiring board (multiple substrate 9 shown in FIG. 6) used in the assembly becomes a large thin plate member (substrate, wiring board). At this time, the planar shape of the thin plate member intersecting with the thickness direction is rectangular. Therefore, one device region (device forming region) 9c on the multi-piece substrate 9 is covered with one cavity 12b of the resin mold 12 and assembled by adopting an individual molding method in which resin sealing is performed. Yes, this reduces the warpage in the individual device regions 9c, that is, the package substrate 5, and in the case of individualization after resin sealing, individualization is performed by dicing using a rotating blade 13. The cost burden can be reduced with a lower capital investment compared to the case of dividing into pieces by a cutting die.

  Since resin sealing is performed by an individual molding method and individualization is performed by dicing, the dicing BGA 4 has a cut surface of the power supply line 5d on the side surface of the package substrate 5 as shown in FIG. Exposed.

  The main wiring 5c, the power supply line 5d, the bonding electrode 5e, and the land 5h in the package substrate 5 are made of, for example, a copper alloy, and each surface excluding the cut surface is subjected to electrolytic plating. The main wiring 5c and the power supply line 5d are also copper wirings or copper leads (conductor leads).

  Further, regions other than the exposed bonding electrodes 5e and lands 5h on the front and back surfaces of the package substrate 5 are covered with a solder resist 5g which is an insulating film.

  Further, as shown in FIG. 1, in the BGA 4, an index 5f indicating the direction of the BGA 4 is formed in the vicinity of the corner of the main surface 5a of the package substrate 5. Further, the gate Au plating is provided as the gate metal portion 5i. Is given.

  The sealing resin 11 forming the sealing body 2 and the resin thin film portion 2a in the BGA 4 is, for example, a thermosetting epoxy resin mixed with a filler. The semiconductor chip 1 is made of, for example, silicon, and a plurality of pads 1c and semiconductor integrated circuits are formed on the main surface 1a. Furthermore, the wire 3 is a gold wire, for example.

  Next, the manufacturing method of BGA4 of this Embodiment is demonstrated along the manufacturing process flowchart shown in FIG.

  First, the multi-piece substrate 9 shown in FIGS. 6 and 7 is prepared. As shown in FIG. 6, a multi-device substrate 9 is formed with device regions 9c, which are a plurality of device formation regions, arranged side by side along the substrate longitudinal direction 9e, and each device region 9c has a substrate longitudinal direction. On both sides of 9e, slits 9d are formed along the device region 9c in a direction substantially perpendicular to the substrate longitudinal direction 9e.

  Further, each device region 9c is formed with a plurality of metal wires such as a main wire 5c and a feeder wire 5d made of a copper alloy, and electrodes such as bonding electrodes 5e and lands 5h. Is electroplated. Therefore, as shown in FIGS. 14 and 15, each power supply line 5d is arranged from the inner side toward the outer side across the dicing line 9g. Furthermore, as shown in FIG. 6, each device region 9c of the main surface 9a of the multi-chip substrate 9 is provided with a chip mounting area 9h at the center, and a plurality of chip mounting areas 9h are provided around each chip mounting area 9h. The bonding electrode 5e is formed.

  Further, at the corner of each device region 9c of the main surface 9a of the multi-cavity substrate 9, a gate corresponding to the gate 12c of the upper mold 12a of the resin molding die 12 shown in FIG. Au plating is applied. The gate metal portion 5i is for facilitating peeling of the gate resin remaining on the substrate.

  Further, as shown in FIG. 7, in each device region 9c on the back surface 9b of the multi-chip substrate 9, a plurality of lands 5h are provided in a grid pattern except for the central portion. Further, a plurality of positioning holes 9 f are formed at both ends in the width direction of the multi-piece substrate 9.

  Thereafter, die bonding in step S1 shown in FIG. 5 is performed. That is, the package substrate 5 of the multi-chip substrate 9 and the semiconductor chip 1 are connected. Here, the semiconductor chip 1 is fixed to the chip mounting area 9h of each device region 9c shown in FIG. Thereby, the back surface 1 b of the semiconductor chip 1 and the multi-chip substrate 9 are connected via the die bond agent 6.

  After die bonding, wire bonding shown in step S2 is performed. That is, as shown in FIG. 3, the pads 1 c of the semiconductor chip 1 and the bonding electrodes 5 e of the package substrate 5 corresponding thereto are connected by the wires 3 to electrically connect the semiconductor chip 1 and the package substrate 5.

  After wire bonding, resin molding shown in step S3 is performed. Since the BGA 4 is a large semiconductor package, the multi-chip substrate 9 shown in FIG. 6 used in the assembly is a large thin plate member. Therefore, as described in the above problem, individual molding for performing resin sealing by covering one device region (device forming region) 9c on the multi-piece substrate 9 with one cavity 12b of the resin molding die 12. By assembling by adopting the method, it is possible to reduce the warpage of each device region 9c, that is, the package substrate 5. Furthermore, when individualizing after resin sealing, by dividing into individual pieces by dicing, the cost burden can be reduced with a lower capital investment compared to performing individualization with a cutting die. be able to.

  Accordingly, the upper mold 12a of the resin molding die 12 for individual molding has a one-to-one correspondence with each device region 9c of the multi-piece substrate 9, and a plurality of cavities 12b are individually provided as shown in FIG. Individually formed. Further, in two sides of the side of the gate 12c of each cavity 12b and the side opposite to the side, a recess 12d for forming the resin thin film portion 2a shown in FIG. 5 is formed outside the side of the cavity 12b. As shown in FIG. 10, it is formed so as to communicate with the cavity 12b. The depth of the recess 12d formed in the direction from the lower mold 12e to the upper mold 12a is, for example, about 70 μm.

  Further, a cavity block 12g having a cavity 12b and a cull block 12h having a cull 12i are disposed on the upper mold 12a, and a runner 12j serving as a flow path from the cull 12i to the cavity 12b is formed.

  Individual molding is performed using such a resin molding die 12 having an upper die 12a and a lower die 12e. First, as shown in FIG. 11, the multi-chip substrate 9 having been wire-bonded is disposed on the mold surface 12f of the lower mold 12e. Thereafter, as shown in FIG. 12, the upper mold 12a and the lower mold 12e are clamped to perform clamping, and in this state, the cavity 12b is filled with the sealing resin 11 through the gate 12c. The sealing resin 11 is, for example, a thermosetting epoxy resin mixed with a filler.

  The filling of the sealing resin 11 into the cavity 12b and the recess 12d is completed, and the resin thin film portion 2a is formed integrally with the sealing body 2 as shown in FIG. Thereafter, the sealing resin 11 is cured, and the mold is further opened to take out a large number of substrates 9 from the resin molding die 12.

  As shown in FIG. 14, each device region 9c of the multi-piece substrate 9 taken out from the resin molding die 12 is sealed only on the sealing body 2 and on the outer side and on the opposite two sides. A resin thin film portion 2 a having a thickness of about 70 μm is formed integrally with the stationary body 2.

  After resin molding, ball mounting is performed in step S4 shown in FIG. Here, as shown in FIG. 5, the solder balls 10 are attached to the plurality of lands 5h in each device region 9c on the back surface 9b of the multi-chip substrate 9 shown in FIG.

  Thereafter, dicing shown in step S5 is performed. That is, individualization is performed by dicing. At that time, first, as shown in FIG. 16, the multi-piece substrate 9 is arranged with the back surface 9b facing upward with the pressing rubber 15 interposed on the dicing jig. That is, the multi-piece substrate 9 is disposed on the dicing jig 14 via the pressing rubber 15 with the back surface 9b side to which the solder balls 10 are attached facing upward. More specifically, the surface 2b of the sealing body 2, the resin thin film portion 2a formed integrally with the sealing body 2 only on the two opposite sides on the outer side, and the surface 2b of the sealing body 2 Then, dicing is performed in a state where the side surface (taper) formed over the resin thin film portion 2 a is in contact with the pressing rubber 15. Accordingly, since the multi-piece substrate 9 can be fixed more reliably than the case where the multi-piece substrate 9 is brought into contact with the pressing rubber 15 and fixed only by the surface 2b of the sealing body 2, vibration generated in the multi-piece substrate 9 by dicing can be suppressed. .

  In this state, dicing is performed by using the blade 13 shown in FIG. 16 along the dicing line 9g shown in FIG. In the case of the multi-chip substrate 9 shown in FIG. 14, the blade 13 is diced along the device region 9c and in a direction perpendicular to the slit 9d. At that time, in the method of manufacturing the semiconductor device according to the present embodiment, as shown in FIGS. 14 and 15, the feeder line 5d is provided from the inner side to the outer side across the dicing line 9g. As shown in FIG. 17, since the resin thin film portion 2a formed integrally with the sealing body 2 is disposed at a location corresponding to the dicing line 9g outside the sealing body 2, the resin thin film that is a resin cutting portion The part 2a and the feeder 5d are cut together (simultaneously) by the blade 13.

  That is, the power supply line 5d and the sealing resin 11 forming the resin thin film portion 2a are cut together by the blade 13.

  As described above, in the manufacturing method of the semiconductor device according to the present embodiment, the resin thin film portion 2a that is a resin cutting portion and the power supply line (metal wiring) 5d are cut together when dicing into individual pieces. The sealing resin 11 that forms the resin thin film portion 2a causes a dressing action on the blade 13, and the sealing resin 11 cuts the copper burrs (metal burrs) that are dragged and entangled. The adhesion of copper burrs to 13, that is, clogging due to copper burrs can be suppressed.

  As a result, the occurrence of copper burrs on the cut surface of the package substrate (wiring substrate) 5 can be prevented, and therefore the occurrence of wiring short-circuit defects can be prevented and the reliability of the BGA (semiconductor device) 4 can be improved. be able to.

  Furthermore, since the occurrence of copper burrs on the cut surface of the package substrate 5 can be prevented, the removal work of the copper burrs after dicing can be abolished, and the efficiency of assembling the BGA 4 can be improved.

  In addition, when the resin is sealed by individual molding, the recess 12d formed in communication with the cavity 12b of the upper mold 12a also has an air vent function, and the sealing resin 11 is reliably filled in the recess 12d. Can be made. Accordingly, it is possible to prevent the resin burrs from dropping off in the conventional air vent.

  Thereby, dropping off of the resin burr can be suppressed, and mounting defects when the BGA 4 is mounted on the mounting substrate can be reduced.

  After completion of the dicing, the heat spreader is applied as shown in step S6 of FIG. In other words, the heat spreader 7 is fixed to the surface 2b of the sealing body 2 in the separated BGA 4 by the adhesive 8, whereby the assembly of the BGA 4 is completed. Note that the heat spreader 7 is not necessarily attached.

  Next, a modification of the present embodiment will be described.

  The manufacturing method of the semiconductor device of the modification shown in FIG. 18 is not the resin thin film portion 2a as shown in FIG. 17 on the outside of the sealing body 2 as a resin cutting portion that is cut along with the metal wiring. And a second resin cutting portion (resin cutting portion) 2c having the same thickness as that of the sealing body 2 is formed, and the second resin cutting portion 2c and the power supply line are separated during dicing. 5d is cut together.

  As a result, during dicing, the sealing resin 11 (see FIG. 12) forming the second resin cutting portion 2c causes a dressing action on the blade 13 and seals the copper burrs that are dragged and entangled. The stopping resin 11 can be cut and adhesion of copper burrs to the blade 13, that is, clogging due to copper burrs can be suppressed.

  As a result, the occurrence of copper burrs on the cut surface of the package substrate 5 can be prevented, and the occurrence of wiring short-circuit defects can be prevented, thereby improving the reliability of the semiconductor device.

  However, as shown in FIG. 18, when the second resin cutting portion 2c having the same thickness as the sealing body 2 is formed, the sealing body 2 cut by dicing rather than the resin thin film portion 2a as shown in FIG. Since the amount increases, the life of the blade 13 is reduced. Furthermore, as described in the above problem, since the amount of resin in the second resin cutting portion 2c is larger than that in the resin thin film portion 2a, the warping of the package substrate 5 becomes remarkable.

  Although the invention made by the present inventor has been specifically described based on the embodiments of the invention, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the case where the slit 9d is formed in the multi-cavity substrate 9 has been described, but the slit 9d is not necessarily formed. In that case, four resin cutting portions such as the resin thin film portion 2a are formed along each of the four sides of the device region 9c.

  In the above-described embodiment, the BGA 4 has been described as an example of the semiconductor device. However, any semiconductor device that employs an individual molding method and is assembled using a thin plate member such as a wiring board having metal wiring can be used. LGA (Land Grid Array) other than BGA may be used.

  Furthermore, the semiconductor device is not limited to a wiring board, and a thin film member such as a lead frame made of a copper alloy and a semiconductor device in which resin sealing is performed by an individual molding method, QFN as shown in the modification of FIG. (Quad Flat Non-leaded Package) 16 may be used.

  The QFN 16 is a semiconductor package assembled using a copper frame (thin plate member), and the semiconductor chip 1 is fixed to the tab 17 via the die bond agent 6. A plurality of copper leads (conductor leads) 18 are arranged on the peripheral edge of the back surface 2 d of the sealing body 2. In the assembly of the QFN 16, the sealing body 2 is formed by an individual molding method, and the resin thin film portion 2 a that is a resin cutting portion is formed outside the sealing body 2.

  Further, when dicing after resin sealing, the copper lead 18 and the resin thin film portion 2a are cut together, so that the sealing resin 11 forming the resin thin film portion 2a is formed on the blade 13 as in the case of the BGA 4. On the other hand, a dressing action can be caused to prevent the copper burrs from adhering to the blade 13. As a result, clogging of the blade 13 due to copper burrs can be suppressed and the occurrence of copper burrs on the cut surfaces of the copper leads 18 can be prevented. As a result, the occurrence of short-circuit defects between leads can be prevented and the QFN (semiconductor The reliability of the (device) 16 can be improved.

  Further, in a semiconductor device such as the BGA 4, the heat spreader 7 does not necessarily have to be attached.

  The present invention is suitable for an electronic device assembly and a semiconductor device manufacturing method.

It is a top view which shows an example of the structure of the semiconductor device of embodiment of this invention. FIG. 2 is a side view showing an example of the structure of the semiconductor device shown in FIG. 1. It is sectional drawing which shows an example of the structure of the semiconductor device shown in FIG. FIG. 2 is a back view showing an example of the structure of the semiconductor device shown in FIG. 1. It is a manufacturing process flowchart which shows an example of the assembly of the semiconductor device shown in FIG. It is a top view which shows an example of the structure of the wiring board used for the assembly of the semiconductor device shown in FIG. FIG. 7 is a back view showing an example of the structure of the back surface of the wiring board shown in FIG. 6. It is a top view which shows an example of the structure of the upper mold | type of the resin molding die used at the resin sealing process of the assembly of the semiconductor device shown in FIG. It is sectional drawing which shows an example of the structure of the resin molding die cut | disconnected along the AA line shown in FIG. It is sectional drawing which shows an example of the structure of the resin molding die cut | disconnected along the BB line shown in FIG. It is a fragmentary sectional view which shows an example of the structure before metal mold | die clamp in the resin sealing process of the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure at the time of resin filling in the resin sealing process of the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure at the time of the mold opening in the resin sealing process of the assembly of the semiconductor device shown in FIG. FIG. 2 is a partial plan view showing an example of a structure of a substrate after resin sealing in assembling the semiconductor device shown in FIG. 1. FIG. 15 is a partial back view showing the structure of the substrate shown in FIG. 14. It is sectional drawing which shows an example of the structure at the time of dicing in the isolation | separation process of the assembly of the semiconductor device shown in FIG. It is an expanded partial sectional view which shows the structure of the C section shown in FIG. It is an expanded partial sectional view which shows the structure at the time of dicing in the isolation | separation process of the assembly of the semiconductor device of the modification of embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a Main surface 1b Back surface 1c Pad (electrode)
2 Sealing body 2a Resin thin film part (resin cutting part)
2b Surface 2c Second resin cutting part (resin cutting part)
2d Back side 3 Wire 4 BGA (Semiconductor device)
5 Package board (wiring board)
5a main surface 5b back surface 5c main wiring (metal wiring)
5d Feed line (metal wiring)
5e Bonding electrode (electrode)
5f Index 5g Solder resist 5h Land 5i Gate metal part 6 Die bond agent 7 Heat spreader 8 Adhesive 9 Multi-cavity substrate (wiring substrate)
9a Main surface 9b Back surface 9c Device region (device formation region)
9d slit 9e substrate longitudinal direction 9f positioning hole 9g dicing line 9h chip mounting area 10 solder ball 11 sealing resin 12 resin molding die 12a upper die 12b cavity 12c gate 12d recess 12e lower die 12f die surface 12g cavity block 12h Block 12i Cal 12j Runner 13 Blade 14 Dicing jig 15 Holding rubber 16 QFN (Semiconductor device)
17 Tab 18 Copper lead (conductor lead)

Claims (8)

A method for manufacturing a semiconductor device comprising the following steps:
(A) a base material, a plurality of device forming regions formed on the main surface of the base material, a cutting portion located outside each of the plurality of device forming regions, and the straddle across the cutting portion A feeder line formed from the inside to the outside of each of the plurality of device formation regions, a plurality of bonding electrodes formed on the main surface of the base material, and each of the plurality of bonding electrodes exposed. The first insulating film formed on the main surface of the base material including the plurality of device forming regions and the cutting portion, and the plurality of lands formed on the back surface opposite to the main surface of the base material And a step of preparing a wiring board having a second insulating film formed on the back surface of the base so that each of the plurality of lands is exposed;
(B) After the step (a), mounting a semiconductor chip having a surface on which a plurality of pads are formed in each of the plurality of device formation regions of the wiring board;
(C) a step of electrically connecting the plurality of bonding electrodes formed in each of the plurality of device formation regions and the plurality of pads of the semiconductor chip, respectively, after the step (b);
(D) After the step (c), the step of sealing the semiconductor chip mounted in each of the plurality of device formation regions with a resin to form a sealing body;
(E) a step of forming solder balls on each of the plurality of lands of the wiring board after the step (d);
(F) After the step (e), a rotating blade is allowed to travel along the cutting portion of the wiring board to separate the plurality of device formation regions;
here,
In the step (d), one device forming region of the plurality of device forming regions is formed on the mold 1 so that the sealing bodies formed in each of the plurality of device forming regions are not connected to each other. Performed with two cavities covered,
The sealing body formed in the step (d) includes the first sealing body formed in each of the plurality of device formation regions, and the first sealing body formed in the cutting portion and integrally formed. A resin thin film portion thinner than the thickness of the sealing body,
In the step (f), in a state where the surface of the first sealing body and the surface of the resin thin film portion are fixed, the blade is inserted from the back surface side of the wiring board, and the resin thin film portion and the power supply line Are cut together by the blade. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the feeder line is made of a copper wiring. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the surface of each of the plurality of bonding electrodes and the surface of each of the plurality of lands are subjected to electrolytic plating. In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), the plurality of bonding electrodes and the plurality of pads of the semiconductor chip are electrically connected through a plurality of wires, respectively. In the manufacturing method of the semiconductor device according to claim 1,
The planar shape intersecting with the thickness of the wiring board is a rectangle,
The method of manufacturing a semiconductor device, wherein the plurality of device formation regions are formed side by side along a longitudinal direction of the wiring board. In the manufacturing method of the semiconductor device according to claim 5,
A method of manufacturing a semiconductor device, wherein slits are formed along a longitudinal direction of the wiring board and on both sides of the device formation region. In the manufacturing method of the semiconductor device according to claim 5,
A sealing device formed in the cut portion is formed along a short direction of the wiring board and on both sides of the device formation region. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the substrate is made of glass epoxy resin.

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