JPH07249707A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH07249707A JPH07249707A JP3744794A JP3744794A JPH07249707A JP H07249707 A JPH07249707 A JP H07249707A JP 3744794 A JP3744794 A JP 3744794A JP 3744794 A JP3744794 A JP 3744794A JP H07249707 A JPH07249707 A JP H07249707A
- Authority
- JP
- Japan
- Prior art keywords
- package
- outer lead
- substrate
- protector
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置のパッケー
ジの構造に関する。半導体装置は、近年、小型軽量化お
よび高機能化が要求されており、新しい用途に合わせて
新パッケージが開発され、外リード端子のファインピッ
チ化が進んでいる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package structure. In recent years, semiconductor devices have been required to be smaller and lighter and have higher functions, new packages have been developed according to new applications, and finer pitches of outer lead terminals have been advanced.
【０００２】[0002]
【従来の技術】図３は従来例の説明図である。図におい
て、１はパッケージ、２は基板、３は外リード端子、４
はプロテクタ、５はインナーリード、６はダム、７はチ
ップ、８はパッド、９はワイヤ、10はモールド樹脂、11
はスルーホールである。2. Description of the Related Art FIG. 3 is an explanatory view of a conventional example. In the figure, 1 is a package, 2 is a substrate, 3 is an outer lead terminal, 4
Are protectors, 5 inner leads, 6 dams, 7 chips, 8 pads, 9 wires, 10 mold resin, 11
Is a through hole.
【０００３】一般的にＰＣＬＰ(Printed Circuit Board
Leadless Chip Carrier) 等のパッケージは、図３
（ａ）に示すように、パッケージ用基板材の個々に切り
離した場合の角型のパッケージ用基板２の四辺に相当す
る部分に開口したスルーホール11に、図３（ｂ）に示す
ように、外リード端子３用のめっきを行い、このスルー
ホール11の中心を金型により縦に切断して、図３（ｃ）
〜（ｄ）に示すような個々のＰＣＬＰのパッケージ１の
基板２に分離する。Generally, a PCLP (Printed Circuit Board)
For packages such as Leadless Chip Carrier), see Figure 3.
As shown in FIG. 3A, in the through holes 11 opened in the portions corresponding to the four sides of the rectangular package substrate 2 when the package substrate material is individually cut, as shown in FIG. Plating for the outer lead terminals 3 is performed, and the center of the through hole 11 is vertically cut by a die, and then the result shown in FIG.
The individual PCLP packages 1 are separated into the substrates 2 as shown in FIGS.
【０００４】図３（ｃ）は基板２の裏面から見た背面図
であり、図３（ｄ）は図３（ｃ）の基板のＡ−Ａ’ライ
ンでカットした断面図を示す。この基板２上にＩＣ等の
チップ７を蝋材で固着し、チップ７上のAl等のパッド８
と、外リード端子３と連なる基板２上のインナーリード
５を金のワイヤ９等でボンディング接続する。その後、
基板２上のダム６の内側にモールド樹脂10を充填し、焼
結してＰＣＬＰの半導体製品が完成する。FIG. 3C is a rear view of the substrate 2 viewed from the back side, and FIG. 3D is a sectional view taken along the line AA 'of the substrate of FIG. 3C. A chip 7 such as an IC is fixed on the substrate 2 with a wax material, and a pad 8 such as Al on the chip 7 is attached.
Then, the inner lead 5 on the substrate 2 connected to the outer lead terminal 3 is connected by bonding with a gold wire 9 or the like. afterwards,
Mold resin 10 is filled inside the dam 6 on the substrate 2 and sintered to complete a PCLP semiconductor product.
【０００５】このパッケージ基板材より個々のパッケー
ジ用基板２に分離する際に、スルーホール11内のめっき
の外リード端子３を縦に半分づつに切断して、個々の基
板２に切り出すが、切断時に外リード端子３の厚さが基
板２の裏面より厚いために、テコの原理によって外リー
ド端子３が基板２の裏面より剥離するなどの問題があっ
た。When the package substrate material is separated into individual package substrates 2, the plated outer lead terminals 3 in the through-holes 11 are vertically cut into halves and cut into individual substrates 2. Since the thickness of the outer lead terminals 3 is sometimes thicker than the back surface of the substrate 2, there is a problem that the outer lead terminals 3 are separated from the back surface of the substrate 2 due to the principle of leverage.
【０００６】[0006]
【発明が解決しようとする課題】従って、パッケージの
製造工程およびそれ以降の組立・実装等の各工程で機械
的ストレスにより外リード端子がパッケージ裏面から剥
離したり、傷付いたりする場合がある。Therefore, the outer lead terminals may be peeled off or damaged from the back surface of the package due to mechanical stress in the manufacturing process of the package and subsequent steps such as assembly and mounting.
【０００７】また、プリント配線基板上への直接実装
（表面実装）をペースト状の半田にて行う場合、半田リ
フロー前の搭載時に、約70〜130 μｍの厚さに印刷した
ペースト状半田を押し潰して、近接する外リード端子間
の短絡や、或いは接合不十分等の障害に繋がる。Further, when the paste-like solder is directly mounted on the printed wiring board (surface-mounting), the paste-like solder printed to a thickness of about 70 to 130 μm is pressed at the time of mounting before solder reflow. Otherwise, it may lead to a short circuit between adjacent outer lead terminals, or a failure such as insufficient bonding.
【０００８】本発明は、以上の点を鑑み、外リード端子
の機械的ストレスによるパッケージの基板裏面からの剥
離、並びに傷の発生を未然に防止して、プリント基板へ
の半導体装置のＰＣＬＰ等のパッケージのはんだ付けに
よる表面実装時のファインピッチ外リード端子の実装は
んだを保護することを目的として提供されるものであ
る。In view of the above points, the present invention prevents the peeling of the package from the back surface of the substrate and the occurrence of scratches due to the mechanical stress of the outer lead terminals, and prevents the PCLP of the semiconductor device on the printed circuit board. It is provided for the purpose of protecting the mounting solder of the fine pitch outer lead terminals during surface mounting by soldering the package.
【０００９】[0009]
【課題を解決するための手段】図１、図２は本発明の原
理説明図兼本発明の第１、第２の実施例の説明図であ
る。1 and 2 are explanatory views of the principle of the present invention and explanatory drawings of the first and second embodiments of the present invention.
【００１０】図において、１はパッケージ、２は基板、
３は外リード端子、４はプロテクタ、４ａは枠状プロテ
クタ、４ｂは突起状プロテクタ、５はインナーリード、
６はダムである。In the figure, 1 is a package, 2 is a substrate,
3 is an outer lead terminal, 4 is a protector, 4a is a frame-shaped protector, 4b is a protruding protector, 5 is an inner lead,
6 is a dam.
【００１１】上記問題点の解決法として、パッケージ１
の外リード端子３の周囲に外リード端子３の厚さより厚
い保護用プロテクタ４をパッケージ用基板２の裏面の外
リード端子３近辺に設ける。As a solution to the above problems, the package 1
A protective protector 4 thicker than the thickness of the outer lead terminal 3 is provided around the outer lead terminal 3 in the vicinity of the outer lead terminal 3 on the back surface of the package substrate 2.
【００１２】即ち、本発明の目的は、パッケージ１の基
板２の裏面に、少なくとも外リード端子３の厚さより厚
い寸法を有するプロテクタ４を設けてなることにより、That is, the object of the present invention is to provide the protector 4 having a dimension at least larger than the thickness of the outer lead terminals 3 on the back surface of the substrate 2 of the package 1,
【００１３】[0013]
【作用】本発明では、パッケージの基板裏面の外リード
端子の周囲に保護用のプロテクタを設けることにより、
外リード端子の機械的ストレスによるパッケージ裏面か
らの剥離、並びに傷の発生を未然に防止し、また、表面
実装時のファインピッチ外リードの実装はんだを保護す
ることができる。In the present invention, by providing a protector around the outer lead terminals on the back surface of the package substrate,
It is possible to prevent the outer lead terminals from being peeled off from the back surface of the package due to mechanical stress and to be prevented from being scratched, and protect the mounting solder of the fine pitch outer leads during surface mounting.
【００１４】[0014]
【実施例】図１〜図２は本発明の第１および第２の実施
例の説明図である。図において、１はパッケージ、２は
基板、３は外リード端子、４はプロテクタ、４ａは枠状
プロテクタ、４ｂは突起状プロテクタ、５はインナーリ
ード、６はダムである。1 and 2 are explanatory views of the first and second embodiments of the present invention. In the figure, 1 is a package, 2 is a substrate, 3 is an outer lead terminal, 4 is a protector, 4a is a frame-shaped protector, 4b is a protruding protector, 5 is an inner lead, and 6 is a dam.
【００１５】パッケージにＰＣＬＰを用いた本発明の第
１の実施例について、図１により説明する。図１（ａ）
は基板２の裏面からみた背面図、図１（ｂ）は図１
（ａ）のＡ−Ａ’ラインでカットした断面図を示す。A first embodiment of the present invention in which PCLP is used for the package will be described with reference to FIG. Figure 1 (a)
1 is a rear view of the substrate 2 viewed from the back side, and FIG.
The sectional view cut | disconnected by the AA 'line of (a) is shown.
【００１６】最近は数百ピンのＰＣＬＰのパッケージ１
も登場しているが、図を簡単にするために、９２ピンの
パッケージを用いた。パッケージ用基板２の各辺に、め
っき製の２３本の外リード端子３が 280μｍ幅、120 μ
ｍ間隔、厚さ100 μｍで配列されている。四辺に配列さ
れた９２ピンの外リード端子３の基板２の裏面部分の内
側に 100μｍ離して、外リード端子３の厚さの倍の高さ
の厚さが200 μｍ、幅が200 μｍの枠状プロテクタ４ａ
を基板２の成形時に一体化して作製しておく。Recently, several hundred-pin PCLP package 1
, But a 92-pin package was used to simplify the figure. Twenty-three plated outer lead terminals 3 on each side of the package substrate 2 are 280 μm wide, 120 μm wide.
They are arranged at m intervals and a thickness of 100 μm. A frame with a thickness of 200 μm and a width of 200 μm, which is twice the thickness of the outer lead terminals 3, separated by 100 μm inside the rear surface of the substrate 2 of the 92-pin outer lead terminals 3 arranged on four sides. Shaped protector 4a
Are integrally formed when the substrate 2 is molded.
【００１７】こうしておけば、プラスチック用基板材を
個々の基板２に切り離す際に、基板２裏面の外リード端
子３が剥離することが防がれる。一方、基板２上にＩＣ
等のチップ７を固着し、チップ７上のパッド８と基板上
のくインナーリード５を金のワイヤ９等でワイヤボンデ
ィングし、モールド樹脂10で封止した後、外リード端子
３を半田付けしてプリント基板等に表面実装する際、こ
の枠状のプロテクタ４ａが防波堤となって半田が隣接し
た外リード端子３に流れて短絡する等の障害を防止する
効果もある。This prevents the outer lead terminals 3 on the back surface of the substrate 2 from peeling off when the plastic substrate material is cut into the individual substrates 2. On the other hand, IC on the substrate 2
Etc., the chip 7 is fixed, and the pad 8 on the chip 7 and the inner lead 5 on the substrate are wire-bonded with a gold wire 9 or the like, sealed with the mold resin 10, and then the outer lead terminals 3 are soldered. When it is surface-mounted on a printed circuit board or the like, the frame-shaped protector 4a also serves as a breakwater to prevent an obstacle such as a short circuit caused by the solder flowing to the adjacent outer lead terminals 3.
【００１８】更に、パッケージにＰＣＬＰを用いた本発
明の第２の実施例を図３により説明する。図３（ａ）に
背面図、図３（ｂ）に図３（ａ）のＢ−Ｂ’ラインでカ
ットした断面図で示すように、プロテクタ４の追加とし
て、基板２の裏面に配列された外リード端子３の配列群
の内側に枠状だけでなく、基板２の裏面の四隅に、例え
ば円盤状の突起状プロテクタ４ｂを設けることにより、
実装時のプリント基板に対する基板２の偏りをなくし、
プリント基板に平行に半田付け出来る効果を有すること
ができる。Further, a second embodiment of the present invention in which PCLP is used for the package will be described with reference to FIG. As shown in a rear view of FIG. 3A and a cross-sectional view of FIG. 3B taken along the line BB ′ of FIG. 3A, the protector 4 is additionally provided on the rear surface of the substrate 2. By providing not only a frame shape inside the array group of the outer lead terminals 3 but also, for example, disk-shaped projecting protectors 4b at the four corners of the back surface of the substrate 2,
Eliminating the bias of the board 2 with respect to the printed board when mounting,
It is possible to have the effect of being able to solder in parallel with the printed circuit board.
【００１９】上記の実施例はＰＣＬＰのパッケージにつ
いて説明したが、本発明はＰＣＬＰに限らず、パッケー
ジの基板の側面に外リード端子が形成され、外リード端
子の形状は異なっても、その側面で実装基板にはんだ付
けするタイプのパッケージ、すなわち、ＱＦＪ、ＳＯ
Ｊ、ＰＬＣＣ等のパッケージにもはんだの流れ防止や外
部リード端子保護のために適用出来るものである。Although the above embodiment describes the package of the PCLP, the present invention is not limited to the PCLP and the outer lead terminal is formed on the side surface of the substrate of the package, and even if the shape of the outer lead terminal is different, the side surface is different. The type of package that is soldered to the mounting board, that is, QFJ, SO
It can also be applied to packages such as J and PLCC to prevent solder flow and protect external lead terminals.
【００２０】[0020]
【発明の効果】以上説明したように、本発明によれば、
ＰＣＬＰ等のパッケージの外リード端子の周辺に、枠
状、または円板状、他の形状の外リード端子保護用のプ
ロテクタを設けることにより、外リード端子に対するパ
ッケージ製造工程での剥離の発生を未然に防ぎ、それ以
降の工程での機械的なストレスの発生並びに実装半田の
押しつぶし等を未然に防ぎ、表面実装時の品質安定化を
図ることができ、半導体装置の歩留り、品質、信頼性の
向上に寄与するところが大きい。As described above, according to the present invention,
By providing a frame-shaped, disk-shaped, or other shape protector for protecting the outer lead terminals around the outer lead terminals of the package such as PCLP, peeling may occur before the outer lead terminals in the package manufacturing process. To prevent mechanical stress in the subsequent process and crushing of mounting solder, and stabilize the quality during surface mounting, improving the yield, quality, and reliability of semiconductor devices. It greatly contributes to.
【図１】 本発明の第１の実施例の説明図FIG. 1 is an explanatory diagram of a first embodiment of the present invention.
【図２】 本発明の第２の実施例の説明図FIG. 2 is an explanatory diagram of a second embodiment of the present invention.
【図３】 従来例の説明図FIG. 3 is an explanatory diagram of a conventional example.
図において １ パッケージ ２ 基板 ３ 外リード端子 ４ プロテクタ ４ａ 枠状プロテクタ ４ｂ 突起状プロテクタ ５ インナーリード ６ ダム ７ チップ ８ パッド ９ ワイヤ 10 モールド樹脂 11 スルーホール In the figure, 1 package 2 substrate 3 outer lead terminal 4 protector 4a frame protector 4b protruding protector 5 inner lead 6 dam 7 chip 8 pad 9 wire 10 mold resin 11 through hole
Claims (1)
リード端子(3) を有し、且つ該リード端子(3) の側面で
実装基板にはんだ付けするタイプの該パッケージ(1) に
おいて、 該パッケージ(1) の基板(2) の裏面に少なくとも外部リ
ード端子(3) の厚さより厚い寸法を有するプロテクタ
(4) が設けられてなることを特徴とする半導体パッケー
ジ。1. A package (1) of the type having an external lead terminal (3) on a side surface of a substrate (2) of the package (1) and being soldered to a mounting board at a side surface of the lead terminal (3). The protector having a dimension at least thicker than the thickness of the external lead terminals (3) on the back surface of the substrate (2) of the package (1).
A semiconductor package comprising (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3744794A JPH07249707A (en) | 1994-03-09 | 1994-03-09 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3744794A JPH07249707A (en) | 1994-03-09 | 1994-03-09 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07249707A true JPH07249707A (en) | 1995-09-26 |
Family
ID=12497763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3744794A Withdrawn JPH07249707A (en) | 1994-03-09 | 1994-03-09 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07249707A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10242386A (en) * | 1996-02-23 | 1998-09-11 | Denso Corp | Surface-mount-type semiconductor package, transducer assembly, and surface-mount-type unit |
| KR100370842B1 (en) * | 1995-12-30 | 2003-06-19 | 앰코 테크놀로지 코리아 주식회사 | Chip size package |
| KR100381836B1 (en) * | 1996-12-13 | 2003-07-18 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| US10607906B2 (en) | 2017-06-05 | 2020-03-31 | Fuji Electric Co., Ltd. | Semiconductor package, semiconductor device and semiconductor device manufacturing method |
-
1994
- 1994-03-09 JP JP3744794A patent/JPH07249707A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100370842B1 (en) * | 1995-12-30 | 2003-06-19 | 앰코 테크놀로지 코리아 주식회사 | Chip size package |
| JPH10242386A (en) * | 1996-02-23 | 1998-09-11 | Denso Corp | Surface-mount-type semiconductor package, transducer assembly, and surface-mount-type unit |
| KR100381836B1 (en) * | 1996-12-13 | 2003-07-18 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| US10607906B2 (en) | 2017-06-05 | 2020-03-31 | Fuji Electric Co., Ltd. | Semiconductor package, semiconductor device and semiconductor device manufacturing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010605 |