CN103165560B - Substrate and apply its semiconductor structure - Google Patents
Substrate and apply its semiconductor structure Download PDFInfo
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- CN103165560B CN103165560B CN201310048035.8A CN201310048035A CN103165560B CN 103165560 B CN103165560 B CN 103165560B CN 201310048035 A CN201310048035 A CN 201310048035A CN 103165560 B CN103165560 B CN 103165560B
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- cabling
- bar
- substrate
- depressed part
- pad portion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A kind of substrate and apply its semiconductor structure.Substrate includes base material, plating line, m bar cabling and depressed part.Base material has encapsulation unit district.Plating line is arranged adjacent to the edge in encapsulation unit district.M bar cabling is formed in these a little encapsulation unit districts, and the n bar cabling in m bar cabling extends to plating line, wherein the m positive integer equal to or more than 2, and n is selected from a wherein numerical value of 1 to (m 1).Depressed part cuts off m bar cabling, to electrically isolate this little cablings.
Description
Technical field
The invention relates to a kind of substrate and apply its semiconductor structure, and in particular to one not
All cablings are all connected to the substrate of plating line and apply its semiconductor structure.
Background technology
Tradition strip substrate would generally electroplate a cushion layer before unification on cabling, cuts the most again.
But, after cutting, all of cabling all remains one as the line segment of plate bonding, and this remains line segment and causes
Line signal loss increases.
Summary of the invention
The present invention is related to a kind of substrate and applies its semiconductor structure, can improve asking of line signal loss
Topic.
According to one embodiment of the invention, propose a kind of substrate and apply its semiconductor structure.Substrate includes a base
Material, a plating line, m bar cabling and a depressed part.Base material has an encapsulation unit district.The neighbouring encapsulation of plating line
The edge of cellular zone is arranged.M bar cabling is formed at the n bar cabling in these a little encapsulation unit districts, in m bar cabling
Extending to plating line, wherein m is the positive integer equal to or more than 2, and n is selected from 1 to (m-1) wherein
One numerical value.Depressed part electrically isolates m bar cabling.
According to another embodiment of the present invention, propose a kind of substrate and apply its semiconductor structure.Semiconductor structure
It is electrically connected with part including a substrate, a chip and one.Substrate includes a base material, m bar cabling and a depressed part.
Base material has an encapsulation unit district.M bar cabling is formed in these a little encapsulation unit districts, the n in m bar cabling
Bar cabling extends to plating line, wherein the m positive integer equal to or more than 2, and n is selected from 1 to (m-1)
A wherein numerical value.Depressed part electrically isolates m bar cabling.Chip is located on substrate.It is electrically connected with part electrically to connect
Connect chip and m bar cabling.
For the foregoing of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing, make in detail
Carefully it is described as follows:
Accompanying drawing explanation
Figure 1A illustrates the top view of the semiconductor structure according to one embodiment of the invention.
Figure 1B illustrates the Figure 1A sectional view along direction 1B-1B '.
Fig. 1 C illustrates the Figure 1A sectional view along direction 1C-1C '.
Fig. 1 D illustrates the Figure 1A sectional view along direction 1D-1D '.
Fig. 2 illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.
Fig. 3 illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.
Fig. 4 illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.
Fig. 5 A illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.
Fig. 5 B illustrates the sectional view in Fig. 5 A along direction 5B-5B '.
Fig. 6 illustrates the top view of the semiconductor structure according to another embodiment of the present invention.
Fig. 7 illustrates the signal testing figure of the semiconductor structure of Fig. 1.
Fig. 8 A to 8E illustrates the process drawing of the semiconductor structure according to one embodiment of the invention.
Main element symbol description:
100,200,300,400,500: semiconductor structure
110: substrate
110u, 111u, 112u: upper surface
111: base material
111b: lower surface
111s: side, edge
112: cabling group
112e: cabling extension
112p: connection pad portion
112t, 112t ': cabling
112v, 112v ': via
1121: walk line segment
113: depressed part
114: connecting line
115: plating line
120: chip
120R: chip setting area
120u: active surface
130: be electrically connected with part
140: packaging body
140R: encapsulation unit district
150: protective layer
150a: perforate
C1, C2: curve
Detailed description of the invention
Refer to Figure 1A, it illustrates the top view of the semiconductor structure according to one embodiment of the invention.Quasiconductor
Structure 100 includes substrate 110, chip 120, several electric connection part 130, packaging body 140 (Fig. 1 D)
And protective layer 150.
Substrate 110 includes base material 111 (Figure 1B), several cabling group 112 and several depressed part 113.Base
The material of material 111 can be selected from organic (organic) material, pottery (ceramic) material, silicon substrate or
Metal.Additionally, base material 111 can be single or multiple lift wiring substrate.
Base material 111 has side, edge 111s.Each cabling group 112 is formed on base material 111 and includes m
Bar cabling 112t.The quantity of the cabling group 112 of this example illustrates as a example by four, and it is respectively adjacent in chip
Four sides of 120；But, several cabling groups 112 also can be adjacent to the single side of chip 120.This
Outward, the quantity of cabling group 112 also can be fewer of more than four.
In each cabling group 112, quantity m of cabling 112t is the positive integer more than 2, and its higher limit regards real
Depending on the configuration on border, the embodiment of the present invention is not any limitation as.N bar in m bar cabling 112t extends to
Corresponding side, edge 111s, wherein n is selected from the 1 wherein numerical value arriving (m-1).It is to say, at least
Article one, but the cabling 112t of not all need to extend to side, the edge 111s of base material 111, therefore can reduce signal
Loss.When the cabling 112t being connected to side, edge 111s more lacks bar, and the loss of signal is the fewest.In this example, with
Cabling 112t ' extends to explanation as a example by the 111s of side, edge.Additionally, cabling 112t in each cabling group 112
Quantity can phase XOR identical.
Each cabling group 112 includes several via 112v, and it extends the upper surface 111u stretching base material 111
(Figure 1B) and between lower surface 111b (Figure 1B), to be electrically connected with multilayer line layer or the electricity of base material 111
Property connect base material 111 upper surface 111u and lower surface 111b.In these a little via 112v at least the two with
The distance of side, edge 111s can be identical or different, depending on the visual configuration in its position, and the embodiment of the present invention
It is not any limitation as.Cabling 112t ' is connected to via 112v ', and signal can be transmitted in chip via cabling 112t '
Between 120 and via 112v '.Line segment 1121 of walking between via 112v ' and side, edge 111s is electricity
Plate wire road, it there is no substantial circuit function.In this example, the cabling group 112 that via 112v ' is corresponding
All via 112v near the via of side, edge 111s, so, from via 112v ' with
The length walking line segment 1121 between the 111s of side, edge can shorten, and reduces the loss of signal.When walking line segment
The length of 1121 is the shortest, and the loss of signal is the fewest.
In each cabling group 112, single depressed part 113 is through all of cabling 112t, a little to electrically isolate this
Cabling 112t.For example, m bar cabling 112t respectively includes connection pad portion 112p and cabling extension 112e, respectively
Cabling extension 112e from corresponding connection pad portion 112p extend to depressed part 113 and with other cabling extension
112e electrically isolates via depressed part 113.Additionally, depressed part 113 can pass through laser, cutter or etching side
Formula is formed.
Refer to Figure 1B (not illustrating packaging body 140), it illustrates the Figure 1A sectional view along direction 1B-1B '.
Depressed part 113 from the upper surface 112u of cabling extension 112e via whole cabling extension 112e and base material
The segment thickness of 111, to completely cut through cabling extension 112e.Protective layer 150 (e.g. welding resisting layer) covers
Cabling 112t and there is at least one perforate 150a.In this example, the region of single perforate 150a corresponding to single walk
Line-group group 112, the most also can correspond to single cabling group 112 by multiple perforate 150a.Each m bar line 112t's
Connection pad portion 112p and cabling extension 112e exposes from perforate 150a, consequently, it is possible to forming depressed part 113
Formation process in, depressed part 113 can pass through perforate 150a through and cut off the cabling extension 112e that exposes.
Owing to connection pad portion 112p exposes from perforate 150a, electric connection part 130 (Fig. 1 D) can be made via perforate 150a
Connect connection pad portion 112p.
Refer to Fig. 1 C (not illustrating packaging body 140), it illustrates the Figure 1A sectional view along direction 1C-1C '.
The area of the perforate 150a of protective layer 150 distribution more than m bar cabling 112t, and expose m bar and walk
Line 112t, makes depressed part 113 be able to through and cut off all cabling extension 112e exposed.
Refer to Fig. 1 D, it illustrates the Figure 1A sectional view along direction 1D-1D '.Depressed part 113 is positioned at chip
Between 120 and side, the edge 111s of substrate 110.Chip 120 is located at its active surface 120u orientation upward
On substrate 110, and it is electrically connected on the connection pad portion 112p of cabling 112t through being electrically connected with part 130, this
In example, it is electrically connected with part 130 bonding wire.In another example, chip 120 can be flip (flip chip), its
It is located on the upper surface 110u of substrate 110 with its active surface 120u orientation down and electrical through at least one projection
It is connected to the connection pad portion 112p of cabling 112t.
In this example, cabling group 112 (Figure 1A) is formed at the upper surface 111u of base material 111, so another example
In also can be simultaneously formed at upper surface 111u and lower surface 111b.
Packaging body 140 is formed at the upper surface 110u of substrate 110 and coating chip 120 and is electrically connected with part 130.
Packaging body 140 can include phenolic group resin (Novolac-based resin), epoxy (epoxy-based
Resin), silicone (silicone-based resin) or other suitable coverings.Packaging body 140 also may be used
Silicon dioxide including suitable filler, e.g. powdery.Several encapsulation technologies can be utilized to form packaging body
140, e.g. compression forming (compression molding), injection moulding (injection molding)
Or tuberculosis molding (transfer molding).
Refer to Fig. 2, it illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.Half
Conductor structure 200 includes that substrate 110, chip 120, several electric connection part 130, packaging body 140 (are not painted
Show) and protective layer 150.Substrate 110 includes base material 111 (not being illustrated in Fig. 2), several cabling group 112
And depressed part 113.In this example, the perforate 150a of protective layer exposes at least two cabling groups 112.Respectively walk line-group
In group 112, quantity m of cabling 112t is more than 2, and n bar cabling 112t therein extends to the edge of correspondence
Side 111s, n are selected from the 1 wherein numerical value arriving (m-1).Remaining feature of each cabling group 112 in
Described above, holds this and repeats no more.Additionally, in each cabling group 112, depressed part 113 cut off all of walk
Line 112t, to electrically isolate this little cabling 112t.
Refer to Fig. 3, it illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.Half
Conductor structure 300 includes that substrate 110, chip 120 several electric connection part 130, packaging body 140 (are not painted
Show) and protective layer 150.Substrate 110 includes base material 111 (not being illustrated in Fig. 3), at least one cabling group
112, depressed part 113 and connecting line 114.Cabling group 112 includes several cablings 112t, and its cabling extends
Portion 112e connects connecting line 114 and connection pad portion 112p, and wherein depressed part 113 is through cabling extension 112e
And electrically isolate connection pad portion 112p and connecting line 114.According to this principle, depressed part 113 cut off all of walk
Line 112t, to electrically isolate this little cabling 112t.
Refer to Fig. 4, it illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.With
Unlike the structure of Fig. 3, the connecting line 114 of this example can be protected layer 150 and cover.
Refer to Fig. 5 A, it illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.
Semiconductor structure 400 includes substrate 110, chip 120, several electric connection part 130, packaging body 140 (not
Illustrate) and protective layer 150.Substrate 110 includes base material 111 (being illustrated in Fig. 5 B), at least one cabling group
112, depressed part 113 and several connecting lines 114, each connecting line 114 extends from corresponding cabling group 112
To depressed part 113.
Refer to Fig. 5 B, it illustrates in Fig. 5 A the sectional view along direction 5B-5B '.Two connecting lines 114 are respectively
From adjacent two connection pad portion 112p to extending to therebetween depressed part 113 to ground, make adjacent two connection pad portion 112p
Electrically isolate via therebetween depressed part 113.
Refer to Fig. 6, it illustrates the partial top view of the semiconductor structure according to another embodiment of the present invention.Half
Conductor structure 500 includes that substrate 110, chip 120, several electric connection part 130, packaging body 140 (are not painted
Show) and protective layer 150.Substrate 110 includes base material 111, single cabling group 112 and single depressed part 113,
Wherein cabling group 112 includes that several cablings 112 are around chip 120.Protective layer 150 has single perforate 150a
(such as the annular section of heavy line), it is around chip 120 and exposes all cablings 112, makes in formation single
During depressed part 113, depressed part 113 can pass through perforate 150a cut off all cablings 112, make all walk
Line 112 is electrically isolated from one another.In this example, ring-type depressed part 113 can single cut (such as single feed) or
Cutting (such as gradation feed) is formed by several times.Although the depressed part 113 of this example illustrates as a example by closed ring, so
In another example, depressed part 113 also can be by the open annular recess being made up of the sub-depressed part of several separation.
But, as long as depressed part 113 can cut off the electrical connection of all cabling 112t, the present invention implements
Example does not limit the design of depressed part 113.Other one is mentioned that, this example extend to side, edge 111s's
Cabling 112t ' can only have one, and the loss of signal is greatly reduced.
Refer to Fig. 7, it illustrates the signal testing figure of semiconductor structure of Fig. 1.Curve C1 represents this example
The loss of signal curve of the cabling 112t of semiconductor structure 100, and curve C2 represents in conventional semiconductor structure
All cablings extend to the loss of signal curve of side, edge 111s.Compared to curve C2, due to this example half
In conductor structure 100, also not all cabling 112t extends to side, edge 111s, and therefore its loss of signal is (bent
Line C1) reduce significantly.
Refer to Fig. 8 A to 8E, it illustrates the manufacture process of the semiconductor structure according to one embodiment of the invention
Figure.
As shown in Figure 8 A, it is provided that a substrate 110 '.Substrate 110 ' e.g. strip substrate, it includes base material
111, at least one cabling group 112, an at least connecting line 114 and at least one plating line 115.
Base material 111 has at least one encapsulation unit district 140R.In follow-up unification technique, can be single along encapsulation
The edge cuts of unit district 140R goes out at least semiconductor structure 100.Additionally, base material 111 has at least one core
Sheet setting area 120R, the chip 120 of follow-up setting can corresponding this chip setting area 120R configuration.
In each cabling group 112, quantity m of cabling 112t is more than 2, and n bar cabling 112t therein extends
To corresponding side, edge 111s, n selected from the 1 wherein numerical value arriving (m-1).It is to say, at least one
Bar but the cabling 112t of not all may extend into side, the edge 111s of base material 111, to be directly electrically connected at
Plating line 115.In this example, directly it is electrically connected at explanation as a example by plating line 115 by cabling 112t '.Additionally,
Cabling 112t, connecting line 114 and plating line 115 can in along with technique is formed in the lump, so this is not used to limit
The embodiment of the present invention processed.
Each connecting line 114 connect correspondence cabling group 112 in all of cabling 112t, make not with plating line
The 115 cabling 112t connected can be electrically connected at plating line 115 via connecting line 114 indirectly.
Plating line 115 is arranged adjacent to the edge of encapsulation unit district 140R, and extends adjacent two encapsulation unit districts
Between 140R.A plurality of plating line 115 is electrically connected to each other, and is electrically connected at an electroplated electrode (not illustrating).
Consequently, it is possible in subsequent electroplating process, all cabling 112t being directly or indirectly connected with plating line 115
All can pass through plating line 115 and be electrically connected at electroplated electrode, and then electrodepositable one cushion layer (not illustrating) is in walking
On the connection pad portion 112p of line 112t.The electric connection part 130 that this cushion layer contributes to being subsequently formed is engaged in
On pad portion 112p.
As shown in Figure 8 B, after the technique of plating cushion layer completes, e.g. laser, cutter, erosion can be used
Carving or other suitable material removes technology, formation depressed part 113 is through connecting line 114, to remove whole connection
Line 114, and cut off the electrical connection of all m bar cabling 112t.In this example, depressed part 113 can one
Secondary cutting is formed；The most also graded cutting is formed.
Then, e.g. deionized water can be used, clean depressed part 113, to remove produced by cutting process
Impurity.
As shown in Figure 8 C, can use e.g. surface paste technology (Surface Mounted Technology,
SMT), arrange at least one chip 120 on the upper surface 110u of substrate 110, at least a part of which one chip 120
It is located in the chip setting area 120R of correspondence.
In Fig. 8 C, wire bonds (wire-bonding) technology can be used, form at least one electric connection part
130, e.g. bonding wire, connect the connection pad of the active surface 120u of chip 120 and the cabling 112t of substrate 110
Portion 112p.
As in fig. 8d, e.g. compression forming, injection moulding or tuberculosis molding can be used, form packaging body
140 coating chips 120.
As illustrated in fig. 8e, unification step is performed, to form at least semiconductor structure 100.Such as, may be used
Using e.g. cutter or laser, the edge along encapsulation unit district 140R (8C figure) forms at least one cutting
Road P is through packaging body 140 and substrate 110, to form at least one semiconductor structure 100 as shown in figure ip.
The manufacture method of other semiconductor structure 200,300,400 and 500 is similar in appearance to semiconductor structure 100
Manufacture method, holds this and repeats no more.
In sum, although the present invention is disclosed above with embodiment, and so it is not limited to the present invention.This
Technical field that the present invention belongs to has usually intellectual, without departing from the spirit and scope of the present invention, when making
Various changes and retouching.Therefore, protection scope of the present invention is when being as the criterion depending on those as defined in claim.
Claims (11)
1. a substrate, it is characterised in that including:
One base material, has an encapsulation unit district；
One plating line, the edge in this encapsulation unit district neighbouring is arranged；
M bar cabling, is formed in this encapsulation unit district, and the n bar cabling in this m bar cabling extends to this plating
Line, wherein m is the positive integer equal to or more than 2, and n is selected from a wherein numerical value of 1 to (m-1)；And
One depressed part, electrically isolates this m bar cabling,
Wherein this m bar cabling respectively includes a connection pad portion and a cabling extension, and this substrate further includes a connecting line,
This cabling extension connects this connecting line and this connection pad portion, and this depressed part passes through this cabling extension to electrically isolate
This connection pad portion and this connecting line.
2. substrate as claimed in claim 1, it is characterised in that this depressed part is through respectively this m bar cabling and is somebody's turn to do
The segment thickness of base material.
3. substrate as claimed in claim 1, it is characterised in that further include:
One protective layer, covers this m bar cabling, and has a perforate；
Wherein, this connection pad portion and this depressed part expose from this perforate.
4. substrate as claimed in claim 1, it is characterised in that this cabling extension extends to from this connection pad portion
This depressed part.
5. substrate as claimed in claim 1, it is characterised in that this base material has a chip setting area, and this is recessed
Sunken portion is positioned between this chip setting area and this plating line.
6. substrate as claimed in claim 1, it is characterised in that further include:
Several cabling groups, respectively this cabling group includes this m bar cabling.
7. substrate as claimed in claim 1, it is characterised in that further include:
Several vias, respectively this m bar cabling is connected to the via of correspondence, wherein extends to being somebody's turn to do of this plating line
The via that the one of n bar cabling is connected is the via in those vias near this plating line.
8. a semiconductor structure, it is characterised in that including:
One substrate, including:
One base material, has a side, edge；
M bar cabling, is formed on this base material, and this cabling of n bar in this m bar cabling extends to being somebody's turn to do of correspondence
Side, edge, wherein m is the positive integer equal to or more than 2, and n is selected from a wherein numerical value of 1 to (m-1)；
And
One depressed part, electrically isolates this m bar cabling；
One chip, is located on this substrate；And
One is electrically connected with part, is electrically connected with this chip and this m bar cabling,
Wherein this m bar cabling respectively includes a connection pad portion and a cabling extension, and this substrate further includes a connecting line, and this is walked
Line extension connects this connecting line and this connection pad portion, and this depressed part connects to electrically isolate this through this cabling extension
Pad portion and this connecting line.
9. semiconductor structure as claimed in claim 8, it is characterised in that this depressed part is walked through respectively this m bar
Line and the segment thickness of this base material.
10. semiconductor structure as claimed in claim 9, it is characterised in that further include:
One protective layer, covers this m bar cabling, and has a perforate；
Wherein, respectively this m bar cabling includes a connection pad portion, and this connection pad portion and this depressed part expose from this perforate.
11. semiconductor structures as claimed in claim 8, it is characterised in that further include:
Several vias, respectively this m bar cabling is connected to the via of correspondence, wherein extends to this side, edge
The via that the one of this n bar cabling is connected is the via in those vias near this side, edge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310048035.8A CN103165560B (en) | 2013-02-06 | 2013-02-06 | Substrate and apply its semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310048035.8A CN103165560B (en) | 2013-02-06 | 2013-02-06 | Substrate and apply its semiconductor structure |
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| Publication Number | Publication Date |
|---|---|
| CN103165560A CN103165560A (en) | 2013-06-19 |
| CN103165560B true CN103165560B (en) | 2016-12-28 |
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| CN201310048035.8A Active CN103165560B (en) | 2013-02-06 | 2013-02-06 | Substrate and apply its semiconductor structure |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10879160B2 (en) * | 2018-02-01 | 2020-12-29 | SK Hynix Inc. | Semiconductor package with packaging substrate |
| CN111063619B (en) * | 2019-12-31 | 2021-12-24 | 中国电子科技集团公司第十三研究所 | Electroplating method |
| WO2021142746A1 (en) * | 2020-01-17 | 2021-07-22 | 深圳市德明利技术股份有限公司 | Lpddr substrate design method, lpddr substrate and electronic device |
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| CN103178034A (en) * | 2011-12-21 | 2013-06-26 | 矽品精密工业股份有限公司 | Package structure, package substrate structure and manufacturing method thereof |
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| TW412812B (en) * | 1999-02-03 | 2000-11-21 | Advanced Semiconductor Eng | Method for plating gold to bond leads on a semiconductor substrate |
| CN1567552A (en) * | 2003-06-30 | 2005-01-19 | 美龙翔微电子科技（深圳）有限公司 | Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure |
| TWI246380B (en) * | 2004-06-11 | 2005-12-21 | Advanced Semiconductor Eng | Fabrication method of a printed circuit board |
| CN103178034A (en) * | 2011-12-21 | 2013-06-26 | 矽品精密工业股份有限公司 | Package structure, package substrate structure and manufacturing method thereof |
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