CN1567552A - Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure - Google Patents
Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure Download PDFInfo
- Publication number
- CN1567552A CN1567552A CN 03139676 CN03139676A CN1567552A CN 1567552 A CN1567552 A CN 1567552A CN 03139676 CN03139676 CN 03139676 CN 03139676 A CN03139676 A CN 03139676A CN 1567552 A CN1567552 A CN 1567552A
- Authority
- CN
- China
- Prior art keywords
- lead wire
- electroplate lead
- wire
- electroplate
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The invention relates to a processing method of plating wire distribution of IC packing substrate, including: a. arranging plating wires between wire patterns in packing substrate units to make all the wires of the wire patterns connect mutually by plating wires, where the plating wires or wire patterns connect with metal power supply layers in packing substrates; b. making plating treatment on the packing substrates and eliminating the plating wires by chemically etching process. The invention public plating wires between wire patterns in the packing substrates units, where the plating public wires are thinner than the wire patterns and narrower than the narrowest wire pattern, and eliminates the public wires by etching process, can make the shape change of the wire patterns minimum by controlling etching process conditions, thus beneficial to the improvement of electric performance of the substrate, assuring the integrity of signals and able to reduce wiring area, especially applied to make high-frequency high-speed IC packing substrates.
Description
Technical field
The present invention relates to the semiconductor circuit package substrate manufacturing technology, specifically is that a kind of electroplate lead wire of integrated circuit (IC) substrate package is laid processing method, and the electroplate lead wire structure on the substrate.
Background technology
Along with the miniaturization and the thin typeization of integrated circuit development, the requirement of integrated circuit encapsulation is also improved thereupon, wherein to the requirement of base plate for packaging more towards gently, thin, short, little direction develops, to guarantee good electrical properties.For reaching above requirement, very high wiring density is essential, and wherein the structure of base plate for packaging outer-layer circuit electroplate lead wire has very big influence to the density of wiring and the electrical property after the encapsulation.
At present, printed semiconductor circuit package substrate is electroplated the following two kinds of methods of the common employing of method for arranging of public connecting line:
1. be drawn out to the conducting of public connecting line when realizing electroplating between the base plate for packaging unit by the lead that will independently need electroplate of wiring, base plate for packaging line construction example such as Fig. 1 of this method, wherein substrate (1) is the matrix bar that a plurality of base board units (2) are formed.Lay plating bus (3) between the base board unit (2), plating bus (3) is connected by the interior wire pattern (5) of electroplate lead wire (4) in the base board unit (2) and base board unit (2), thereby all wire patterns that need electroplate (5) all are connected with plating bus.Grid wire pattern (6) in the middle of the substrate also is connected with plating bus (3) by electroplate lead wire (4).Plating bus (3) extends to the substrate edges of boards always, and the electroplating clamp contact during plating on the electroplating device is communicated with the plating bus (3) of substrate edges of boards, finishes electroplating process.
2. the example of second kind of method for arranging such as Fig. 2, remove similar method in the employing and 1, between base board unit (7), lay the plating bus (8) that is communicated with electroplate lead wire (9) in the base board unit (7), thereby realize outside the conducting of inner intraphase conductor figure in unit (10) and plating bus (8), plating bus (11) in also in the base plate for packaging unit, arranging, interior plating bus is realized passing through electroplate lead wire (9) near the inner lead figure (12) at unit center position as the additional part of plating bus between the unit, the conducting of interior plating bus (11) and plating bus (8).
Above-mentioned two kinds of wiring methods are after realizing plating, all be by removing on the substrate mode of plating bus electroplate lead wire to be separated to each other, this mode is at residue electroplate lead wire (4) on corresponding diagram 1 base board unit that stays on the wire pattern of substrate shown in Fig. 3 a and the residue electroplate lead wire (9) on corresponding diagram 2 base board units shown in Fig. 3 b.The remaining electroplate lead wire situation of this kind influences the integrality of signal to the loss and the interference of the HW High Way formation signal on the base plate for packaging that is used for high frequency, high speed.Increase the difficulty of wiring simultaneously, even under the situation of high-density wiring very, can not realize arranging of electroplate lead wire.
Summary of the invention
The problems referred to above in view of the electroplate lead wire wiring technique existence that has integrated circuit (IC) substrate package now, the invention provides a kind of electroplate lead wire layout processing method of base plate for packaging and the electroplate lead wire structure on the substrate, by in base board unit, arranging electroplate lead wire, the mutual conducting of separate conductors when realizing electroplating, and keep electroplate lead wire to remove the shape of all signal conductors of back to greatest extent, complete with the transmission that guarantees signal, realize high-density wiring.
The electroplate lead wire of integrated circuit of the present invention (IC) base plate for packaging is laid processing method and is achieved in that it comprises:
Between a, the wire pattern in the base plate for packaging unit electroplate lead wire is set, all leads of wire pattern are communicated with each other by electroplate lead wire, the metal power layer in electroplate lead wire or wire pattern and the base plate for packaging is communicated with;
Wherein, some lead of electroplate lead wire or wire pattern is communicated with by the interior metal power layer of little via hole and base plate for packaging.
Electroplate lead wire also can be communicated with by the interior metal power layer of non-signal conductor figure such as power lead figure and substrate.
B, the wire pattern that needs on the base plate for packaging to electroplate carried out electroplating processes after, remove electroplate lead wire, the shape when making final holding wire keep designing to greatest extent by chemical etching process again.
Electroplate lead wire structure in a kind of integrated circuit (IC) substrate package unit, it is characterized in that comprising the integrated circuit (IC) substrate package unit, between base plate for packaging unit inside conductor figure, electroplate lead wire is set, each bar lead of wire pattern is connected to described electroplate lead wire nearby, and the bus plane in electroplate lead wire or wire pattern and the base plate for packaging bottom is communicated with.
The present invention lays electroplate lead wire between base plate for packaging unit inside conductor figure, to special pattern, as nation point surely, racket etc. is finished required plating, after the plating of nickel gold, remove the public lead portion of plating by etch process, the control etch process conditions can make the unit wire shape change of wire pattern reach minimum, helps the improvement of substrate electrical property, guarantee the complete of signal, and can reduce the area that connects up.
The present invention avoided the tradition of base plate for packaging electroplate cut off in the wiring of public lead-in wire electroplate public lead-in wire after, on the real wire pattern of substrate, stay the defective of a large amount of unnecessary public line segments, be specially adapted to make the base plate for packaging of high frequency, High Speed ICs.
Description of drawings
Fig. 1 is existing IC base plate for packaging plating bus and electroplate lead wire topology example;
Fig. 2 is existing another kind of IC base plate for packaging plating bus and electroplate lead wire topology example;
Fig. 3 is the line construction example after plating bus is removed in encapsulation illustrated in figures 1 and 2;
Fig. 4 is the structural representation of base plate for packaging of the present invention unit wire pattern and electroplate lead wire;
Fig. 5 (a) is the I partial enlarged drawing of electroplate lead wire in Fig. 4 base plate for packaging unit, (b) is electroplate lead wire and the little via hole of metallization junction M partial enlarged drawing, (c) be the little via hole of metallization place the A-A profile;
Fig. 6, Fig. 7 represent on the bus plane formation schematic diagram of the little via hole of metallization on the insulating medium layer and insulating medium layer;
Fig. 8-Figure 11 forms the electroplate lead wire structural representation of attenuate for adopting graphic plating;
Figure 12-Figure 16 forms the electroplate lead wire structural representation of attenuate for adopting pre-engraving method;
Figure 17 is for adopting the electroplate lead wire structural representation of narrow thin wire bar;
Figure 18 is the formation schematic diagram of solder mask;
Figure 19 windows at the protection schematic diagram of follow-up electroplating process for the solder mask of electroplate lead wire;
Other locality protection schematic diagram when Figure 20 is the electroplate lead wire etching;
Figure 21 a, b are the schematic diagram before and after the electroplate lead wire etching.
Embodiment
Further specify below in conjunction with accompanying drawing.
Fig. 4 uses base plate for packaging unit line structural representation of the present invention, Fig. 5 be the little via hole of partial enlarged drawing, electroplate lead wire and the metallization junction partial enlarged drawing of electroplate lead wire in Fig. 4 base plate for packaging unit and the via hole place that metallizes profile.Electroplate lead wire structure in the diagram integrated circuit (IC) substrate package unit, comprise IC base plate for packaging unit (13), electroplate lead wire (15) is set between base plate for packaging unit (13) inside conductor figure (14), each bar lead of wire pattern (14) is connected to described electroplate lead wire (15) nearby, and electroplate lead wire (15) passes the interior metal power layer (18) of insulating medium layer (17) and base plate for packaging by the little via hole of metallization (16) again and is communicated with.
Electroplate lead wire also can be communicated with by the interior metal power layer of non-signal conductor figure and substrate, and this non-signal conductor figure is a power lead figure etc.
The specific implementation process of electroplate lead wire of the present invention is as follows:
(1), with reference to Fig. 6, Fig. 7, on insulating medium layer on the bus plane and the insulating medium layer metallization little via hole formation be described as follows:
The interior a certain bus plane (see figure 7) of sandwich construction that bus plane (18) can utilize substrate base copper bus plane (see figure 6) or lamination growth method to form.Insulating medium layer on the bus plane (17) but can be the sensitization insulating resin of silk-screen, also can be the non-sensitization insulating resin of silk-screen.But for the sensitization insulating resin, using the little via hole of metallization (16) that connects electroplate lead wire (15) and bus plane (18) on it is to form by photoetching process (being mask, exposure, development); For non-sensitization insulating resin, the little via hole of the metallization on it (16) is the method formation by laser drilling.After insulating medium layer forms, form the plating formation that the very thin metal deposition layer (19) of one deck is convenient to follow-up circuit metal level at the dielectric laminar surface by the chemical metal deposition technology.
(2), in the formation of base plate for packaging unit (13) inside conductor figure (14) and electroplate lead wire (15)
Consider to reduce and follow-uply remove the lateral etch of the process of electroplate lead wire (15) wire pattern (14) with chemical etching, thereby reduce the deformation of wire pattern (15), the attenuate of the thickness of electroplate lead wire (15) must being tried one's best, or electroplate lead wire (15) need that the width of cut-off parts tries one's best little.
Electroplate lead wire of the present invention is the electroplate lead wire structure of attenuate, and its thickness is less than the thickness of wire pattern, or enough little of the width of electroplate lead wire, and the removal etch process of follow-up electroplate lead wire is not exerted an influence to wire pattern.
The method that realizes electroplate lead wire (15) structure of above attenuate has following two kinds:
A) method of graphic plating is with reference to Fig. 8-Figure 11, and the growth course of the circuit metal level before wire pattern (14) etching is carried out in two steps.At first be to grow required electroplate lead wire metal layer thickness (20) (see figure 8) by the electric plating of whole board method, the upper surface that needs electroplate lead wire (15) position of removing after by the figure transfer technology photosensitive resist film (21) being stayed then is electroplated onto required thickness (see figure 9) by the graphic plating technology with the wire pattern metal level (22) in zone outside the photosensitive resist film afterwards.To comprise the photosensitive resist film (21) that the wire pattern (14) of electroplate lead wire (15) transfers to by the figure transfer technology at last and go up (see figure 10), etch the wire pattern (14) (seeing Figure 11) that comprises electroplate lead wire (15) with etch process.
B) pre-etching method is with reference to Figure 12-Figure 16, and wire pattern metal level (22) growth course before wire pattern (14) etching is to electroplate in a step to finish, and promptly a step electric plating of whole board reaches required metal layer thickness (seeing Figure 12).By the figure transfer technology photosensitive resist film (21) is stayed zone (seeing Figure 13) except that electroplate lead wire (15) position that needs at last to remove then, utilize chemical etch technique that the metal level at photosensitive resist film (21) place of windowing is carried out attenuate afterwards and be etched to required electroplate lead wire metal layer thickness (20) (seeing Figure 14).The wire pattern (14) that will comprise electroplate lead wire (15) by the figure transfer technology is transferred to photosensitive resist film (21) and is gone up (seeing Figure 15) again, etches the wire pattern (14) (seeing Figure 16) that comprises electroplate lead wire (15) with etch process.
Realize that it is the hachure that meets technological ability by design on the etching mask version that electroplate lead wire needs the width of the cut-off parts little method of trying one's best, realize wire pattern (14) simultaneously by figure transfer photosensitive resist film and etch process then and be easy to the thin electroplate lead wire (15) (figure sees 17) of etching cut-out at last.
(3), the formation of solder mask
After the technical process in finishing (one) and (two), carry out the formation of solder mask (23).As shown in figure 18, solder mask (23) be by figure transfer (be silk-screen, exposure, develop) but will the formation of photosensitive solder resist resin to the base board unit face.Solder mask (23) forms the protective layer of circuit and exposes needs the opening of follow-up plating (24) on the wire pattern (14); and expose and be used for etching at last and cut off electroplate lead wire (15) and corresponding etching openings (25), so that in the removal (seeing Figure 18) of follow-up realization electroplate lead wire (15).
(4) follow-up electroplated metal layer
Be used for etching at last and cut off the etching openings (25) (seeing Figure 19) of electroplate lead wire (15) to need before follow-up plating is carried out in follow-up plating opening (24) zone carrying out solder mask photosensitive resist film (21) being covered by the figure transfer technology.Carry out follow-up plating to electroplating opening (24) then.
(5), the chemical etching of electroplate lead wire (15) is removed
By the figure transfer technology photosensitive resist film (21) is covered All Ranges (seeing Figure 20) except that the etching openings (25) of electroplate lead wire (15), then by chemical etching process just electroplate lead wire (15) etching remove.Time by the control chemical etching can remove electroplate lead wire (15) to reach, and keep the original-shape (seeing Figure 21) of wire pattern (14) to greatest extent fully to the controlling of the removal of electroplate lead wire (15).
Claims (9)
1, the electroplate lead wire of IC base plate for packaging is laid processing method, it is characterized in that comprising:
Between a, the wire pattern in the base plate for packaging unit electroplate lead wire is set, all leads of wire pattern are communicated with each other by electroplate lead wire, the metal power layer in electroplate lead wire or wire pattern and the base plate for packaging is communicated with;
B, base plate for packaging is carried out follow-up plating, remove electroplate lead wire by chemical etching process again.
2, lay processing method according to the electroplate lead wire of claim 1, it is characterized in that: some lead of electroplate lead wire or wire pattern is communicated with by the interior metal power layer of little via hole and base plate for packaging.
3, lay processing method according to the electroplate lead wire of claim 2, it is characterized in that: described micropore is made by the hole metallization method.
4, lay processing method according to the electroplate lead wire of claim 1, it is characterized in that: electroplate lead wire is communicated with by the interior metal power layer of non-signal conductor figure and substrate.
5, lay processing method according to the electroplate lead wire of claim 4, it is characterized in that: described non-signal conductor figure is the power lead figure.
6, lay processing method according to the electroplate lead wire of claim 1, it is characterized in that: described electroplate lead wire is the electroplate lead wire structure of attenuate, its thickness is less than the thickness of wire pattern, or enough little of the width of electroplate lead wire, the removal etch process of electroplate lead wire is not exerted an influence to the signal conductor figure.
7, lay processing method according to the electroplate lead wire of claim 6, it is characterized in that the electroplate lead wire structure-forming process of described attenuate is:
1), electric plating of whole board grows required electroplate lead wire metal layer thickness (20), need the upper surface at electroplate lead wire (15) position of removing after by figure transfer photosensitive resist film (21) being stayed, adopt the graphic plating technology that the wire pattern metal level (22) in zone outside the photosensitive resist film is electroplated onto required thickness;
2), will comprise on the photosensitive resist film (21) that the wire pattern (14) of electroplate lead wire (15) transfers to, etch the wire pattern (14) that comprises electroplate lead wire (15) with etch process by the figure transfer technology.
8, lay processing method according to the electroplate lead wire of claim 6, it is characterized in that the electroplate lead wire structure-forming process of described attenuate is:
1), a step electric plating of whole board forms required wire pattern metal level (22), adopt figure transfer that photosensitive resist film (21) is stayed the zone of removing electroplate lead wire (15) position that needs removal at last, the metal level at photosensitive resist film (21) place of windowing is carried out attenuate be etched to required electroplate lead wire metal layer thickness (20);
2), the wire pattern (14) that will comprise electroplate lead wire (15) by figure transfer transfers on the photosensitive resist film (21), etches the wire pattern (14) that comprises electroplate lead wire (15) with etch process.
9, the electroplate lead wire structure in a kind of integrated circuit (IC) substrate package unit, it is characterized in that: comprise the integrated circuit (IC) substrate package unit, between base plate for packaging unit inside conductor figure, electroplate lead wire is set, each bar lead of wire pattern is connected to described electroplate lead wire nearby, and the metal power layer in electroplate lead wire and the base plate for packaging is communicated with.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03139676 CN100505189C (en) | 2003-06-30 | 2003-06-30 | Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03139676 CN100505189C (en) | 2003-06-30 | 2003-06-30 | Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567552A true CN1567552A (en) | 2005-01-19 |
| CN100505189C CN100505189C (en) | 2009-06-24 |
Family
ID=34470662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03139676 Expired - Fee Related CN100505189C (en) | 2003-06-30 | 2003-06-30 | Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100505189C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427681A (en) * | 2011-12-05 | 2012-04-25 | 深圳市五株电路板有限公司 | Manufacturing method of goldfinger circuit board |
| CN103165560B (en) * | 2013-02-06 | 2016-12-28 | 日月光半导体制造股份有限公司 | Substrate and apply its semiconductor structure |
| CN108875250A (en) * | 2018-07-02 | 2018-11-23 | 广州美维电子有限公司 | A kind of ameliorative way, electronic equipment, the storage medium of electroplating mild alloy uniformity |
| CN113471165A (en) * | 2020-03-31 | 2021-10-01 | 深南电路股份有限公司 | Packaging substrate and packaging substrate motherboard |
-
2003
- 2003-06-30 CN CN 03139676 patent/CN100505189C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427681A (en) * | 2011-12-05 | 2012-04-25 | 深圳市五株电路板有限公司 | Manufacturing method of goldfinger circuit board |
| CN103165560B (en) * | 2013-02-06 | 2016-12-28 | 日月光半导体制造股份有限公司 | Substrate and apply its semiconductor structure |
| CN108875250A (en) * | 2018-07-02 | 2018-11-23 | 广州美维电子有限公司 | A kind of ameliorative way, electronic equipment, the storage medium of electroplating mild alloy uniformity |
| CN108875250B (en) * | 2018-07-02 | 2023-03-24 | 广州美维电子有限公司 | Method for improving uniformity of electroplated soft gold, electronic equipment and storage medium |
| CN113471165A (en) * | 2020-03-31 | 2021-10-01 | 深南电路股份有限公司 | Packaging substrate and packaging substrate motherboard |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100505189C (en) | 2009-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7365006B1 (en) | Semiconductor package and substrate having multi-level vias fabrication method | |
| CN1170465C (en) | Vias and method for making the same in organic board and chip carriers | |
| KR100271838B1 (en) | Planar redistribution structure and printed wiring device | |
| CN102111968B (en) | Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate | |
| CN101286454A (en) | Printed circuit board and producing method of encapsulation base of integrated circuit | |
| KR0157060B1 (en) | Mounting substrate | |
| CN107920415A (en) | Has circuit board of thick copper circuit and preparation method thereof | |
| CN1227725C (en) | Noise shielded multi-layer substrates and manufacture thereof | |
| US7045460B1 (en) | Method for fabricating a packaging substrate | |
| US3568312A (en) | Method of making printed circuit boards | |
| KR20050035161A (en) | Semiconductor component | |
| US6930044B1 (en) | Method for fabricating a packaging substrate | |
| EP1344435B1 (en) | Parallel plane substrate | |
| US6651324B1 (en) | Process for manufacture of printed circuit boards with thick copper power circuitry and thin copper signal circuitry on the same layer | |
| CN1567552A (en) | Method for handling electroplating lead layout of IC packaging base plate and electroplating lead structure | |
| US6740222B2 (en) | Method of manufacturing a printed wiring board having a discontinuous plating layer | |
| CN102149255B (en) | Forming method of multiple-lead through hole | |
| CN104105340A (en) | Package substrate via hole structure and manufacture method | |
| JP3914458B2 (en) | Method for manufacturing circuit board having heat sink | |
| CN1567551A (en) | Method for forming solid conductive via hole of integrated circuit packaging base plate | |
| JPH08204312A (en) | Manufacture of chip-on board substrate | |
| US20230298986A1 (en) | Package substrate and manufacturing method thereof | |
| KR101173316B1 (en) | Method for manufacturing printed circuit board and printed circuit board manufactured by the same | |
| CN1747629A (en) | Production of duoble-face printing circuit board | |
| CN211457534U (en) | Fine interlayer circuit structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090624 Termination date: 20200630 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |