JP2013042005A - 半導体装置、半導体装置の製造方法、及び、電子機器 - Google Patents
半導体装置、半導体装置の製造方法、及び、電子機器 Download PDFInfo
- Publication number
- JP2013042005A JP2013042005A JP2011178390A JP2011178390A JP2013042005A JP 2013042005 A JP2013042005 A JP 2013042005A JP 2011178390 A JP2011178390 A JP 2011178390A JP 2011178390 A JP2011178390 A JP 2011178390A JP 2013042005 A JP2013042005 A JP 2013042005A
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- Prior art keywords
- bump
- semiconductor device
- semiconductor
- solder
- stud bump
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 214
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 229910000679 solder Inorganic materials 0.000 claims abstract description 113
- 238000007747 plating Methods 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims description 80
- 230000008569 process Effects 0.000 claims description 38
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000007772 electroless plating Methods 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 55
- 239000011521 glass Substances 0.000 abstract description 32
- 229910045601 alloy Inorganic materials 0.000 abstract description 18
- 239000000956 alloy Substances 0.000 abstract description 18
- 239000010410 layer Substances 0.000 description 78
- 239000011347 resin Substances 0.000 description 36
- 229920005989 resin Polymers 0.000 description 36
- 238000002844 melting Methods 0.000 description 23
- 230000008018 melting Effects 0.000 description 23
- 238000003384 imaging method Methods 0.000 description 20
- 239000000463 material Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 14
- 230000003287 optical effect Effects 0.000 description 11
- 239000011241 protective layer Substances 0.000 description 10
- 230000004048 modification Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 229910000765 intermetallic Inorganic materials 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 238000003825 pressing Methods 0.000 description 4
- 229910016334 Bi—In Inorganic materials 0.000 description 3
- 229910020830 Sn-Bi Inorganic materials 0.000 description 3
- 229910007637 SnAg Inorganic materials 0.000 description 3
- 229910018728 Sn—Bi Inorganic materials 0.000 description 3
- 229910018956 Sn—In Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910005728 SnZn Inorganic materials 0.000 description 1
- 229910008599 TiW Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000006059 cover glass Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
【解決手段】半導体部材31と、半導体部材31上に形成されているCuスタッドバンプ41と、Cuスタッドバンプ41と電気的に接続するはんだバンプ44とを備える半導体装置30を構成する。半導体部材31は、受光面と同じ面にガラス基板32と接続される電極45が形成されている。そして、この電極上にフリップチップ接続用のCuスタッドバンプが形成されている。Cuスタッドバンプ41は、はんだバンプ44との接続面に合金層43が形成されている。また、Cuスタッドバンプ41ははんだバンプ44と接触していない表面にめっき層42を備える。
【選択図】図3
Description
Auスタッドバンプを、半導体チップのCu電極へ接続するフリップチップ接続技術(特許文献3)や、SnめっきされたCu電極へ接続するフリップチップ接続技術(特許文献4)がある。
また、Auスタッドバンプに替わる、Cuスタッドバンプが提案されている(特許文献5)。
また、本技術の半導体装置の製造方法は、半導体部材上にCuスタッドバンプを形成する工程と、Cuスタッドバンプをはんだバンプにフリップチップ接続する工程とを有する。
また、本技術の電子機器は、上記半導体装置と、半導体装置の出力信号を処理する信号処理回路とを備える。
なお、説明は以下の順序で行う。
1.半導体装置の概要
2.半導体装置の第1実施形態
3.第1実施形態の半導体装置の製造方法
4.半導体装置の第2実施形態
5.第2実施形態の半導体装置の製造方法
6.電子機器
半導体装置のフリップチップ接続の概要について説明する。
図1に、従来の一般的なAuスタッドバンプを用いたフリップチップ接続の構成を示す。図1Aは、接続前のAuスタッドバンプ11及びSnバンプ12の構成を示す図である。図1Bは、接続後のAuスタッドバンプ11及びSnバンプ12の構成を示す図である。
このとき、Auスタッドバンプ11とSnバンプ12との接続は、接続信頼性を高めるために、300℃以上で行う必要がある。
300℃以下の接続では、図1Bに示すように、AuのSnへの拡散により、接続部分にSnAu4合金等の強度の低い金属間化合物(Inter Metallic Compound:IMC)20が生成する。このため、クラック24等の発生により接続不良が低下し、信頼性の低下が懸念される。また、Snバンプ12にAuスタッドバンプ11が刺さった状態となるため、AuのSnへの拡散を防ぐことは困難である。このため、接続部分でのIMC20の発生を防ぐことが難しい。
上述のように、Auスタッドバンプ11とSnバンプ12とによるフリップチップ接続では、300℃以上の高温接続が必要とされ、接続信頼性の観点から低温接続が困難である。
しかし、Auスタッドバンプ21とInバンプ22とを用いた接続では、AuとInとの間の拡散係数が大きいため、AuIn合金の成長を制御することが難しい。この結果、図2Bに示すように、AuIn合金23の成長により、Inバンプの吸い上げが発生する。このため、Auスタッドバンプ21とInバンプ22とによるフリップチップ接続では、接続性を確保することが難しい。
[イメージセンサ:構成]
以下、半導体装置の第1実施形態について説明する。図3に第1実施形態の半導体装置の構成を表す断面図を示す。第1実施形態は、半導体装置としてイメージセンサの例を挙げて説明する。図3は、ガラス基板上に実装されたイメージセンサからなる半導体装置30の断面図である。
また、ガラス基板32は、ガラス基板上に形成されたフリップチップ接続用の電極47と、電極47上に形成されたアンダーバンプメタル(UBM)48と、UBM48上に形成された低融点はんだバンプ44とを備える。さらに、ガラス基板32上に形成された配線層34と、配線層を被覆する保護層49と、配線層34と接続された外部接続用の電極35と、外部接続用の電極35上に形成されたはんだボール36とを備える。
また、半導体部材31とガラス基板32との間には、Cuスタッドバンプ41とはんだバンプ44との接続部を封止するアンダーフィル(UF)樹脂33が設けられている。
また、半導体部材31は、受光面と同じ面にガラス基板32と接続される電極45が形成されている。そして、この電極45上に、フリップチップ接続用のCuスタッドバンプ41が形成されている。Cuスタッドバンプ41は、はんだバンプ44との接触面に合金層43が形成されている。また、Cuスタッドバンプ41は、はんだバンプ44と接触していない表面にめっき層42を備える。
次に、上述の半導体装置30において、半導体部材31上に形成するCuスタッドバンプ41の構成を、図4に示す。図4に示すCuスタッドバンプ41は、接続前の状態である。また、図5に半導体部材31とガラス基板32とを接続した後の、Cuスタッドバンプ41とはんだバンプ44との構成を示す。
また、Cuスタッドバンプ41は、表面がめっき層42により被覆されている。
めっき層42は、Cuスタッドバンプ41の酸化を防ぐための保護層となる。また、めっき層42は、Cuスタッドバンプ41をフリップチップ接続した際に、表面のめっき層が、はんだバンプ44内に速やかに拡散する材料によって構成する。
めっき層42としては、例えば、無電解法によるフラッシュNiめっき層とフラッシュAuめっき層とからなるめっき層、又は、無電解Coめっき層を用いる。
めっき層42は、例えば、各層の厚さが0.01〜0.1μmで形成される。
例えば、はんだバンプ44がInからなる場合には、Cuスタッドバンプ41とはんだバンプ44との界面にIn3Cu7の金属間化合物等が形成される。In3Cu7の金属間化合物は、機械的強度を十分に有する。このため、低温フリップチップ接続においても、接続信頼性の低下を引き起こす強度の低い合金が発生しない。また、Cuスタッドバンプと、上述の二元系低融点はんだ等との組み合わせにおいても、界面に機械的強度に劣る合金層が発生しない。このため、熱に弱い構成を備える半導体部材31においても、フリップチップ接続を適用することができる。
従って、フリップチップ接続において、低温接続が可能であり、さらに、半導体装置の接続信頼性を向上することができる。
上述の第1実施形態の半導体装置の製造方法について説明する。なお、以下の説明では、半導体装置に形成するスタッドバンプ周辺の構成のみを説明する。その他の構成は従来公知の方法により製造することができる。
図6に、図3に示す半導体装置30のプロセスフローを示す。
図6に示すように、公知の方法を用いて、半導体基体上に半導体部材31を構成する、フォトダイオード、各種トランジスタ等の各素子や、配線等を形成する。このとき、フリップチップ接続を行うための外部接続用の電極45を形成する。
半導体部材31の外部機器との接続用の電極45上に、Cuスタッドバンプ41を形成する。
形成したCuスタッドバンプ41上に無電解めっき法を用いて、めっき層42を形成する。
半導体基体の各種素子の形成面と反対側の面(裏面)を切削(バックグラインド:BG)し、裏面照射型の固体撮像素子を構成する半導体部材31を形成する。
半導体基体をダイシング(DC)して半導体部材31を個片化する。
UBM48上に低融点はんだを用いてはんだバンプ44を形成する。
以上の工程により、半導体装置30を製造することができる。
上述の半導体装置30のプロセスフローにおけるCuスタッドバンプの形成工程を、図7に示す製造工程図を用いて説明する。
図7Aに示すように、キャピラリ52を用いて半導体部材31の電極45上にCuワイヤ51のボンディングを行う。そして、Cuワイヤ51を切断することにより、図7Bに示すように、Cuスタッドバンプ41を形成する。Cuスタッドバンプ41の形成工程では、例えば、径が15〜35μmΦのCuワイヤ51を用いて、30〜70μmΦのCuスタッドバンプ41を形成する。
めっき層42は、例えば、Niめっき層とAuめっき層をそれぞれ0.01〜0.1μmの厚さに形成する。
以上の工程により、半導体部材31上にCuスタッドバンプ41を形成する。
次に、上述の半導体装置30のプロセスフローにおけるはんだバンプの形成工程を、図8に示す製造工程図を用いて説明する。
図8Aに示すように、電極47及び保護層49の表面にバリアメタル層53を形成する。
バリアメタル層53を形成する前に、電極47の表面の酸化膜を逆スパッタにより除去する。その後、スパッタリング法を用いて電極47上にTi層を形成する。そして、Ti層を被覆するように、スパッタリング法を用いてCu層を形成する。このように、Ti層とCu層とからなるバリアメタル層53を形成する。
以上の工程により、ガラス基板32上にはんだバンプ44を形成する。
次に、上述の半導体装置30のプロセスフローにおけるフリップチップ接続工程及びUF樹脂封止工程を、図9に示す製造工程図を用いて説明する。
まず、図9Aに示すように、Cuスタッドバンプ41の形成面とはんだバンプ44の形成面とを対向させて、半導体部材31とガラス基板32との位置を合わせる。
上述のフリップチップ接続において圧接時のバンプ単位に掛ける圧力(Bonding force)は、例えば、0.01gf/bump〜10gf/bumpである。また、フリップチップ接続の際の加熱温度は200℃以下とする。また、加熱温度は、使用するはんだバンプ44の融点以上の温度とする。例えば、はんだバンプ44にIn単体のはんだを用いた場合には、Inの融点である156℃以上に加熱する。
以上の工程により、ガラス基板32に半導体部材31をフリップチップ接続することができる。
次に、上述の半導体装置30の製造方法の変形例を示す。この変形例では、UF樹脂によるフリップチップ接続部の封止を行う工程が、上述の製造方法と異なる。
図10に、UF樹脂封止工程を変更したプロセスフローを示す。
半導体部材の外部機器との接続用の電極45上に、Cuスタッドバンプ41を形成する。
形成したCuスタッドバンプ41上に無電解めっき法を用いて、めっき層42を形成する。
形成したCuスタッドバンプ41上にアンダーフィル(UF)樹脂33をラミネートする。
半導体基体の各種素子の形成面と反対側の面(裏面)を切削(バックグラインド:BG)し、裏面照射型の固体撮像素子を構成する半導体部材31を形成する。
半導体基体をダイシング(DC)して半導体部材31を個片化する。
UBM48上に低融点はんだを用いてはんだバンプ44を形成する。
以上の工程により、半導体装置30を製造することができる。
まず、上述の工程によりCuスタッドバンプ41にめっき層42を形成(図7C)した後、図11Aに示すように、Cuスタッドバンプ41を覆うアンダーフィル(UF)樹脂33を形成する。UF樹脂33は、例えば、アンダーフィル樹脂を含む塗布液を用いたスピンコート法、又は、アンダーフィル樹脂のドライフィルムのラミネートにより形成する。
以上の工程により、フリップチップ接続の前にCuスタッドバンプ41を覆うUF樹脂33を形成し、UF樹脂33をフリップチップ接続後に硬化する方法により、半導体装置30を製造することができる。
上述の第1実施形態の半導体装置において、ガラス基板の代わりに配線基板を用いることができる。図12に、配線基板を用いた半導体装置の構成を示す。
また、配線基板37は、配線基板37上に形成されたフリップチップ接続用の電極47と、電極47上に形成されたアンダーバンプメタル(UBM)48と、UBM48上に形成された低融点はんだバンプ44とを備える。さらに、ガラス基板32上に形成された配線層34と、配線層34を被覆する保護層49と、配線層34と接続された外部接続用の電極35と、外部接続用の電極35上に形成されたはんだボール36とを備える。
配線基板37は、半導体部材31の受光面上に透光性の光学部材38、例えばガラス等を備える。そして、光学部材38の周囲に沿っての配線基板37上に、電極47、UBM48及びはんだバンプ44が形成されている。
次に、半導体装置の第2実施形態について説明する。図13に第2実施形態の半導体装置を示す。
図13に示す半導体装置60は、第1半導体部材61と第2半導体部材62とからなる。そして、第2半導体部材62上に、第1半導体部材61がフリップチップ接続により搭載されている。
はんだバンプ44は、低融点はんだから構成される。低融点はんだとしては、例えば、Inの一元系はんだ材料、Sn−Bi、Sn−In、Bi−In等の二元系低融点はんだ材料、上記二元系材料にその他の金属が添加されたはんだ材料等を用いる。
Cuスタッドバンプ41とはんだバンプ44との接触面には、Cuとはんだとの合金層43が形成されている。
[製造方法1:後UF樹脂プロセスフロー]
図14に、図13に示す半導体装置60のプロセスフローを示す。
図14に示すように、公知の方法を用いて、半導体基体上に第1半導体部材61を構成する各種トランジスタ等の各素子や、配線等を形成する。このとき、フリップチップ接続を行うための外部接続用の電極45を形成する。
第1半導体部材61の外部機器との接続用の電極上に、Cuスタッドバンプ41を形成する。
形成したCuスタッドバンプ41上に無電解めっき法を用いて、めっき層42を形成する。
半導体基体の各種素子の形成面と反対側の面(裏面)を切削(バックグラインド:BG)する。そして、半導体基体をダイシング(DC)して第1半導体部材61を個片化する。
UBM48上に低融点はんだを用いてはんだバンプ44を形成する。
そして、半導体基体の各種素子の形成面と反対側の面(裏面)を切削(バックグラインド:BG)する。そして、半導体基体をダイシング(DC)して第2半導体部材62を個片化する。
フリップチップ接続後、Cuスタッドバンプ41とはんだバンプ44との接続部を覆って、第1半導体部材61と第2半導体部材との間にアンダーフィル(UF)樹脂33を注入する。そして、注入したUF樹脂33を加熱して硬化(キュア)する。
以上の工程により、第2実施形態の半導体装置60を製造することができる。
なお、Cuスタッドバンプ41の形成、はんだバンプ44の形成、及び、フリップチップ接続は、上述の図7〜9に示す第1実施形態と同様の方法により行うことができる。
次に、上述の第2実施形態の半導体装置60の製造方法の変形例を示す。この変形例では、UF樹脂による半導体部材同士の封止を行う工程が、上述の製造方法と異なる。
図15に、UF樹脂封止工程を変更したプロセスフローを示す。
第1半導体部材61の外部機器との接続用の電極上に、Cuスタッドバンプ41を形成する。
形成したCuスタッドバンプ41上に無電解めっき法を用いて、めっき層42を形成する。
形成したCuスタッドバンプ41を覆って、第1半導体部材61の全面にアンダーフィル(UF)樹脂33をラミネートする。
半導体基体の各種素子の形成面と反対側の面(裏面)を切削(バックグラインド:BG)する。そして、半導体基体をダイシング(DC)して第1半導体部材61を個片化する。
UBM48上に低融点はんだを用いてはんだバンプ44を形成する。
そして、半導体基体の各種素子の形成面と反対側の面(裏面)を切削(バックグラインド:BG)する。そして、半導体基体をダイシング(DC)して第2半導体部材62を個片化する。
以上の工程により、第2実施形態の半導体装置60を製造することができる。
[カメラ]
上述の実施形態の半導体装置は、例えば、半導体メモリや、デジタルカメラやビデオカメラ等のカメラシステム、撮像機能を有する携帯電話、又は、撮像機能を備えた他の機器等の電子機器に適用可能である。以下、電子機器の一構成例として、カメラを例に挙げ説明する。
この例のカメラ70は、固体撮像装置71と、固体撮像装置71の受光センサ部に入射光を導く光学系72と、固体撮像装置71及び光学系72間に設けられたシャッタ装置73と、固体撮像装置71を駆動する駆動回路74とを備える。さらに、カメラ70は、固体撮像装置71の出力信号を処理する信号処理回路75を備える。
光学系(光学レンズ)72は、被写体からの像光(入射光)を固体撮像装置71の撮像面(不図示)上に結像させる。これにより、固体撮像装置71内に、一定期間、信号電荷が蓄積される。なお、光学系72は、複数の光学レンズを含む光学レンズ群で構成してもよい。また、シャッタ装置73は、入射光の固体撮像装置71への光照射期間及び遮光期間を制御する。
(1)半導体部材と、前記半導体部材上に形成されているCuスタッドバンプと、前記Cuスタッドバンプと電気的に接続するはんだバンプと、を備える半導体装置。
(2)前記Cuスタッドバンプの表面に形成されためっき層を備える(1)に記載された半導体装置。
(3)前記はんだバンプが、In、SnBi、SnIn及びBiInから選ばれる少なくとも1種類以上を含んで構成されている(1)又は(2)に記載された半導体装置。
(4)前記めっき層が、NiとAuとのめっき層、又は、Coめっき層からなる(2)又は(3)に記載された半導体装置。
(5)半導体部材上にCuスタッドバンプを形成する工程と、前記Cuスタッドバンプをはんだバンプにフリップチップ接続する工程と、を有する半導体装置の製造方法。
(6)無電解めっき法により前記Cuスタッドバンプ表面にめっき層を形成する工程を有する(5)に記載の半導体装置された製造方法。
(7)フリップチップ接続時に200℃以下で加熱する、又は、フリップチップ接続後に200℃以下の加熱を行う(5)又は(6)に記載された半導体装置の製造方法。
(8)(1)〜(4)に記載された半導体装置と、前記半導体装置の出力信号を処理する信号処理回路と、を備える電子機器。
Claims (8)
- 半導体部材と、
前記半導体部材上に形成されているCuスタッドバンプと、
前記Cuスタッドバンプと電気的に接続するはんだバンプと、を備える
半導体装置。 - 前記Cuスタッドバンプの表面に形成されためっき層を備える請求項1に記載された半導体装置。
- 前記はんだバンプが、In、SnBi、SnIn及びBiInから選ばれる少なくとも1種類以上を含んで構成されている請求項1に記載された半導体装置。
- 前記めっき層が、NiとAuとのめっき層、又は、Coめっき層からなる請求項2に記載された半導体装置。
- 半導体部材上にCuスタッドバンプを形成する工程と、
前記Cuスタッドバンプをはんだバンプにフリップチップ接続する工程と、を有する
半導体装置の製造方法。 - 無電解めっき法により前記Cuスタッドバンプ表面にめっき層を形成する工程を有する請求項5に記載された半導体装置の製造方法。
- フリップチップ接続時に200℃以下で加熱する、又は、フリップチップ接続後に200℃以下の加熱を行う請求項5に記載された半導体装置の製造方法。
- 半導体部材と、前記半導体部材上に形成されているCuスタッドバンプと、前記Cuスタッドバンプと電気的に接続するはんだバンプとからなる半導体装置と、
前記半導体装置の出力信号を処理する信号処理回路と、を備える
電子機器。
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- 2012-08-07 US US13/568,574 patent/US9105625B2/en not_active Expired - Fee Related
- 2012-08-07 TW TW101128440A patent/TWI523175B/zh not_active IP Right Cessation
- 2012-08-10 CN CN2012102857034A patent/CN102956603A/zh active Pending
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JP2014175592A (ja) * | 2013-03-12 | 2014-09-22 | Stanley Electric Co Ltd | 半導体発光装置 |
JP2015195319A (ja) * | 2014-03-31 | 2015-11-05 | 日本電気株式会社 | モジュール部品及びその製造方法 |
TWI488244B (zh) * | 2014-07-25 | 2015-06-11 | Chipbond Technology Corp | 具有凸塊結構的基板及其製造方法 |
JP2016076617A (ja) * | 2014-10-07 | 2016-05-12 | 新光電気工業株式会社 | 指紋認識用半導体装置、指紋認識用半導体装置の製造方法及び半導体装置 |
US10062657B2 (en) | 2014-10-10 | 2018-08-28 | Ishihara Chemical Co., Ltd. | Method for manufacturing alloy bump |
Also Published As
Publication number | Publication date |
---|---|
KR20130020565A (ko) | 2013-02-27 |
TW201320270A (zh) | 2013-05-16 |
TWI523175B (zh) | 2016-02-21 |
US9105625B2 (en) | 2015-08-11 |
US20130043585A1 (en) | 2013-02-21 |
JP6035714B2 (ja) | 2016-11-30 |
KR101996676B1 (ko) | 2019-07-04 |
CN102956603A (zh) | 2013-03-06 |
US20150303167A1 (en) | 2015-10-22 |
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