TWI523175B - 半導體裝置,製造半導體裝置的方法,以及電子裝置 - Google Patents

半導體裝置,製造半導體裝置的方法,以及電子裝置 Download PDF

Info

Publication number
TWI523175B
TWI523175B TW101128440A TW101128440A TWI523175B TW I523175 B TWI523175 B TW I523175B TW 101128440 A TW101128440 A TW 101128440A TW 101128440 A TW101128440 A TW 101128440A TW I523175 B TWI523175 B TW I523175B
Authority
TW
Taiwan
Prior art keywords
bump
solder
semiconductor
stud
stud bump
Prior art date
Application number
TW101128440A
Other languages
English (en)
Other versions
TW201320270A (zh
Inventor
脅山悟
尾崎裕司
Original Assignee
新力股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新力股份有限公司 filed Critical 新力股份有限公司
Publication of TW201320270A publication Critical patent/TW201320270A/zh
Application granted granted Critical
Publication of TWI523175B publication Critical patent/TWI523175B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14618Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H01L2224/11416Spin coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1143Manufacturing methods by blanket deposition of the material of the bump connector in solid form
    • H01L2224/11436Lamination of a preform, e.g. foil, sheet or layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • H01L2224/11825Plating, e.g. electroplating, electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/13076Plural core members being mutually engaged together, e.g. through inserts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/1319Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13562On the entire exposed surface of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1357Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165Material
    • H01L2224/16501Material at the bonding interface
    • H01L2224/16503Material at the bonding interface comprising an intermetallic compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8102Applying permanent coating to the bump connector in the bonding apparatus, e.g. in-situ coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134Bonding interfaces of the bump connector
    • H01L2224/81355Bonding interfaces of the bump connector having an external coating, e.g. protective bond-through coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81413Bismuth [Bi] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81805Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/8181Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/81951Forming additional members, e.g. for reinforcing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Wire Bonding (AREA)

Description

半導體裝置,製造半導體裝置的方法,以及電子裝置
本發明是關於經配置而使用一柱形凸塊連接的一種半導體裝置、一種製造半導體裝置的方法、以及一種電子裝置。
關於半導體裝置的一覆晶連接(flip-chip connection)技術,有一將Au柱形凸塊予以連接於錫銀SnAg焊料凸塊的方法,或有一將Au柱形凸塊予以連接於塗覆有Pd的Sn焊料凸塊的方法(日本專利申請公開號2009-218442和2009-239278)。
有一覆晶連接技術,其將Au柱形凸塊予以連接於半導體晶片之Cu電極(日本專利申請公開號2001-60602),或有一覆晶連接技術,其藉由將Au柱形凸塊予以連接於鍍Sn之半導體晶片之Cu電極(日本專利申請公開號2005-179099)。
此外,已有提出建議以一Cu柱形凸塊取代Au柱形凸塊(日本專利申請公開號2011-23568)。
在使用前述柱形凸塊之覆晶連接技術中,其被要求改進半導體裝置之連接可靠性。
本揭露提供具有高連接可靠性之一種半導體裝置、製造半導體裝置的方法、以及電子裝置。
本揭露的半導體裝置包括一半導體構件、一形成於半導體構件的Cu柱形凸塊、以及一經配置而電性連接於該Cu柱形凸塊的焊料凸塊。
此外,本揭露的製造半導體裝置的方法包括:於一半導體構件形成一Cu柱形凸塊;以及覆晶連接該Cu柱形凸塊至一焊料凸塊。
此外,本揭露的電子裝置中包含一半導體裝置和一經配置而處理半導體裝置之一輸出信號的信號處理電路。
根據該半導體裝置和該半導體裝置的製造方法,使用Cu柱形凸塊執行覆晶連接,即使在低溫連接下,在銅與焊料之間的連接部並不會產生低強度的合金。因此,防止在Cu柱形凸塊和焊料凸塊之間的連接部有連接缺陷,並能夠提升連接可靠性。
根據本揭露,可能提供具有高連接可靠性的半導體裝置和電子裝置。
本揭露的這些和其它目的、特徵和優點按照接下來如附呈圖式所示之實施方式將更加容易理解。
在下文中將描述用以實現本揭露的實施例之例子。但是,本揭露將不會被限制在下述的例子。
值得注意的是,將按照以下順序給出下面的描述。
1.半導體裝置綜述
2.半導體裝置之第一實施例
3.製造半導體裝置的方法之第一實施例
4.半導體裝置之第二實施例
5.製造半導體裝置的方法之第二實施例
6.電子裝置
1.半導體裝置綜述
將描述半導體裝置之覆晶連接的綜述。
第1圖係顯示使用一般Au柱形凸塊的相關技術之覆晶連接之結構配置。第1A圖係顯示Au柱形凸塊11和Sn凸塊12連接前之結構配置。第1B圖係顯示Au柱形凸塊11和Sn凸塊12連接後之結構配置。
第1A圖所示的Au柱形凸塊11是由Au金屬線所形成的Au凸塊。Au柱形凸塊11上形成電極14,電極14形成在半導體構件13。除了形成有Au柱形凸塊11的電極14外,半導體構件13由一保護層15所塗覆。
此外,如第1A圖所示的Sn凸塊12包括一Sn群組焊料,諸如一SnAg焊料凸塊。Sn凸塊12包含一形成於配線基板16的電極17以及一形成於電極17的凸塊下金屬層(under bump metal,UBM)18。配線基板16在除了形成有UBM 18的電極17之外的部分塗覆有一保護層19。
如第1B圖所示,半導體構件13係藉Au柱形凸塊11和Sn凸塊12而覆晶連接於配線基板16。
此時,可能有必要在於300℃或更高來連接Au柱形凸塊11和Sn凸塊12,以提升連接可靠性。
如第1B圖所示,於300℃或更低的連接中,由於Au對Sn之擴散,使得於連接部產生有一具有低強度的金屬間化合物(IMC)20,如SnAu4合金。因此,裂紋24和相似物的產生可能會降低連接性和可靠性。此外,由於Au柱形凸塊11伸入Sn凸塊12,所以防止Au擴散至Sn是困難的。因此,在連接部分之IMC 20的產生是難以防止的。
如上所述,覆晶連接藉由Au柱形凸塊11和Sn凸塊12而執行,它可能有必要在300℃或更高執行高溫連接,因此,在低溫連接鑒於連接可靠性是很難執行的。
此外,如第2圖所示,取代使用Sn凸塊,考慮使用In群組的一低熔點之焊料凸塊以覆晶連接Au柱形凸塊11。第2A圖係顯示Au柱形凸塊21和In凸塊22連接前之結構配置。第2B圖係顯示Au柱形凸塊21和In凸塊22連接後之結構配置。
第2A圖所示的Au柱形凸塊21具有如上述第1A圖所示相同的結構配置。此外,In凸塊係由In群組焊料構成。在此方法中,不會產生具有低強度如SnAu4合金的合金,所以它能夠在200℃或更低下進行覆晶連接。
然而,藉由Au柱形凸塊21和In凸塊22進行連接,Au和In之間的擴散係數是大的,所以對於AuIn合金的增長是很難控制。如第2B圖所示,In凸塊因AuIn合金23之增長而吸入。因此,藉由Au柱形凸塊21和In凸塊22而進行覆晶連接,它是難以確保連接性。
如上所述,使用柱形凸塊的覆晶連接,考慮到連接可 靠性是難以進行低溫處理。因此,在具有低耐熱性的材料的情況下被安裝在該半導體組件等,也難以適用於具有高連接可靠性之覆晶連接。因此,一覆晶連接方法已被要求在低溫下能夠穩定地連接,該半導體裝置通過使用具有低耐熱性的材料而形成,並具有高的連接可靠性。
2.半導體裝置之第一實施例 [圖像傳感器:結構配置]
在下文中,進行說明該半導體裝置之第一實施例。第3圖是顯示如第一實施例所述的半導體裝置的結構之剖面圖。在第一實施例,將描述作為半導體裝置之圖像傳感器的一個例子。第3圖係顯示一半導體裝置30藉由一圖像傳感器安裝在玻璃基板而形成之剖面圖。
一半導體裝置30係藉由包括一圖像傳感器和一玻璃基板32之一半導體構件31而構成。半導體構件31包括形成於半導體構件31之一電極45和形成於電極45之一Cu柱形凸塊41。
此外,玻璃基板32包含:一電極47,藉由覆晶連接形成於玻璃基板32;凸塊下金屬層(UBM)48,形成於電極47上;以及一低熔點的焊料凸塊44,形成於凸塊下金屬層48上。另外,一配線層34形成於玻璃基板32、一保護層49塗覆於配線層34、一電極35用於外部連結連接於配線層34、以及一焊料球36形成於一外部連結之電極35。
此外,填充樹脂(under-fill)33密封於Cu柱形凸塊41 和焊料凸塊44之間一連接部,填充樹脂設置於半導體構件31和玻璃基板32之間。
半導體構件31是作為圖像傳感器通常使用的元件,是如CCD(電荷耦合器件)圖像傳感器和CMOS(互補金屬氧化物半導體)圖像傳感器的一種半導體元件。半導體構件31設置於玻璃基板32之面對光接收表面的一側。
此外,電極45連接於玻璃基板32之光接收表面的同一側而形成於半導體構件31。然後,用於覆晶連接之銅柱形凸塊41形成於電極45。合金層43形成於Cu柱形凸塊41和焊料凸塊44之間的接觸面。此外,Cu柱形凸塊41包含一沒有接觸於焊料凸塊44的表面之鍍層42。
例如玻璃基板32是用於圖像傳感器的蓋玻璃而構成。然後,用於覆晶連接之電極35和用於外部連結之電極47藉由配線層34而連接於玻璃基板32。焊料球36用於連接到外部設備而形成於電極35。焊料球36是用於Sn群組和相似物的二元或三元的焊料。例如,SnBi、SnIn、SnAgCu、SnZn、以及SnAg和相似物等使用。
值得注意的是,可藉由Au配線替代焊料球36,玻璃基板32能使用Au配線並藉由配線連接。
[Cu柱形凸塊:結構配置]
接著,在上述半導體裝置圖30,第4圖係顯示Cu柱形凸塊41形成於半導體構件31的結構配置狀態。第4圖係顯示Cu柱形凸塊41於連接前狀態之剖面圖。此外,第 5圖係顯示Cu柱形凸塊41和焊料凸塊44連接於半導體構件31和玻璃基板32之後狀態之剖面圖。
如第4圖所示,半導體構件31之電極45形成於Cu柱形凸塊41。除了形成於Cu柱形凸塊41之電極45,半導體構件31塗覆一保護層46。
另外,Cu柱形凸塊41的表面塗覆該鍍層42。
鍍層42是防止Cu柱形凸塊41氧化之一保護層。此外,當銅柱形凸塊41是覆晶連接,該鍍層42為以一於焊料凸塊44表面之鍍層而迅速擴散之材料所形成。
例如,關於該鍍層42,係為使用藉由無電方法而由一快閃鎳鍍層和一快閃金鍍層所構成之鍍層,或一無電鈷鍍層。
例如,鍍層42的厚度為0.01至0.1微米。
另外,焊料凸塊44設置在玻璃基板32而形成低熔點焊料。例如,關於作為低熔點焊料,可使用In之一元焊料物質,低熔點焊料之二元的焊料物質如Sn-Bi、Sn-In、Bi-In,以及藉由加入其它金屬形成二元的焊料物質。例如,關於低熔點焊料,可使用熔點為200℃或更低之焊料物質。
然後,形成於半導體構件31之Cu柱形凸塊41壓接於玻璃基板32之焊料凸塊44,由此將Cu柱形凸塊41之頂端使進入焊料凸塊44。接著,在Cu柱形凸塊41貼黏(stuck)至焊料凸塊44的狀態下執行加熱,而如第5圖所示進行覆晶連接。
如第5圖所示,當進行覆晶連接,在銅柱形凸塊41和焊料凸塊44之間接觸面的一鍍層42,被擴散進入焊料凸塊44。此外,銅和焊料的合金層43形成於Cu柱形凸塊41和焊料凸塊44之間的接觸表面。此時,優異的是,該焊料凸塊44並不完全為合金,且非合金的焊料凸塊44留在凸塊下金屬層48。
在上述結構配置中,藉由使用Cu作為覆晶連接的柱形凸塊材料,它是能夠防止產生一具有弱機械強度合金於該低熔點焊料凸塊44的一介面。此外,藉由使用低熔點焊料作為焊料凸塊44而可在低溫執行一覆晶連接。
例如,焊料凸塊44藉由In構成的情況下,In3Cu7之金屬間化合物等形成於Cu柱形凸塊41和焊料凸塊44之間的一介面。In3Cu7之金屬間化合物具有足夠的機械強度。因此,即使在低溫的覆晶連接,合金具有低的強度而導致連接可靠性的降低是不產生的。此外,即使在Cu柱形凸塊和低熔點二元焊料材料等,具有弱的機械強度的合金層並沒有在介面產生。因此,即使在半導體元件31具有熱敏感的配置,它是可以適用於覆晶連接。
因此,當覆晶連接,它能夠於低溫執行連接,並進一步提高了連接可靠性的半導體裝置。
3.製造半導體裝置的方法之第一實施例
將對製造半導體裝置的方法之第一實施例進行說明。在以下的說明中,半導體裝置只在臨近形成的的柱形凸塊 之配置將被描述。其它的結構,可以由相關技術的習知方法製造。
[製造方法:後續的UF樹脂的處理流程]
第6圖顯示出如第3圖所示的半導體裝置30的處理流程。
如圖6中所示。元件如光二極體和各種電晶體,和配線等構成的半導體構件31形成於半導體基底是習知的方法。此時,用於形成於外部連接的電極45是使用覆晶連接。
Cu柱形凸塊41形成於電極45上,用於連接到半導體構件31之外部設備。
藉由無電鍍法而於成形的銅柱形凸塊41形成該鍍層42。
相反的表面(背面)用於形成不同種的半導體基底上的元件被切斷(背面磨削;BG),和半導體構件31藉由背面照射型固態攝像裝置而形成。
半導體基底進行切割(DC),並在半導體構件31被分離成單獨的芯片。
此外,配線層34、電極47等藉由習知方法在玻璃基板32上形成。然後,電極47形成於凸塊下金屬層48。
凸塊下金屬層48使用低熔點焊料形成於焊料凸塊44。
接著,銅柱形凸塊41被帶入壓合(接合)於焊料凸塊44,覆晶連接之半導體構件31從而被分離成單獨的芯片 至玻璃基板32。連接後,填充(UF)樹脂33於周圍注射銅柱形凸塊41和焊料凸塊44之間的連接部分。然後,注入的UF樹脂33被加熱和UF樹脂硬化(固化)。
用上述方法,能夠製造半導體裝置30。
[製造方法:銅柱形凸塊]
銅柱形凸塊形成於上述半導體裝置30的處理流程的過程中,將描述參照如第7圖所示的製造處理。
如第7A圖所示,銅線51使用毛細管52並藉導入接合於半導體構件31之電極45。然後,如第7B圖所示,銅柱形凸塊41藉由銅線51切割而形成。例如在銅柱形凸塊41的形成過程中,具有一直徑為15至35微米之銅線51被用來形成具有一直徑30至70微米之銅柱形凸塊41。
接下來,如第7C圖所示,銅柱形凸塊41的表面是形成於鍍層42。藉由無電鍍方法而形成鍍層42。例如,藉由無電鍍方法於Cu柱形凸塊41的表面進行快閃鍍Ni。然後,快閃鍍Ni層表面進行快閃鍍Au。因此,鍍層42的構成藉由鍍Ni層和鍍Au層而形成。
例如,鍍層42之鍍Ni層和鍍Au層分別具有厚度為0.01至0.1微米。
此外,例如,Co鍍層藉由無電鍍法進行於作為鍍層42之Cu柱形凸塊41的表面。在這種情況下,具有厚度為0.01至0.1微米之鍍層42是藉由Co鍍層而形成。
藉由上述過程,Cu柱形凸塊41形成於半導體構件31。
[製造方法:焊料凸塊]
接著請參閱第8圖,半導體裝置30之焊料凸塊形成的過程,將描述於製造處理流程圖。
如第8A圖所示,電極47和保護層49的表面形成於金屬障壁層53。
金屬障壁層53形成前,電極47表面的氧化膜經由反向濺射而移除。接著,電極47是經由濺射法而形成於Ti層。然後,形成Cu層,以藉由濺射法塗覆Ti層。因此,金屬障壁層53藉由Ti層和Cu層而構成。
接下來,如第8B圖所示。金屬障壁層53形成於抗蝕劑層54。然後,抗蝕劑層54經由光罩55進行曝光處理。在光罩55,用於形成電極47的部分之曝光光照的圖案被使用。
接下來,如第8C圖所示,凸塊下金屬層48和焊料凸塊44形成於經由一電鍍法移除抗蝕劑層54之暴露部的開口。凸塊下金屬層48藉由Ni、Ti、TiW、W、Cu、和類似物的電鍍方法而形成。此外,藉由一元焊料的銦之電鍍方法、低熔點材料的二元焊料材料,如Sn-Bi、Sn-In、Bi-In、和類似物等而形成焊料凸塊44。
接下來,如第8D圖所示。將抗蝕劑層54移除後,所述金屬障壁層53暴露於表面而除去。另外,焊料凸塊44經由回流是呈球形形式而熔化。
經由上述過程,玻璃基板32形成於焊料凸塊44。
[製造方法:覆晶連接]
接著,覆晶連接處理和UF樹脂密封過程於上述半導體裝置30的所述處理的製造處理流程圖,請參閱第9圖所示。
首先,如第9A圖所示,半導體構件31和玻璃基板32藉由Cu柱形凸塊41的表面和焊料凸塊44的表面而排列形成。
接下來,如第9B圖所示,Cu柱形凸塊41和焊料凸塊44是排列對齊的,所述半導體構件31和玻璃基板32被帶入壓合而進行覆晶連接。在這時間,壓合和加熱同時進行於覆晶連接。Cu柱形凸塊41的表面為鍍層42,藉由加熱程序擴散至焊料凸塊44。此外,Cu柱形凸塊41和焊料凸塊44之間的接合面藉由加熱程序產生合金層43。
例如,在上述的覆晶連接,施加至凸塊的每個單元於壓合接觸期間的壓力(結合力)為0.01 gf/bump至10 gf/bump。此外,覆晶連接之加熱溫度設定在200℃或更低。此外,加熱溫度設定於焊料凸塊44的熔點溫度或以上。例如,固態In焊料使用於焊料凸塊44的情況下,焊料在In的熔點156℃或更高下加熱。
接下來,如第9C圖所示,填充(UF)樹脂33施加至Cu柱形凸塊41和焊料凸塊44之間的連接部。然後,填充樹脂33被加熱和硬化。填充樹脂33、半導體構件31、和玻璃基板32是接合,從而提高半導體裝置的黏合表面之機 械連接可靠性。
上述過程,半導體構件31可以覆晶連接於玻璃基板32。
在上述的覆晶連接,可使用低熔點焊料的焊料凸塊44而在200℃或更低進行退火。此外,具有低強度的合金儘管在低溫覆晶連接而使用銅柱形凸塊41係不被產生。
值得注意的是,在上述提到的製造過程中,加熱過程引起合金層的生長並不需要和覆晶連接在同一時間。例如,帶入壓合的過程後和半導體構件31的覆晶連接方法,以及玻璃基板32,可利用不同進程而退火。此時,在200℃或更低溫度下進行退火。
[修改的例子:初步UF樹脂處理流程]
接著,在上述半導體裝置30的製造方法之修改的例子將被描述。在修改後的例子中,藉由UF樹脂密封覆晶連接的連接部是不同於上述製造方法。
第10圖顯示藉由UF樹脂密封過程而改變的處理流程。
如第10圖所示,元件如光二極管和各種電晶體管,和配線和類似物構成半導體構件31於半導體基底上形成係用習知的方法。此時,形成用於外部連接的電極45,用於執行覆晶連接。
電極45形成於Cu形凸塊41,而用於連接至半導體構件之外部設備。
藉由無電鍍方法,成型的銅柱形凸塊41形成於鍍層 42。
成型的Cu柱形凸塊41是層疊在填充(UF)樹脂33。
相反的表面(背面)之面用於形成不同種元件為半導體基底被切斷(背面磨削:BG)和半導體構件31構成的後表面形成照射型固態成像裝置。
半導體基底進行切割(DC)和半導體元件31被分離成單獨芯片。
此外,玻璃基板32經由習知的方法形成於配線層34、電極47和相似物等。然後,電極47形成於凸塊下金屬層(UBM)48。
凸塊下金屬層(UBM)48使用低熔點焊料形成於焊料凸塊44。
接著,Cu柱形凸塊41被納入而壓接觸(接合)於焊料凸塊44,從而覆晶連接之半導體構件31被分離成單獨的芯片於玻璃基板32。連接後,UF樹脂33被加熱和硬化(固化)。
藉由上述過程,半導體裝置30可以被製造。
接著,請參閱第11圖的製造處理圖,為上述半導體裝置30的處理流程進行說明之UF樹脂形成工序和UF樹脂密封工序。在以下的說明中,僅有與上述製造半導體裝置的方法中是不同的過程將被描述。
首先,Cu柱形凸塊41藉由上述程序形成於鍍層42(第7C圖),然後填充(UF)樹脂33覆蓋而形成於Cu柱形凸塊41如第11A圖所示。例如,利用填充樹脂或填充樹脂之乾 燥膜層的塗佈液,填充(UF)樹脂33能藉由旋塗法而形成。
接下來,如第11B圖所示,半導體構件31和玻璃基板32藉由形成於Cu柱形凸塊41之表面和形成於焊料凸塊44之表面而面對並校準。然後,如第11C圖所示,半導體構件31和玻璃基板32經由壓接觸和覆晶連接。另外,合金層43形成於銅柱形凸塊41和焊料凸塊44之間的連接面,並且藉由熱加工而硬化UF樹脂33。
藉由上述過程,於覆晶連接之前,覆蓋於Cu柱形凸塊41之UF樹脂33被形成,而該半導體裝置30在藉由覆晶連接後之硬化UF樹脂33的方法而被製造。
[半導體裝置的一修改例]
在半導體裝置的第一實施例,配線基板能替代玻璃基板。第12圖顯示半導體裝置使用配線基板之配置。
如第12圖所示的半導體裝置,半導體構件31經由圖像傳感器和配線基板37而構成。半導體構件31包含形成於半導體構件31上的電極45和形成於電極45上的Cu柱形凸塊41。
此外,配線基板37包含電極47藉由覆晶連接形成於配線基板37,電極47形成於凸塊下金屬層(UBM)48,以及凸塊下金屬層(UBM)48形成於低熔點之焊料凸塊44。再者,配線基板37包含:形成於玻璃基板32上的配線層34;保護層49,塗覆配線層34;電極35,用於外部連接 到配線層34;以及焊料球36,形成於用於外部連接的電極35之上。
例如,配線基板37包含一位於半導體構件31之光接收面玻璃上的透光性光學構件38。然後,沿著透光性光學構件38的圓周,配線基板37形成於電極47、凸塊下金屬層(UBM)48、和焊料凸塊44。
另外,如第12圖所示為半導體構件31、半導體構件31之銅柱形凸塊41、及相似物之配置和第一實施例是相同的。此外,焊料凸塊44、電極47、配線層34、及相似物形成於配線基板37之配置與第一實施例是相同的。
如上所述的修改實施例中,半導體構件31之元件包含Cu柱形凸塊41是覆晶連接合並不限定,只要作為電子構件包含一電極對應於覆晶連接和焊料凸塊形成於電極而利用。例如,除了如上所述的玻璃基板和配線基板等,半導體構件可能是半導體元件和相似物而覆晶連接。
4.半導體裝置的第二實施例
接著,半導體裝置之第二個實施例將被描述。第13圖顯示半導體裝置的第二實施例。
如第13圖所示之一種半導體裝置60,其中包含一第一半導體構件61和一第二半導體構件62。然後,第一半導體構件61藉由覆晶連接安裝在所述第二半導體構件62。
第一半導體構件61包含電極45形成於第一半導體構 件61和銅柱形凸塊41形成於電極45。值得注意的是,第一半導體構件61是和如上所述第3圖所示之第一實施例的半導體構件31具有相同的結構。所以省略詳細的說明。
第二半導體構件62包含電極47用於覆晶連接,電極47形成於凸塊下金屬層(UBM)48,和凸塊下金屬層(UBM)48形成於低熔點的焊料凸塊44。另外,所述第二半導體構件62之一端部包含一焊盤電極63用於外部連接之配線接合。半導體裝置60藉由配線電性接合於外部電子裝置,外部電子裝置藉由焊盤電極63而配線接合於第二半導體構件62。此外,保護層49設置於第二半導體構件62的表面,除了用於覆晶連接之電極47和用於配線接合之焊盤電極63。
銅柱形凸塊41之表面藉由鍍層42而塗覆。例如作為鍍層42,快閃Ni鍍層和快閃Au鍍層藉由無電方法或無電Co鍍層而構成鍍層。
焊料凸塊44藉由低熔點焊料而形成。作為低熔點焊料,如一元焊料的In,和藉由加入其它金屬至二元焊料物質而使用之低熔點二元焊料如Sn-Bi、Sn-In、Bi-In和焊料物質而形成。
Cu柱形凸塊41和焊料凸塊44之間的接觸面上形成Cu和焊料之合金層43。
此外,在第13圖所示半導體裝置60中,填充(UF)樹脂33密封半導體構件之間的整個連接面,該填充樹脂33設置於第一半導體構件61和第二半導體構件62之間。第 一半導體元件61和第二半導體元件62藉由填充(UF)樹脂33機械性連接。然後,Cu柱形凸塊41和焊料凸塊44之間的連接部而形成為填充(UF)樹脂33。因此,半導體裝置60藉由填充樹脂33填充於第一半導體構件61和第二半導體構件62之間而形成一片狀物。
5.半導體裝置製造方法之第二實施例 [第一製造方法:後續的UF樹脂之處理流程]
第14圖顯示出第13圖中所示的半導體裝置60的處理流程。
如第14圖中所示,元件如各種類之電晶體管,和配線等構成第一半導體構件61形成於半導體基底係藉由習知方法。此時,用於外部連接的電極45上形成用於覆晶連接。
電極連接到第一半導體構件61之外部設備而形成於Cu柱形凸塊41。
成形的Cu柱形凸塊41藉由無電鍍法而形成於鍍層42。
相反的表面(背面)之面用於形成不同種元件為半導體基底被切斷(背面磨削:BG)。因此,半導體基底進行切割(DC)然後第一半導體構件61被分離成單獨的芯片。
此外,藉由習知的方法,元件如各種之電晶體、配線和相似物等構成第二半導體構件62於半導體基底而形成。此時,電極47安置於第一半導體構件61而形成,並且凸塊下金屬層(UBM)48形成於電極47。
凸塊下金屬層(UBM)48藉由低熔點焊料形成於焊料凸塊44。
然後,在相反表面(背面)的面上,用於形成不同種的半導體基底上的元件被切斷(背面磨削:BG)。然後,半導體基底進行切割(DC)然後第二半導體構件62被分離成單獨的芯片。
接著,銅柱形凸塊41被納入壓觸接(接合)於焊料凸塊44,從而第一半導體構件61覆晶連接於第二半導體構件62。
覆晶連接,Cu柱形凸塊41和焊料凸塊44之間的連接部被覆蓋和填充(UF)樹脂33注入於第一半導體構件61和第二半導體構件62之間。然後,注入的UF樹脂33被加熱和硬化(固化)。
藉由上述製程,第二實施例之半導體裝置60能製造而得。
值得注意的是,Cu柱形凸塊41之形成,焊料凸塊44之形成,以及覆晶連接能藉由於第7圖至第9圖所示上述之第一實施例的相同方法而進行。
[第二製造方法:初步UF樹脂的處理流程]
接著,製造半導體裝置60之方法的一修改例於第二實施例將被描述。在修改例中,藉由填充(UF)樹脂密封二個半導體構件是不同於上述製造方法。
第15圖顯示出在填充(UF)樹脂密封過程中改變的處 理流程。
如第15圖所示,元件如各種之電晶體、配線和相似物等構成第一半導體構件61於半導體基底藉由習知方法而形成。此時,用於外部連接的電極45藉由覆晶連接而形成。
Cu柱形凸塊41形成於電極而連接至第一半導體構件61的外部設備。
成形的該銅柱形凸塊41藉由無電鍍方法而形成於該鍍層42。
成形的該Cu柱形凸塊41被覆蓋於該第一半導體構件61之全表面和該第一半導體構件61之全表面層疊該填充(UF)樹脂33。
在相反表面(背面)的面上,用於形成不同種的半導體基底上的元件被切斷(背面磨削:BG)。然後,半導體基底進行切割(DC),該第一半導體構件61被分離成單獨的芯片。
此外,藉由習知的方法,元件如各種之電晶體、配線和相似物等構成該第二半導體構件62於半導體基底而形成。此時,該電極47安置於該第一半導體構件61而形成,並且該電極47形成於凸塊下金屬層(UBM)48。
該凸塊下金屬層(UBM)48使用低熔點焊料而形成於該焊料凸塊44。
然後,在相反表面(背面)的面上,用於形成不同種的半導體基底上的元件被切斷(背面磨削:BG)。然後,半導 體基底進行切割(DC),該第二半導體構件62被分離成單獨的芯片。
接著,該銅柱形凸塊41被納入壓合接觸(接合)於的該焊料凸塊44,從而該第一半導體構件61覆晶連接於該第二半導體構件62。連接後,注入之填充(UF)樹脂被加熱和硬化。
藉由上述製程,該第二實施例之半導體裝置60能製造而得。
6.電子裝置 [相機]
上面描述半導體裝置之實施例可實施於電子裝置,包括一半導體記憶體,一相機系統如數位相機和攝影相機、具有攝像功能的行動電話、或具有圖像功能的其他設備、或相似物等。在下文中,將描述以相機作為配置實例之電子裝置。
第16圖顯示攝影相機能夠拍攝靜止圖像或移動圖像的配置。
本實施例之一種照相機70包含一固態成像裝置71,一光學系統72能引導入射光至固態成像裝置71之光接收傳感器單元,一快門裝置73設置於固態成像裝置71和光學系統72之間,和一驅動電路74能驅動固態成像裝置71。另外,照相機70包含一信號處理電路75能處理固態成像裝置71的輸出信號。
該固態成像裝置71使用半導體裝置而製造,固態成像裝置包含上述藉由覆晶連接之銅柱形凸塊。
該光學系統(光學透鏡)72聚焦於一目標之表面(圖未示)的該固態成像裝置71之影像光線(入射光)。結果,信號電荷累積於該固態成像裝置71的一預設時間週期。值得注意的是,該光學系統72可以包含多個光學透鏡之光學透鏡組而組成。此外,該快門裝置73利用該固態成像裝置71的入射光而控制的光照射期間和遮光期間的。
該驅動電路74供給一驅動信號至該固態成像裝置71和該快門裝置73。然後,該驅動電路74控制一信號輸出操作至該固態成像裝置71之該信號處理電路75,以及一個快門操作的該快門裝置73所提供的驅動信號而控制。也就是說,在這個例子中,基於從驅動電路74所提供的驅動信號(定時信號),信號傳輸操作從該固態成像裝置71至該信號處理電路75而執行。
該信號處理電路75對從固態成像裝置71傳送而來的各種信號進行處理。然後,進行信號(圖像信號)處理的各種信號被儲存於如記憶體之儲存介質(圖未示)或輸出到監視器(圖未示)。
值得注意的是,公開揭露可以配置如下。
(1)一種半導體裝置,包括一半導體構件、一形成於半導體構件的Cu柱形凸塊、以及一經配置而電性連接於該Cu柱形凸塊的焊料凸塊。
(2)如第(1)項所述的半導體裝置,更包括一鍍層,該 鍍層形成於該銅柱形凸塊之一表面。
(3)如第(1)項或第(2)項所述的半導體裝置,其中該焊料凸塊包括選自In、SnBi、SnIn、及BiIn的至少一種。
(4)如第(2)項或第(3)項所述的半導體裝置,其中該鍍層包括Ni、Au、和Co鍍層中之一個鍍層。
(5)一種半導體裝置的製造方法,包括:於一半導體構件形成一Cu柱形凸塊;以及覆晶連接該Cu柱形凸塊至一焊料凸塊。
(6)如第(5)項所述的製造半導體裝置的方法,更包括藉由無電鍍法而形於該Cu柱形凸塊之一表面上成一鍍層。
(7)如第(5)項或第(6)項所述的製造半導體裝置的方法,其中係於覆晶連接期間和之後於200℃或更低執行加熱。
(8)一種電子裝置,包括第(1)項至第(4)項所述任一項之一半導體裝置,和一信號處理電路經配置而處理該半導體裝置之一輸出信號。
本公開包含2011年8月17日向日本專利局提出申請的日本優先權專利JP2011-178390之相關內容,全部內容通過引用結合於此。
凡精於此項技藝者當可依據設計要求和其他因素而作其它種種之改良、組合、次組合、和變更,惟舉凡依本發明申請專利範圍所作之均等變化與修飾,皆應仍屬本發明專利涵蓋之範圍內。
11‧‧‧Au柱形凸塊
12‧‧‧Sn凸塊
13‧‧‧半導體構件
14‧‧‧電極
15‧‧‧保護層
16‧‧‧配線基板
17‧‧‧電極
18‧‧‧凸塊下金屬層
19‧‧‧保護層
20‧‧‧金屬間化合物
21‧‧‧Au柱形凸塊
22‧‧‧In凸塊
23‧‧‧AuIn合金
24‧‧‧裂紋
30‧‧‧半導體裝置
31‧‧‧半導體構件
32‧‧‧玻璃基板
33‧‧‧填充樹脂
34‧‧‧配線層
35‧‧‧電極
36‧‧‧焊料球
37‧‧‧配線基板
38‧‧‧光學構件
41‧‧‧Cu柱形凸塊
42‧‧‧鍍層
43‧‧‧合金層
44‧‧‧焊料凸塊
45‧‧‧電極
46‧‧‧保護層
47‧‧‧電極
48‧‧‧凸塊下金屬層
49‧‧‧保護層
51‧‧‧銅線
52‧‧‧毛細管
53‧‧‧金屬障壁層
54‧‧‧抗蝕劑層
55‧‧‧光罩
60‧‧‧半導體裝置
61‧‧‧第一半導體構件
62‧‧‧第二半導體構件
63‧‧‧焊盤電極
70‧‧‧照相機
71‧‧‧固態成像裝置
72‧‧‧光學系統
73‧‧‧快門裝置
74‧‧‧驅動電路
75‧‧‧信號處理電路
第1A圖係顯示一柱形凸塊和焊料凸塊覆晶連接前之結構配置,及第1B圖係顯示該柱形凸塊和該焊料凸塊覆晶連接後之結構配置。
第2A圖係另一顯示該柱形凸塊和該焊料凸塊覆晶連接前結構配置,及第2B圖係另一顯示該柱形凸塊和該焊料凸塊覆晶連接後結構配製。
第3圖係顯示根據第一實施例之一半導體裝置的結構配製之剖面圖。
第4圖係顯示一Cu柱形凸塊覆晶連接前之結構配置。
第5圖係顯示之該Cu柱形凸塊和該焊料凸塊覆晶連接後結構配置。
第6圖係顯示根據第一實施例的該半導體裝置的一處理流程圖。
第7A至7C圖係該Cu柱形凸塊製造處理之圖。
第8A至8D圖係之該焊料凸塊製造處理之圖。
第9A至9C圖係由該銅柱形凸塊和該焊料凸塊經覆晶連接的製程圖。
第10圖係顯示根據第一實施例的該半導體裝置的一修改例處理之處理流程圖。
第11A至11C圖係顯示由Cu柱形凸塊和該焊料凸塊經覆晶連接之處理圖。
第12圖係顯示根據第一實施例的該半導體裝置之一修改例的結構配置。
第13圖係顯示根據第二實施例的一半導體裝置的結 構配置之剖面圖。
第14圖係顯示根據第二實施例的該半導體裝置的處理流程圖。
第15圖係顯示根據第二實施例的該半導體裝置的一修改例之處理流程。
第16圖係顯示一電子裝置之結構配置。
30‧‧‧半導體裝置
31‧‧‧半導體構件
32‧‧‧玻璃基板
33‧‧‧填充樹脂
34‧‧‧配線層
35‧‧‧電極
36‧‧‧焊料球
41‧‧‧Cu柱形凸塊
42‧‧‧鍍層
43‧‧‧合金層
44‧‧‧焊料凸塊
45‧‧‧電極
46‧‧‧保護層
47‧‧‧電極
48‧‧‧凸塊下金屬層
49‧‧‧保護層

Claims (7)

  1. 一種半導體裝置,包含:一基板;一半導體電路構件,與該基板分開;一Cu柱形凸塊,形成於該半導體電路構件上;一焊料凸塊,形成於該基板上且經配置而電性連接於該Cu柱形凸塊;一鍍層,該鍍層直接形成於該Cu柱形凸塊之一外表面上;以及一合金層,形成於該Cu柱形凸塊與該焊料凸塊之間且緊鄰該Cu柱形凸塊與該焊料凸塊之每一者,使得該合金層接觸該Cu柱形凸塊與該焊料凸塊之每一者,其中,該鍍層直接形成於不與該焊料凸塊接觸的該Cu柱形凸塊的該外表面之一部分上。
  2. 如申請專利範圍第1項所述的半導體裝置,其中該焊料凸塊包含選自In、SnBi、SnIn、及BiIn的至少一種。
  3. 如申請專利範圍第1項所述的半導體裝置,其中該鍍層包含Ni、Au、和Co鍍層中之一個鍍層。
  4. 如申請專利範圍第1項所述的半導體裝置,更包含一電極,該電極直接形成於該半導體電路構件上,其中該Cu柱形凸塊直接形成於該電極上。
  5. 一種製造半導體裝置的方法,包含:形成一基板;形成一半導體電路構件,該半導體電路構件與該基板 分開;於該半導體電路構件上形成一Cu柱形凸塊;於該基板上形成一焊料凸塊,且電性連接該焊料凸塊於該Cu柱形凸塊;藉由無電鍍法,直接於該Cu柱形凸塊之一外表面上形成一鍍層;以及形成一合金層於該Cu柱形凸塊與該焊料凸塊之間且緊鄰該Cu柱形凸塊與該焊料凸塊之每一者,使得該合金層接觸該Cu柱形凸塊與該焊料凸塊之每一者,其中,該鍍層直接形成於不與該焊料凸塊接觸的該Cu柱形凸塊的該外表面之一部分上。
  6. 如申請專利範圍第5項所述的半導體裝置的製造方法,其中係於該電性連接期間和之後於200℃或更低執行加熱。
  7. 一種電子裝置,包含:一半導體裝置,包含一基板、與該基板分開的一半導體電路構件、一形成於該半導體電路構件上的Cu柱形凸塊、和一形成於該基板上且經配置而電性連接於該Cu柱形凸塊的焊料凸塊;一信號處理電路,經配置而處理該半導體裝置之一輸出信號;一鍍層,該鍍層直接形成於該Cu柱形凸塊之一外表面上;以及一合金層,形成於該Cu柱形凸塊與該焊料凸塊之間且 緊鄰該Cu柱形凸塊與該焊料凸塊之每一者,使得該合金層接觸該Cu柱形凸塊與該焊料凸塊之每一者,其中,該鍍層直接形成於不與該焊料凸塊接觸的該Cu柱形凸塊的該外表面之一部分上。
TW101128440A 2011-08-17 2012-08-07 半導體裝置,製造半導體裝置的方法,以及電子裝置 TWI523175B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011178390A JP6035714B2 (ja) 2011-08-17 2011-08-17 半導体装置、半導体装置の製造方法、及び、電子機器

Publications (2)

Publication Number Publication Date
TW201320270A TW201320270A (zh) 2013-05-16
TWI523175B true TWI523175B (zh) 2016-02-21

Family

ID=47712067

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101128440A TWI523175B (zh) 2011-08-17 2012-08-07 半導體裝置,製造半導體裝置的方法,以及電子裝置

Country Status (5)

Country Link
US (2) US9105625B2 (zh)
JP (1) JP6035714B2 (zh)
KR (1) KR101996676B1 (zh)
CN (1) CN102956603A (zh)
TW (1) TWI523175B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6082282B2 (ja) * 2013-03-12 2017-02-15 スタンレー電気株式会社 半導体発光装置
TWI600129B (zh) 2013-05-06 2017-09-21 奇景光電股份有限公司 玻璃覆晶接合結構
JP6311407B2 (ja) * 2014-03-31 2018-04-18 日本電気株式会社 モジュール部品及びその製造方法
TWI488244B (zh) * 2014-07-25 2015-06-11 Chipbond Technology Corp 具有凸塊結構的基板及其製造方法
WO2016019335A1 (en) * 2014-08-01 2016-02-04 Kyocera America, Inc. Chip attachment system
JP6314070B2 (ja) * 2014-10-07 2018-04-18 新光電気工業株式会社 指紋認識用半導体装置、指紋認識用半導体装置の製造方法及び半導体装置
KR101778498B1 (ko) 2014-10-10 2017-09-13 이시하라 케미칼 가부시키가이샤 합금 범프의 제조방법
US11018099B2 (en) * 2014-11-26 2021-05-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having a conductive bump with a plurality of bump segments
WO2016100662A1 (en) * 2014-12-19 2016-06-23 Glo Ab Light emitting diode array on a backplane and method of making thereof
TWI632653B (zh) * 2017-02-15 2018-08-11 財團法人工業技術研究院 電子封裝結構
US11114387B2 (en) 2017-02-15 2021-09-07 Industrial Technology Research Institute Electronic packaging structure

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07112041B2 (ja) * 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
JP2001060602A (ja) * 1999-08-23 2001-03-06 Fuji Electric Co Ltd フリップチップ実装構造及びその製造方法
US6713318B2 (en) * 2001-03-28 2004-03-30 Intel Corporation Flip chip interconnection using no-clean flux
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
DE10392377T5 (de) * 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer
JP4136844B2 (ja) * 2002-08-30 2008-08-20 富士電機ホールディングス株式会社 電子部品の実装方法
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US7276801B2 (en) * 2003-09-22 2007-10-02 Intel Corporation Designs and methods for conductive bumps
JP4497913B2 (ja) 2003-12-17 2010-07-07 Sumco Techxiv株式会社 単結晶半導体製造用ヒータ装置
US7402908B2 (en) * 2005-05-05 2008-07-22 Micron Technology, Inc. Intermediate semiconductor device structures
KR100719905B1 (ko) * 2005-12-29 2007-05-18 삼성전자주식회사 Sn-Bi계 솔더 합금 및 이를 이용한 반도체 소자
JP2009054790A (ja) * 2007-08-27 2009-03-12 Oki Electric Ind Co Ltd 半導体装置
JP5187832B2 (ja) 2008-03-11 2013-04-24 田中電子工業株式会社 半導体装置
US20090246911A1 (en) 2008-03-27 2009-10-01 Ibiden, Co., Ltd. Substrate for mounting electronic components and its method of manufacture
JP4697258B2 (ja) * 2008-05-09 2011-06-08 ソニー株式会社 固体撮像装置と電子機器
JP4941490B2 (ja) * 2009-03-24 2012-05-30 ソニー株式会社 固体撮像装置、及び電子機器
EP2234387B8 (en) * 2009-03-24 2012-05-23 Sony Corporation Solid-state imaging device, driving method of solid-state imaging device, and electronic apparatus
JP2010263014A (ja) * 2009-04-30 2010-11-18 Panasonic Corp 半導体装置
JP2011023568A (ja) 2009-07-16 2011-02-03 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US8659155B2 (en) * 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US20110186989A1 (en) * 2010-02-04 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Bump Formation Process

Also Published As

Publication number Publication date
TW201320270A (zh) 2013-05-16
KR20130020565A (ko) 2013-02-27
CN102956603A (zh) 2013-03-06
JP6035714B2 (ja) 2016-11-30
US20130043585A1 (en) 2013-02-21
US20150303167A1 (en) 2015-10-22
US9105625B2 (en) 2015-08-11
KR101996676B1 (ko) 2019-07-04
JP2013042005A (ja) 2013-02-28

Similar Documents

Publication Publication Date Title
TWI523175B (zh) 半導體裝置,製造半導體裝置的方法,以及電子裝置
JP5435849B2 (ja) 基板に取り付けられたスタッドバンプを伴う、フリップチップパッケージング用の可融性入出力相互接続システムおよび方法
US8101866B2 (en) Packaging substrate with conductive structure
US20110001250A1 (en) Method and structure for adhesion of intermetallic compound (imc) on cu pillar bump
US9397137B2 (en) Interconnect structure for CIS flip-chip bonding and methods for forming the same
US8779300B2 (en) Packaging substrate with conductive structure
KR102305916B1 (ko) 프리-코팅 상호연결 요소를 포함하는 플립-칩 조립 방법
TWI502666B (zh) Electronic parts mounting body, electronic parts, substrate
JP5217043B2 (ja) 半導体装置の製造方法
US20050042872A1 (en) Process for forming lead-free bump on electronic component
US9601374B2 (en) Semiconductor die assembly
JP2007208056A (ja) 半導体装置の製造方法
TWI709213B (zh) 封裝結構及組件連接的方法
KR100494023B1 (ko) 반도체 촬상소자 패키지 및 그 제조방법
US9190377B2 (en) Metal coating for indium bump bonding
JP2017092341A (ja) 電極構造、接合方法及び半導体装置
JP2023065027A (ja) 半導体受光素子、半導体受光素子の製造方法および検査方法
JP2019029441A (ja) 光半導体ユニットの製造方法
JP2007208055A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees