JP2012506149A - 低いエッチング速度の誘電体ライナを用いたギャップ充填の改善 - Google Patents

低いエッチング速度の誘電体ライナを用いたギャップ充填の改善 Download PDF

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Publication number
JP2012506149A
JP2012506149A JP2011532139A JP2011532139A JP2012506149A JP 2012506149 A JP2012506149 A JP 2012506149A JP 2011532139 A JP2011532139 A JP 2011532139A JP 2011532139 A JP2011532139 A JP 2011532139A JP 2012506149 A JP2012506149 A JP 2012506149A
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layer
liner
dielectric
boron
dielectric material
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JP2012506149A5 (enExample
Inventor
ヨン ス クォン，
ビ チャン，
アンチュアン ワン，
ヨン， エス． リー，
ミハエラ バルシーヌ，
リ−クン シャ，
ジン ホ チョン，
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Applied Materials Inc
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Applied Materials Inc
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Publication of JP2012506149A5 publication Critical patent/JP2012506149A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
JP2011532139A 2008-10-16 2009-09-29 低いエッチング速度の誘電体ライナを用いたギャップ充填の改善 Pending JP2012506149A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10607608P 2008-10-16 2008-10-16
US61/106,076 2008-10-16
US12/437,256 US7910491B2 (en) 2008-10-16 2009-05-07 Gapfill improvement with low etch rate dielectric liners
US12/437,256 2009-05-07
PCT/US2009/058832 WO2010045021A2 (en) 2008-10-16 2009-09-29 Gapfill improvement with low etch rate dielectric liners

Publications (2)

Publication Number Publication Date
JP2012506149A true JP2012506149A (ja) 2012-03-08
JP2012506149A5 JP2012506149A5 (enExample) 2012-11-15

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JP2011532139A Pending JP2012506149A (ja) 2008-10-16 2009-09-29 低いエッチング速度の誘電体ライナを用いたギャップ充填の改善

Country Status (6)

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US (1) US7910491B2 (enExample)
JP (1) JP2012506149A (enExample)
KR (1) KR101161098B1 (enExample)
CN (1) CN102187450A (enExample)
TW (1) TWI396253B (enExample)
WO (1) WO2010045021A2 (enExample)

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JP2014175596A (ja) * 2013-03-12 2014-09-22 Hitachi Kokusai Electric Inc 半導体装置の製造方法、基板処理装置およびプログラム
JP2014183223A (ja) * 2013-03-19 2014-09-29 Hitachi Kokusai Electric Inc 半導体装置の製造方法、基板処理装置およびプログラム
JP2014199942A (ja) * 2009-10-27 2014-10-23 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． バルクＦｉｎＦＥＴ中のＳｉフィンのフィン下部近くのＳＴＩ形状
KR20170135902A (ko) * 2015-04-03 2017-12-08 어플라이드 머티어리얼스, 인코포레이티드 열 cvd 동안 리간드들을 동시-유동시킴으로써 고 종횡비 트렌치들을 충진하는 프로세스
WO2024157821A1 (ja) * 2023-01-27 2024-08-02 東京エレクトロン株式会社 成膜方法及び成膜装置

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