JP2012504263A5 - - Google Patents

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Publication number
JP2012504263A5
JP2012504263A5 JP2011528145A JP2011528145A JP2012504263A5 JP 2012504263 A5 JP2012504263 A5 JP 2012504263A5 JP 2011528145 A JP2011528145 A JP 2011528145A JP 2011528145 A JP2011528145 A JP 2011528145A JP 2012504263 A5 JP2012504263 A5 JP 2012504263A5
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JP
Japan
Prior art keywords
clock signal
duty cycle
command
slave device
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2011528145A
Other languages
English (en)
Japanese (ja)
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JP2012504263A (ja
Filing date
Publication date
Priority claimed from US12/241,832 external-priority patent/US8181056B2/en
Priority claimed from US12/241,960 external-priority patent/US8161313B2/en
Application filed filed Critical
Priority claimed from PCT/CA2009/001271 external-priority patent/WO2010037205A1/en
Publication of JP2012504263A publication Critical patent/JP2012504263A/ja
Publication of JP2012504263A5 publication Critical patent/JP2012504263A5/ja
Pending legal-status Critical Current

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JP2011528145A 2008-09-30 2009-09-17 出力遅延調整によるシリアル接続のメモリシステム Pending JP2012504263A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US12/241,960 2008-09-30
US12/241,832 US8181056B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with output delay adjustment
US12/241,960 US8161313B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with duty cycle correction
US12/241,832 2008-09-30
PCT/CA2009/001271 WO2010037205A1 (en) 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012193816A Division JP5599852B2 (ja) 2008-09-30 2012-09-04 出力遅延調整によるシリアル接続のメモリシステム

Publications (2)

Publication Number Publication Date
JP2012504263A JP2012504263A (ja) 2012-02-16
JP2012504263A5 true JP2012504263A5 (enrdf_load_stackoverflow) 2012-10-25

Family

ID=42072981

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2011528145A Pending JP2012504263A (ja) 2008-09-30 2009-09-17 出力遅延調整によるシリアル接続のメモリシステム
JP2012193816A Expired - Fee Related JP5599852B2 (ja) 2008-09-30 2012-09-04 出力遅延調整によるシリアル接続のメモリシステム

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012193816A Expired - Fee Related JP5599852B2 (ja) 2008-09-30 2012-09-04 出力遅延調整によるシリアル接続のメモリシステム

Country Status (6)

Country Link
EP (1) EP2329496A4 (enrdf_load_stackoverflow)
JP (2) JP2012504263A (enrdf_load_stackoverflow)
KR (1) KR20110081958A (enrdf_load_stackoverflow)
CN (1) CN102165529B (enrdf_load_stackoverflow)
TW (1) TW201027556A (enrdf_load_stackoverflow)
WO (1) WO2010037205A1 (enrdf_load_stackoverflow)

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US8665665B2 (en) * 2011-03-30 2014-03-04 Mediatek Inc. Apparatus and method to adjust clock duty cycle of memory
US9257164B2 (en) * 2013-03-14 2016-02-09 Altera Corporation Circuits and methods for DQS autogating
JP6232313B2 (ja) * 2014-02-25 2017-11-15 新日本無線株式会社 同期式シリアル通信方法およびスレーブ装置
KR102757627B1 (ko) * 2016-09-23 2025-01-23 삼성전자주식회사 케스-케이드 연결 구조로 레퍼런스 클록을 전달하는 스토리지 장치들을 포함하는 전자 장치
KR20190009534A (ko) * 2017-07-19 2019-01-29 에스케이하이닉스 주식회사 반도체장치
KR101999125B1 (ko) * 2017-11-24 2019-07-11 파밀넷 주식회사 Rs-422와 rs-485 시리얼 통신을 위한 출력신호 자동 제어기
KR102679157B1 (ko) 2018-10-30 2024-06-27 삼성전자주식회사 모드 레지스터 쓰기 명령을 이용하여 쓰기 클럭의 듀티 사이클의 트레이닝을 수행하는 시스템 온 칩, 시스템 온 칩의 동작 방법, 및 시스템 온 칩을 포함하는 전자 장치
JP2020155841A (ja) * 2019-03-18 2020-09-24 キオクシア株式会社 半導体集積回路及び送信装置
US10937468B2 (en) * 2019-07-03 2021-03-02 Micron Technology, Inc. Memory with configurable die powerup delay
CN111339024A (zh) * 2020-04-17 2020-06-26 深圳比特微电子科技有限公司 计算装置以及计算系统
CN112332881B (zh) * 2020-10-19 2022-04-26 深圳市信锐网科技术有限公司 使能电路及通信装置
CN112698683B (zh) * 2020-12-28 2024-07-19 深圳市合信自动化技术有限公司 一种可配置总线解决传输延时数据出错的方法、装置及plc
JP2022141178A (ja) * 2021-03-15 2022-09-29 キオクシア株式会社 メモリシステム
JPWO2023089778A1 (enrdf_load_stackoverflow) * 2021-11-19 2023-05-25
US20240312511A1 (en) * 2023-03-14 2024-09-19 Powerchip Semiconductor Manufacturing Corporation Stacked memory with a timing adjustment function

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JP2000148674A (ja) * 1998-11-09 2000-05-30 Sharp Corp シリアルデータ伝送方法
US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
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JP2003140962A (ja) * 2001-10-30 2003-05-16 Mitsubishi Electric Corp 信号送受信システム
JP3843002B2 (ja) * 2001-11-26 2006-11-08 株式会社ルネサステクノロジ 可変遅延回路及びその可変遅延回路を用いたシステムｌｓｉ
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US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7389375B2 (en) * 2004-07-30 2008-06-17 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
US7352219B2 (en) * 2005-08-30 2008-04-01 Infineon Technologies Ag Duty cycle corrector
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