JP2012504263A5

JP2012504263A5 -

Info

Publication number: JP2012504263A5
Application number: JP2011528145A
Authority: JP
Filing date: 2009-09-17
Publication date: 2012-10-25

Claims

A method in a slave device among a plurality of serially connected slave devices,
Receiving a command from a master device specifying an adjustment to the clock duty cycle;
Receiving an input clock signal;
Generating a duty cycle corrected clock signal from the input clock signal by the command;
Outputting the duty cycle corrected clock signal.

The method of claim 1, wherein the slave device is a memory device and the master device is a memory controller.

Receiving a command from a master device specifying how the slave device should adjust a delay to be applied to at least one signal output by the slave device;
Receiving at least one input signal, wherein the at least one input signal comprises at least the input clock signal;
Generating a delayed version of the input signal by the command for each of the at least one input signal;
Outputting the delayed version of the input signal, wherein the delayed version of the input clock signal comprises a delayed version of the duty cycle corrected clock signal. The method of claim 1.

Receiving a command from a master device that specifies an adjustment to a clock duty cycle includes receiving a command including a command identifier that regards the command as a duty cycle correction command, and the command adjusts the duty cycle. The method of claim 1, further comprising data indicating what to do.

5. The method of claim 4, wherein receiving a command further comprises receiving a device address indicating which device acting as a slave device is to execute the command.

If the command has a device address that matches a device address of the slave device, performing the step of generating the duty cycle corrected clock signal according to the command;
6. The method of claim 5, further comprising: when the command has a device address that is a broadcast device address, generating the duty cycle corrected clock signal according to the command.

The step of generating a duty cycle corrected clock signal is:
a) generating a half rate clock signal from the input clock signal;
b) delaying the half-rate clock signal by a selected one of a plurality of delays to generate a delayed half-rate clock signal;
5. The method of claim 4, comprising: c) combining the half rate clock signal with the delayed half rate clock signal to generate the duty cycle corrected clock signal.

8. The method of claim 7, wherein the data indicating how to adjust the duty cycle correction includes an indication of the selected one of the plurality of delays.

A method in a memory system comprising a master device and a plurality of serially connected slave devices including at least a first slave device and a lowest slave device comprising:
In the master device,
a) outputting a first clock signal that functions as an input clock signal for the first slave device;
b) receiving a second clock signal which is an output clock signal of the lowest slave device;
c) generating a duty cycle correction command according to a duty cycle of the second clock signal, and outputting the duty cycle correction command;
In the first slave device of the plurality of serially connected slave devices,
a) receiving the first clock signal from the master device as the input clock signal of the first slave device;
b) generating an output clock signal from the input signal;
In each other slave device of the plurality of serially connected slave devices,
a) receiving the output clock signal of a preceding slave device as an input clock signal of the slave device;
b) generating an output clock signal from the input clock signal;
In each of at least one of the plurality of serially connected devices acting as a slave device,
a) receiving the duty cycle correction command;
b) generating a duty cycle corrected clock signal from the input clock signal by the duty cycle correction command;
c) outputting the duty cycle corrected clock signal as the output clock signal of the slave device.

The method of claim 9, wherein each slave device is a memory device and the master device is a memory controller.

In the master device,
a) outputting at least one output signal, wherein the at least one output signal includes the first clock signal functioning as an input clock signal of the first slave device;
b) receiving a second clock signal which is an output clock signal of the lowest slave device;
c) determining an amount of phase offset between the first clock signal and the second clock signal;
d) generating an output delay adjustment command in response to the phase offset between the first clock signal and the second clock signal, and outputting the output delay adjustment command. 10. The method according to 10.

The step of generating a duty cycle correction command according to the duty cycle of the second clock signal and outputting the duty cycle correction command is performed by any one of the plurality of serially connected slave devices. 11. A method according to claim 9 or 10, comprising the step of generating a duty cycle correction command for execution.

The step of generating a duty cycle correction command according to the duty cycle of the second clock signal and outputting the duty cycle correction command is performed by all of the plurality of serially connected slave devices. 13. The method of claim 12, comprising the step of generating

The step of receiving the duty cycle correction command includes receiving a command including a command identifier that regards the command as a duty cycle correction command and including data indicating how to adjust the duty cycle. The method described in 1.

The step of generating a duty cycle corrected clock signal is:
a) generating a half rate clock signal from the input clock signal;
b) delaying the half-rate clock signal by a selected one of a plurality of delays to generate a delayed half-rate clock signal;
15. The method of claim 14, comprising: c) combining the half rate clock signal with the delayed half rate clock signal to generate the duty cycle corrected clock signal.

16. The method of claim 15, wherein the data indicating how to adjust the duty cycle correction includes an indication of the selected one of the plurality of delays.

A slave device for use in a configuration having a plurality of serially connected slave devices,
Command input to receive commands from the master device that specify adjustments to the duty cycle;
A clock input for receiving an input clock signal; and
A duty cycle correction circuit for generating a duty cycle corrected clock signal from the clock input by the control command;
A slave device comprising: a clock output for outputting the clock signal with the duty cycle corrected.

The slave device according to claim 17, wherein the slave device is a memory device.

The command input is also for receiving a command from the master device that specifies an adjustment for output delay;
The slave device further includes an output delay adjustment circuit for generating a delayed clock signal from the duty cycle corrected clock signal according to the command,
The clock output for outputting the duty cycle corrected clock signal outputs the delayed clock signal;
The slave device according to claim 17 or 18.

A command processing circuit for processing the command;
The command is
A command identifier that regards the command as a duty cycle correction command;
Data indicating how the duty cycle should be adjusted;
The slave device according to claim 17 or 18.

A device address register;
The command further includes a device address indicating which slave device should execute the command, and the slave device is configured to execute the command if the device address matches the contents of the device address register. Being
21. The slave device according to claim 20.

The duty cycle correction circuit includes:
a) a clock divider circuit that generates a half rate clock signal from the input clock signal;
b) a delay circuit that delays the half-rate clock signal by a selected one of a plurality of delays to generate a delayed half-rate clock signal;
22. A combiner that combines c) the half rate clock signal with the delayed half rate clock signal to generate the duty cycle corrected clock signal. Slave device.

The delay circuit includes M unit delay elements with M> = 2, and the duty cycle correction circuit includes:
When selecting the number of unit delay elements to be active when delaying the half rate clock signal to generate the delayed half rate clock signal, N> = 1 N 23. The slave device of claim 22, further comprising an N to M decoder that decodes a signal received on the input line.

A plurality of serially connected devices serving as slave devices according to claim 17 comprising at least a first slave device and a lowest slave device;
A master device connected to the first slave device and the lowest slave device,
A master device configured to output a first clock signal that functions as an input clock signal for the first slave device; and
A clock input for receiving a second clock signal that is an output clock signal of the lowest slave device;
A duty detector for determining a duty cycle of the second clock signal;
A command generator that generates a duty cycle correction command that specifies an adjustment to a clock duty cycle in response to the duty cycle of the second clock signal,
The first slave device of the plurality of serially connected devices acting as a slave device is:
a) receiving the first clock signal from the master device as the input clock signal of the first slave device;
b) generating an output clock signal from the input clock signal;
The other respective slave devices of the plurality of serially connected devices that serve as slave devices are:
a) receiving the output clock signal of the preceding slave device as an input clock signal of the slave device;
b) generating an output clock signal from the input clock signal;
At least one of the plurality of serially connected slave devices is:
a) receiving the duty cycle correction command,
b) Generate a clock signal with a duty cycle corrected by the control command,
c) outputting the duty cycle corrected clock signal as the output clock signal of the slave device;
system.

25. The system of claim 24, wherein the system is a memory system, each slave device is a memory device, and the master device is a memory controller.

A phase detector for determining an amount of phase offset between the first clock signal and the second clock signal;
The command generator also generates an output delay adjustment command according to the amount of phase offset,
Of the plurality of serially connected slave devices, the first slave device is:
a) receiving the first clock signal from the master device as the input clock signal of the first slave device;
b) generating an output clock signal from the input clock signal;
Each other slave device of the plurality of serially connected slave devices is:
a) receiving the output clock signal of the preceding slave device as an input clock signal of the slave device;
b) generating an output clock signal from the input clock signal;
At least one of the plurality of serially connected slave devices is:
a) receiving the output delay adjustment command,
b) generating the output clock signal of the device by delaying the input clock signal of the device according to the control command;
The memory system according to claim 24 or 25.

The command generator generates a duty cycle correction command in response to a duty cycle of the second clock signal and is executed by a designated one of the plurality of serially connected devices acting as a slave device 26. The memory system of claim 24 or 25, configured to output the duty cycle correction command by generating a correction command.

The command generator generates a duty cycle correction command according to the duty cycle of the second clock signal and generates a duty cycle correction command for execution by all of the plurality of serially connected devices acting as slave devices 26. The memory system according to claim 24, wherein the memory system is configured to output the duty cycle correction command.

25. Receiving the duty cycle correction command includes receiving a command including a command identifier that regards the command as a duty cycle correction command and including data indicating how to adjust the duty cycle. 29. The memory system according to any one of items 28 to 28.