JP2012004307A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2012004307A5 JP2012004307A5 JP2010137461A JP2010137461A JP2012004307A5 JP 2012004307 A5 JP2012004307 A5 JP 2012004307A5 JP 2010137461 A JP2010137461 A JP 2010137461A JP 2010137461 A JP2010137461 A JP 2010137461A JP 2012004307 A5 JP2012004307 A5 JP 2012004307A5
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- wiring region
- wafer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims 33
- 238000004519 manufacturing process Methods 0.000 claims 13
- 239000004065 semiconductor Substances 0.000 claims 13
- 238000007781 pre-processing Methods 0.000 claims 5
- 238000000034 method Methods 0.000 claims 3
- 238000010030 laminating Methods 0.000 claims 2
- 238000005498 polishing Methods 0.000 claims 2
- 238000006073 displacement reaction Methods 0.000 claims 1
- 238000004070 electrodeposition Methods 0.000 claims 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010137461A JP5505118B2 (ja) | 2010-06-16 | 2010-06-16 | 半導体デバイスを製造する方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010137461A JP5505118B2 (ja) | 2010-06-16 | 2010-06-16 | 半導体デバイスを製造する方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012004307A JP2012004307A (ja) | 2012-01-05 |
| JP2012004307A5 true JP2012004307A5 (enExample) | 2013-10-10 |
| JP5505118B2 JP5505118B2 (ja) | 2014-05-28 |
Family
ID=45535975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010137461A Active JP5505118B2 (ja) | 2010-06-16 | 2010-06-16 | 半導体デバイスを製造する方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5505118B2 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5850412B2 (ja) * | 2012-10-02 | 2016-02-03 | 株式会社デンソー | 半導体装置の製造システム及び半導体装置の製造方法 |
| JP6805640B2 (ja) * | 2016-08-29 | 2020-12-23 | 株式会社ニコン | 積層装置、薄化装置、露光装置制御装置、プログラム及び積層体の製造方法 |
| KR102656249B1 (ko) * | 2017-11-28 | 2024-04-11 | 가부시키가이샤 니콘 | 적층 기판의 제조 방법 및 제조 장치 |
| JP7721471B2 (ja) * | 2022-03-22 | 2025-08-12 | キオクシア株式会社 | 半導体装置およびその製造方法 |
| CN118841342B (zh) * | 2024-06-18 | 2025-02-25 | 昆山麦普恩精密组件有限公司 | 一种半导体零配件表面处理的控制方法及系统 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4720469B2 (ja) * | 2005-12-08 | 2011-07-13 | 株式会社ニコン | 貼り合わせ半導体装置製造用の露光方法 |
| JP2007214402A (ja) * | 2006-02-10 | 2007-08-23 | Cmk Corp | 半導体素子及び半導体素子内蔵型プリント配線板 |
| JP5512102B2 (ja) * | 2007-08-24 | 2014-06-04 | 本田技研工業株式会社 | 半導体装置 |
-
2010
- 2010-06-16 JP JP2010137461A patent/JP5505118B2/ja active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9799619B2 (en) | Electronic device having a redistribution area | |
| US9086632B2 (en) | Fine pattern structures having block co-polymer materials and methods of fabricating the same | |
| JP2014154800A5 (enExample) | ||
| JP2009003434A5 (enExample) | ||
| WO2010116694A3 (en) | Method of manufacturing semiconductor device | |
| TW201114009A (en) | Chip package and fabrication method thereof | |
| CN102799060B (zh) | 虚设图案以及形成虚设图案的方法 | |
| JP2012004307A5 (enExample) | ||
| JP2015070058A (ja) | 積層薄膜キャパシタの製造方法 | |
| JP2015099885A (ja) | 半導体装置および半導体装置の製造方法 | |
| KR102065648B1 (ko) | 반도체 패키지 | |
| KR20140081544A (ko) | 돌출부를 구비하는 반도체 칩, 이의 적층 패키지 및 적층 패키지의 제조 방법 | |
| TWI549235B (zh) | 封裝結構及其製法與定位構形 | |
| US8173539B1 (en) | Method for fabricating metal redistribution layer | |
| KR101771740B1 (ko) | 박막형 칩 소자 및 그 제조 방법 | |
| KR20140027797A (ko) | 반도체 소자의 제조 방법 | |
| TWI489600B (zh) | 半導體堆疊結構及其製法 | |
| JP2015115402A5 (enExample) | ||
| JP6214222B2 (ja) | 半導体装置の製造方法 | |
| TW201709364A (zh) | 具有嵌入式電路圖案之封裝基板、製造其之方法及包含其之半導體封裝 | |
| JP5559773B2 (ja) | 積層半導体装置の製造方法 | |
| JP2004296864A (ja) | 半導体装置及びパターン発生方法 | |
| KR101384131B1 (ko) | 3차원 집적 회로의 접합 방법 및 3차원 집적 회로 | |
| TWI658767B (zh) | 電路板的製造方法以及應用於製造其之堆疊結構 | |
| US10490550B1 (en) | Larger-area integrated electrical metallization dielectric structures with stress-managed unit cells for more capable extreme environment semiconductor electronics |