JP2011530181A - 歪み層の緩和 - Google Patents
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- 239000000463 material Substances 0.000 claims abstract description 186
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 230000002040 relaxant effect Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 84
- 238000000034 method Methods 0.000 claims description 43
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 33
- 238000010438 heat treatment Methods 0.000 claims description 33
- 230000002787 reinforcement Effects 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000010521 absorption reaction Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000012779 reinforcing material Substances 0.000 claims description 2
- 239000003351 stiffener Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 18
- 238000004519 manufacturing process Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 229910052594 sapphire Inorganic materials 0.000 description 5
- 239000010980 sapphire Substances 0.000 description 5
- 230000037303 wrinkles Effects 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000009477 glass transition Effects 0.000 description 4
- 238000001534 heteroepitaxy Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 230000005693 optoelectronics Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- -1 nitride compounds Chemical class 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004071 soot Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229910002059 quaternary alloy Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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Abstract
【選択図】 図1
Description
歪み材料層の一つの面上に第1のコンプライアント材料を有する第1の低粘度層を堆積させるステップと、
歪み材料層の他の面上に第2のコンプライアント材料を有する第2の低粘度層を堆積させて、第1のサンドイッチ構造を形成するステップと、
第1の低粘度層および第2の低粘度層のリフローが生じるように第1のサンドイッチ構造を加熱処理して、それによって少なくとも部分的に歪み材料層を緩和させるステップと、を含む。
Claims (19)
- 歪み材料層を緩和する方法であって、
第1の低粘度層を前記歪み材料層の一面上に堆積させるステップと、
第2の低粘度層を前記歪み材料層の他の面上に堆積させて、第1のサンドイッチ構造を形成するステップと、
前記第1の低粘度層および前記第2の低粘度層のリフローが引き起こされるように、前記第1のサンドイッチ構造を加熱処理し、それによって前記歪み材料層を少なくとも部分的に緩和するステップと、
を含む方法。 - 前記サンドイッチ構造を前記加熱処理するステップの前に、第1の基板を前記第1の低粘度層と前記第2の低粘度層の一方に結合させるステップを更に含む、請求項1に記載の方法。
- 前記第1の低粘度層と前記第2の低粘度層の他方を第2の基板に結合させた後、加熱処理を行って第2のサンドイッチ構造を形成するステップを更に含む、請求項2に記載の方法。
- 前記第1の基板および前記第2の基板は、同様の材料あるいは互いの熱膨張係数の差が20%未満、特に10%未満である材料で構成される、請求項3に記載の方法。
- 少なくとも部分的に緩和した前記歪み材料層の少なくとも一面を露出するために、前記サンドイッチ構造を加熱処理するステップの後、前記第1の基板と前記第2の基板の少なくとも一方と、それが結合された前記低粘度層を取り外すステップを更に含む、請求項3または4に記載の方法。
- 前記加熱処理の前に、前記歪み材料層をパターン形成し、それによって歪み材料島、特に、隙間によって分離された横方向寸法が0.5mmより大きい歪み材料島を形成するステップを更に有する、請求項1〜5のいずれか一項に記載の方法。
- 前記第2の低粘度層を両方の前記歪み材料層上に堆積させるステップの前に、前記歪み材料層をパターン形成し、且つ、前記第2の低粘度層を前記歪み材料層上に堆積させるステップの後に、前記第2の低粘度層をパターン形成する、請求項6に記載の方法。
- 前記歪み材料層が、III/N材料、特にInGaNを含み、またはそれからなる、請求項1〜7のいずれか一項に記載の方法。
- 前記第1の低粘度層および/または前記第2の低粘度層が、ボロホスホシリケートガラス(BPSG)または、ホウ素またはリンを含むSiO2化合物を含み、またはそれからなる請求項1〜8のいずれか一項に記載の方法。
- 前記加熱処理が、少なくとも800℃の温度、特に少なくとも850℃の温度で行われる、請求項1〜9のいずれか一項に記載の方法。
- 前記第1の低粘度層および/または第2の低粘度層が、5質量%未満のホウ素、特に4質量%以下のホウ素を含む、請求項1〜10のいずれか一項に記載の方法。
- 前記歪み材料層、特にInGaN歪み層が、前記第1の低粘度層を前記歪み材料層上に堆積するステップの前に、支持基板上に堆積させたシード基板上、特にGaN層上に成長され、
前記第2の基板へ結合するために前記歪み材料層上に前記第2の低粘度層を堆積させる前に、前記歪み材料層を前記シード基板から取り外し、前記第1の低粘度層によって前記第1の基板に結合して、前記第2のサンドイッチ構造を形成する、
請求項3〜11のいずれか一項に記載の方法。 - 前記第1の低粘度層および/または前記第2の低粘度層が、前記第1の基板および/または前記第2の基板の取り外しに適した吸収層を備える、請求項1〜12のいずれか一項に記載の方法。
- 請求項1〜13のいずれか一項に記載の方法によって少なくとも部分的に緩和した歪み材料を形成するステップと、形成された少なくとも部分的に緩和した前記歪み材料上に、材料層、特に、LED、レーザーあるいは光起電分野に適用される活性層をエピタキシャル成長させるステップと、を更に含む半導体デバイスを製造する方法。
- 少なくとも部分的に緩和した前記材料が、極性III−N材料であり、前記エピタキシャル成長層が、III極性表面上で行われる、請求項1〜14のいずれか一項に記載の方法。
- 機械的な圧力を、前記加熱処理の少なくとも一部分中、特にピストンによって、前記歪み材料層の面に垂直に、前記第1の低粘度層と前記第2の低粘度層の他方に加えるステップを更に含む、請求項2に記載の方法。
- 前記圧力が、特に、前記圧力が前記第1の低粘度層および前記第2の低粘度層の他方の一面から他の面まで線形的に変化するように、あるいは、縁部におけるよりも中心においてより大きくなるように、前記第1のサンドイッチ構造の反対側まで不均一に加えられる、請求項16に記載の方法。
- 前記第2の粘度層を堆積させるステップが、
a)省略され、第1の基板が前記第1の低粘度層に結合され、前記方法が、特にピストンによって、機械的な圧力を前記第1の歪み材料層が結合された表面と反対側の前記歪み材料層の表面に加えるステップを更に含み、前記機械的な圧力が、前記加熱処理の少なくとも一部分中、前記歪み材料層の面と垂直に加えられるか、あるいは、
b)低粘度層を補強材、特に、前記歪み材料層の他方の面上に配置されたウエハの少なくとも一面上に堆積させるステップに置き換えられ、前記基板が前記低粘度層に結合され、前記方法が、前記加熱処理の少なくとも一部分中、機械的な圧力を、特にピストンによって、前記補強材の、前記歪み材料層に取付けられた面と反対側の面に、前記歪み材料層の面に垂直に加えるステップを更に含む、
請求項1に記載の方法。 - 前記歪み層の、第1の基板に結合された面と反対側の面および/または前記ピストンの表面および/または前記歪み材料に付加された補強材の表面は、1×1マイクロメートルスキャンで1nmを超える粗さを有する、請求項16〜18のいずれか一項に記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08290757A EP2151856A1 (en) | 2008-08-06 | 2008-08-06 | Relaxation of strained layers |
EP08290757.7 | 2008-08-06 | ||
EP09290577.7 | 2009-07-21 | ||
EP09290577 | 2009-07-21 | ||
PCT/EP2009/005694 WO2010015401A2 (en) | 2008-08-06 | 2009-08-06 | Relaxation of strained layers |
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JP2011530181A true JP2011530181A (ja) | 2011-12-15 |
JP5582617B2 JP5582617B2 (ja) | 2014-09-03 |
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US (2) | US20110143522A1 (ja) |
EP (1) | EP2324493B1 (ja) |
JP (1) | JP5582617B2 (ja) |
KR (1) | KR101227580B1 (ja) |
CN (2) | CN102113102B (ja) |
TW (1) | TWI457984B (ja) |
WO (1) | WO2010015401A2 (ja) |
Cited By (2)
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JP2012501071A (ja) * | 2008-08-25 | 2012-01-12 | ソイテック | 歪み層緩和のための硬化層 |
JP2020512684A (ja) * | 2017-03-17 | 2020-04-23 | ソイテックSoitec | 光電子デバイスを形成するための成長基板、そのような基板を作製するための方法、及び特にマイクロディスプレイスクリーンの分野における基板の使用 |
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TWI457984B (zh) | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | 應變層的鬆弛方法 |
US8536022B2 (en) * | 2010-05-19 | 2013-09-17 | Koninklijke Philips N.V. | Method of growing composite substrate using a relaxed strained layer |
FR2973157B1 (fr) * | 2011-03-25 | 2014-03-14 | Soitec Silicon On Insulator | Procédé de réalisation d'ilots de matériau contraint au moins partiellement relaxe |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
WO2019163646A1 (ja) * | 2018-02-23 | 2019-08-29 | 株式会社カネカ | 太陽電池の製造方法 |
FR3091005B1 (fr) * | 2018-12-21 | 2021-01-29 | Soitec Silicon On Insulator | Substrat de croissance et procede de fabrication d’un tel substrat |
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JP2012501071A (ja) * | 2008-08-25 | 2012-01-12 | ソイテック | 歪み層緩和のための硬化層 |
JP2020512684A (ja) * | 2017-03-17 | 2020-04-23 | ソイテックSoitec | 光電子デバイスを形成するための成長基板、そのような基板を作製するための方法、及び特にマイクロディスプレイスクリーンの分野における基板の使用 |
JP7053055B2 (ja) | 2017-03-17 | 2022-04-12 | ソイテック | 光電子デバイスを形成するための成長基板、そのような基板を作製するための方法、及び特にマイクロディスプレイスクリーンの分野における基板の使用 |
JP2022087136A (ja) * | 2017-03-17 | 2022-06-09 | ソイテック | 光電子デバイスを形成するための成長基板、そのような基板を作製するための方法、及び特にマイクロディスプレイスクリーンの分野における基板の使用 |
JP7322329B2 (ja) | 2017-03-17 | 2023-08-08 | ソイテック | 光電子デバイスを形成するための成長基板、そのような基板を作製するための方法、及び特にマイクロディスプレイスクリーンの分野における基板の使用 |
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KR20110050637A (ko) | 2011-05-16 |
WO2010015401A2 (en) | 2010-02-11 |
CN103123895A (zh) | 2013-05-29 |
JP5582617B2 (ja) | 2014-09-03 |
TWI457984B (zh) | 2014-10-21 |
US20110143522A1 (en) | 2011-06-16 |
EP2324493B1 (en) | 2014-05-07 |
TW201023249A (en) | 2010-06-16 |
WO2010015401A3 (en) | 2010-05-14 |
EP2324493A2 (en) | 2011-05-25 |
CN103123895B (zh) | 2016-01-20 |
KR101227580B1 (ko) | 2013-01-31 |
US8481408B2 (en) | 2013-07-09 |
CN102113102B (zh) | 2013-09-18 |
US20120214291A1 (en) | 2012-08-23 |
CN102113102A (zh) | 2011-06-29 |
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