US20110143522A1 - Relaxation of strained layers - Google Patents

Relaxation of strained layers Download PDF

Info

Publication number
US20110143522A1
US20110143522A1 US13/056,572 US200913056572A US2011143522A1 US 20110143522 A1 US20110143522 A1 US 20110143522A1 US 200913056572 A US200913056572 A US 200913056572A US 2011143522 A1 US2011143522 A1 US 2011143522A1
Authority
US
United States
Prior art keywords
layer
strained
low
material layer
viscosity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/056,572
Other languages
English (en)
Inventor
Fabrice Letertre
Carlos Mazure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP08290757A external-priority patent/EP2151856A1/en
Application filed by Soitec SA filed Critical Soitec SA
Assigned to S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES reassignment S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LETERTRE, FABRICE, MAZURE, CARLOS
Publication of US20110143522A1 publication Critical patent/US20110143522A1/en
Assigned to SOITEC reassignment SOITEC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Definitions

  • the present invention relates to the field of strained layers and compliant substrates for application in the manufacture of semiconductor devices useful in electronic, opto-electronic, photovoltaic field and, in particular, to the relaxation of strained heteroepitaxial films by compliant substrates.
  • heteroepitaxy is an important manufacturing step in the semiconductor technology. For instance, when native bulk substrates are not available or are too expensive, useful materials are often formed by heteroepitaxy on seed substrates. In the field of light-emitting semiconductor devices or solar cells there is a need to grow heteroepitaxial films of III/N materials on substrates as sapphire or SiC. However, when materials are formed by heteroepitaxy on substrates with a different lattice constants and different coefficients of thermal expansion as compared to the ones of the materials detrimental effects on material quality are caused by misfit compressive or tensile strain and the corresponding generation of dislocations and cracks.
  • film of materials are formed by heteroepitaxy with a limited thickness such that neither crack nor dislocation occurred in the material.
  • these films can, for instance, be used for epitaxial growth of layers used in electronic and opto-electronic, photovoltaic applications.
  • thin heteroepitaxial films are strained due to the misfit of lattice parameter and the quality of epitaxial growth or subsequent steps can be deteriorated.
  • the above-mentioned problem is solved by the method for relaxing a strained material layer according to claim 1 .
  • the method comprises the steps of
  • first low-viscosity layer comprising a first compliant material on one face of the strained material layer
  • second low-viscosity layer comprising a second compliant material on another face of the strained material layer to form a first sandwiched structure
  • subjecting the first sandwiched structure to a heat treatment such that reflow of the first and the second low-viscosity layers is caused thereby at least partly relaxing the strained material layer.
  • low-viscosity is used to indicate compliance and deformation ability of the thus specified layer during the heat treatment (see also discussion below).
  • the heat treatment at a temperature above the glass transition temperature results in some reflow (plastic deformation e.g. due to some glass transition) of the first and the second low-viscosity layers thereby elastically relaxing the strained material layer.
  • the provision of low-viscosity layers on both sides of the strained material layer allows in a free displacement of this strained material layer and, in particular, complete relaxation, if it is desired, without the formation of defects. Complete relaxation can be achieved by an appropriate choice of the temperature and duration of the heat treatment process.
  • a first substrate may be bonded to one of the first and the second low-viscosity layers before the step of subjecting the sandwich to the heat treatment.
  • This first substrate might be advantageously used for transfer from a seed substrate on that the strained material layer was heteroepitaxially grown beforehand.
  • a second substrate may be bonded to the other one of the first and the second low-viscosity layers before the step of heat treatment thereby forming a second sandwiched structure comprising both substrates, both low-viscosity layers and the strained material layer.
  • the second sandwiched structure comprising the first and the second substrates that may be made, e.g., of sapphire or some Si compound provides the advantage that buckling of the strained material layer during the relaxation heat treatment can reliably be prevented.
  • the first and the second substrates act as almost infinite rigid mechanical stiffeners during the heat treatment that suppresses or significantly reduces surface buckling and allows a mainly lateral relaxation of the strained material layer.
  • the dilatation of the substrates during the heat treatment may also participate to the relaxation of the strained material.
  • the first and the second substrates are made of the same material or at least of materials of similar coefficients of thermal expansion in order to avoid a risk that the second sandwiched structure could break during the heat treatment due to a significantly different expansion on both sides of the strained material layer.
  • the materials and the thicknesses of the substrates may advantageously be chosen such that the effect of mismatch between coefficients of thermal expansion is low enough at the reflow temperature so that the second sandwiched structure is mechanically stable during the heating to limit the risk of disassembling, cracks or splits of the substrates.
  • the coefficients of thermal expansion of substrates may differ by not more than 20%, preferably by not more than 10% and even more preferably by not more than 5% at the reflow temperature.
  • the first and second substrates may be chosen from the couple of Si/SiC, GaAS/Ge, SiC/AlN or GaN/AlN.
  • some (mechanical) pressure may be applied to the strained material layer to avoid or dampen wrinkles that may form during the heat processing (see also description below with reference to FIGS. 4 and 5 ).
  • the method comprises applying a mechanical pressure, in particular, by a piston, to the other of the first and second low-viscosity layers (the low-viscosity layer to which the first substrate is not bonded) perpendicular to the faces of the strained material layer during at least part of the heat treatment.
  • the pressure may be applied in an inhomogeneous manner across the strained material layer, in particular, such that the pressure varies linearly from one side of the other of the first and second low-viscosity layers to the other or is higher in the center than it is at the edges.
  • An uniaxial pressure can be applied to the strained material layer through a mechanical means, such as direct contact with a piston, or with another semiconductor wafer, or with a gas or liquid compressed by a piston.
  • the pressure may be applied at low enough temperature such that the strained material layer is not wrinkled.
  • the structure can be heated up to a temperature at which the BPSG (or low viscosity layer) flows while the pressure is applied. It is possible to optimize the magnitude of the pressure, the rate at which the pressure is applied, the rate at which the temperature of the wafer is increased, and the duration of the high temperature and high pressure application in order to minimize the amplitude of the wrinkling, or increase the wavelength.
  • the pressure may also be applied at high temperature, after the wrinkles have formed.
  • the pressure may be precisely controlled such that it is applied across the structure in an inhomogeneous manner.
  • the pressure may vary linearly from one side to the other, or may be higher in the center and lower at the edges. This could be accomplished by applying the pressure with a piston that has a wedge or circular cross-section.
  • suppressing wrinkles can be further optimized.
  • the low-viscosity layer may be deposited on the piston rather than the strained material layer.
  • the particular surface of the strained material layer and/or the surface of the piston or the surface of the stiffener that is applied to the surface of the strained material layer is relatively rough (e.g., above 1 nm roughness on a 1 by 1 micron scan) in order to avoid strong bonding between the low-viscosity layer and the strained material layer.
  • the low-viscosity layer provided between the piston and the strained material layer particularly serves to avoid friction between the piston (or an equivalent tool) and the strained material layer and facilitates relaxation of the same.
  • the pressure may be applied directly to the strained material layer without mediation by a low-viscosity layer.
  • a stiffener e.g., a wafer, may be laid on the strained material layer and the pressure is applied to the stiffener and thereby to the strained material layer during the heat treatment.
  • the herein disclosed method also comprises detaching at least one of the first and second substrates and the low-viscosity layer to which it is bonded after the step of subjecting the sandwich to the heat treatment in order to expose at least one surface of the strained material layer.
  • This exposed surface can subsequently be used for the further processing.
  • it can be used for epitaxy of a layer useful for the manufacture of an electronic or opto-electronic semiconductor device or solar cells.
  • the strained material layer may be patterned before the heat treatment thereby forming strained material islands separated by interspaces.
  • the formation of islands of the strained material layer further facilitates the relaxation process.
  • the shapes of the strained material islands are arbitrary, in principle, and might be chosen to be circular, square or rectangular for ease of manufacture. Due to the provision of two low-viscosity layers covering the strained material islands at two major surfaces lateral dimensions of some tenth parts of a millimeter, e.g., about 0.5 mm, or even larger can be chosen for the islands without strongly affecting the relaxation effect as compared to the case of significantly smaller islands which are used in the art.
  • the strained material layer is patterned before depositing the second low-viscosity layer or both the strained material layer and the second low-viscosity layer are patterned after depositing the second low-viscosity layer on the strained material layer.
  • the formation of the strained material islands can be performed after transfer of the strained material layer to the first substrate and before the second low-viscosity layer is deposited on the strained material or trenches (interspaces) are formed through the second low-viscosity layer and the strained material layer in which case the bonding to the second substrate includes bonding of the islands structures and interspaces are maintained in the bonded structure.
  • the first low-viscosity layer may also be partially or completely etch. These interspaces may be advantageous in achieving a completely relaxed strained material layer after the heat treatment.
  • the first and/or the second low-viscosity layers can be deposited in the form of buried oxide layers each being a compliant material layer.
  • an SiO 2 layer or undoped silicon glass or a SiN layer may be deposited on the strained material layer in order to enhance the adherence of the low-viscosity layer to the strained material layer.
  • the strained material layer comprises or consists of InGaN which is useful for the production of LEDs and solar cells, for instance. It should be noted, however, that InGaN represents only one example for the material of the strained material layer. In fact, the strained material layer may, for instance, comprise or consist of a III/N material, polar, semi-polar or non-polar, chosen from a binary, ternary quaternary alloy.
  • the first and/or the second low-viscosity layers may comprise or consist of borophosphosilicate glass (BPSG) or an SiO 2 — compound comprising boron or phosphorous to cause elastically relaxation of the strained material layer due to reflow when heated above the glass transition temperature.
  • BPSG borophosphosilicate glass
  • SiO 2 — compound comprising boron or phosphorous to cause elastically relaxation of the strained material layer due to reflow when heated above the glass transition temperature.
  • the heat treatment is advantageously performed at a temperature of at least 800° C., in particular, at least 850° C., in order to allow for complete relaxation of the strained material layer or the strained material islands with no substantially buckling, respectively.
  • strained material refers to the strained material layer or the islands formed from the strained material layer.
  • annealing temperatures in the range of 850° C. to 950° C., in particular, 900° C. to 950° C., can be used for causing a high (fast) reflow of the compliant material, since the strained material is capped and shielded by the first and second substrates and, thus, damage of the strained material layer is prevented even at such high temperatures.
  • the first and/or second low-viscosity layer may preferably comprise some % of weight boron but less than 5% of weight boron, in particular, less than 4% of weight boron in order to guarantee sufficient reflow at high anneal temperatures from 850° C. up to 950° C. but a sufficient mechanical rigidity at lower temperatures (about 800° C.) involved in epitaxy on the relaxed strained material (see description below).
  • phosphorous my be present at 1 to 3% by weight, in particular, 2 to 3% by weight.
  • the strained material layer in particular, a strained InGaN layer, may be grown on a seed substrate, in particular, a massive or composite seed substrate with a GaN layer being deposited on a support substrate before the step of depositing the first low-viscosity layer that is the first compliant material on the strained material layer and the strained material layer can be detached from the seed substrate and bonded by the first low-viscosity layer to the first substrate before depositing the second low-viscosity layer that is the second compliant material on the strained material layer for bonding to the second substrate to form the second sandwiched structure.
  • the detachment of strained layer from the seed substrate may be performed by the SMART CUT® technology, etching, laser lift off technique or any other suitable method.
  • a heteroepitaxially grown strained material layer that was transferred to the first substrate can efficiently be relaxed in accordance with the present invention.
  • the present invention has the advantage to easily allow the choice of the face of the InGaN material to free by the detachment of the first or the second substrate.
  • the III-polarity face as the Ga face for InGaN material after relaxation step that is particularly suitable for subsequent epitaxy.
  • the first low-viscosity layer and/or the second low-viscosity layer may comprise an absorption layer suitable for absorbing electromagnetic radiation in order to facilitate detachment after the heat treatment by means of laser lift off as know in the art.
  • the material of the absorbing electromagnetic radiation may be for example SiN or other nitride compounds such as GaN and related compounds.
  • the absorption layer of the first low-viscosity layer is arranged at the interface of the first low-viscosity layer and the first substrate and/or the absorption layer of the second low-viscosity layer is arranged at the interface of the second low-viscosity layer and the second substrate in order to avoid damage of the at least partly relaxed strained material layer.
  • the herein disclosed method for relaxing a strained material layer in a elastic relaxation mode with substantially no buckling can advantageously be used for the production of semiconductor device for electronic, photovoltaic or opto-electronic applications. It is, therefore, provided a method for the manufacture of a semiconductor device, comprising the formation of at least partially relaxed strained material according to one of the examples described above, and further comprising epitaxially or homoepitaxially growing a material layer on the formed at least partially relaxed strained material, in particular, at least partially relaxed strained material islands, after removal of at least the first substrate together with the first low-viscosity layer or the second substrate together with the second low-viscosity layer.
  • a sandwiched structure after at least partial relaxation of strained material layer in particular the at least partially relaxed strained layer is in InGaN and substrates are in sapphire.
  • the relaxed strained layer is in InGaN and the both substrates are in sapphire or in silicon.
  • a sandwiched structure comprising in this order a first substrate; a first low-viscosity layer; a strained material layer; a second low-viscosity layer; a second substrate; wherein the strained material layer and the second low-viscosity layer are patterned into islands separated by interspaces and the first and the second low-viscosity layers have the property to reflow at a temperature above the glass transition temperatures of the first and the second low-viscosity layers.
  • FIG. 1 illustrates an example of the inventive method for relaxing a strained material layer comprising the steps of forming a sandwiched structure comprising a borophosphosilicate glass above and below the strained material layer of InGaN and bonded to respective substrates and subjecting the sandwiched structure to heat treatment.
  • FIG. 2 illustrates another example of the inventive method for relaxing a strained material layer wherein the strained material layer is patterned thereby forming islands and trenches filled by a compliant material layer.
  • FIG. 3 illustrates another example of the inventive method for relaxing a strained material layer wherein the strained material layer is patterned thereby forming islands and open interspaces.
  • FIG. 4 illustrates an example of the inventive method for relaxing a strained material layer wherein external mechanical pressure is applied by some pressure means to the strained material layer during heat processing.
  • FIG. 5 illustrates an example of the inventive method for relaxing a strained material layer comparable to the one shown in FIG. 4 but with a borophosphosilicate glass layer or a stiffener provided for mediating the application of the pressure.
  • a multilayer stack representing a sandwiched structure is formed and subject to heat treatment (indicated by the arrows).
  • the sandwiched structure comprises a first substrate 1 , a first borophosphosilicate glass layer 2 , a strained material layer 3 , a second borophosphosilicate glass layer 4 and a second substrate 5 .
  • the strained material layer 3 is sandwiched by two low-viscosity compliant borophosphosilicate glass layers 2 and 4 .
  • the two low-viscosity compliant borophosphosilicate glass layers 2 and 4 allow for reliable complete elastical relaxation of the strained material layer 3 and the two substrates, which in the present example may be sapphire substrates, act as stiffeners to avoid any significant buckling of the strained material layer 3 .
  • the strained material layer 3 may be a c-plane InGaN film that was heteroepitaxially grown on a GaN seed layer deposited on some support substrate and transferred to the first substrate 1 by means of the first borophosphosilicate glass layer 2 .
  • the InGaN film may comprise 0.5 to 30% of molar indium and the thickness of the InGaN film may be chosen from 10 to 300 nm.
  • the InGaN film comprises about 5-7% of molar indium for a thickness of the film of about 100 nm.
  • an SiO 2 layer of a thickness of 10-100 nm may be deposited on the strained material layer 3 , e.g., the InGaN film, before deposition of the first borophosphosilicate glass layer 2 .
  • the second borophosphosilicate glass layer 4 is deposited on the free surface of the strained material layer 3 , i.e. on the N face of the InGaN film.
  • an SiN film may be formed on the N face of the InGaN film before deposition of the second borophosphosilicate glass layer 4 in order to improve adherence.
  • the second substrate was bonded to the second borophosphosilicate glass layer 4 .
  • Both borophosphosilicate glass layers may be formed of the same material to avoid stresses or other asymmetric influences on the strained material layer 3 caused by different reflow properties during the heat treatment.
  • the first and second borophosphosilicate glass layers 2 and 4 may comprise 4-5% of weight of boron and can appropriately have thicknesses of 0.5 micrometer up to a few micrometers. The greater the thicknesses of the respective borophosphosilicate glass layers 2 and 4 are chosen, the faster the relaxation of the strained material layer 3 will be achieved.
  • the sandwiched structure shown in FIG. 1 is annealed at a temperature of about 800° C. to 950° C. Fast reflow of the compliant material is expected at such high temperatures that can be employed, since the InGaN film is protected by the first and second substrates 1 and 5 .
  • the strained material layer 3 is patterned by etching trenches (interspaces) in the layer thereby forming strained material islands.
  • the continuous strained material layer 3 of FIG. 1 was etched to form trenches before the deposition of the second borophosphosilicate glass layer 4 .
  • the second borophosphosilicate glass layer 4 was deposited on the strained material it fills the trenches completely.
  • the manufacture of the sandwiched structure is the same as the one described with reference to FIG. 1 .
  • FIG. 3 Another example of a multilayer stack comprising a strained material layer that is to be relaxed by compliant material during heat treatment is shown in FIG. 3 .
  • the second borophosphosilicate glass layer 4 was deposited on the continuous strained material layer 3 of FIG. 1 and subsequently both the second borophosphosilicate glass layer 4 and the strained material layer 3 was patterned by etching trenches or interspaces 6 .
  • the borophosphosilicate glass layer 2 may also be partially or completely etched depending on the ability of the strained material to relax. Apart from this etching process, again, the manufacture of the sandwiched structure is the same as the one described with reference to FIG. 1 .
  • relaxation of the strained material islands 3 is not hindered by any material of the second borophosphosilicate glass layer 4 that was filled into the trenches.
  • the first substrate 1 and the first borophosphosilicate glass layer 2 can be detached in order to get access to the Ga face of the relaxed strained InGaN film (islands) that can be used for (homo)epitaxially growth of an InGaN layer, for example.
  • the boron content of the second borophosphosilicate glass layer 2 is below some 4 to 5% of weight such that a sufficiently high reflow (plastic deformation) can be achieved during the heat treatment at temperatures above 850° C. but concurrently a sufficient rigidity is provided at temperatures that are involved in the epitaxial growth, e.g., about 800° C.
  • the epitaxy can be performed with relaxed InGaN material of (approximately) the same indium content as the relaxed strained material 3 of FIGS. 1 to 3 .
  • relaxed InGaN material of (approximately) the same indium content as the relaxed strained material 3 of FIGS. 1 to 3 .
  • dislocation density of about 5 ⁇ 10 5 to 5 ⁇ 10 9 cm 2 with a thickness of 1 to 3 micrometers can be obtained.
  • trenches in both layers 2 and 4 might be provided and even be preferred in view of the relaxation step. It also possible to partially etch the second borophosphosilicate glass layer 2 .
  • FIG. 4 Another example for the herein disclosed inventive method is illustrated in FIG. 4 .
  • a multilayer stack representing a sandwiched structure is formed and subject to heat treatment (indicated by the arrows).
  • the sandwiched structure only comprises a first substrate 1 , a first borophosphosilicate glass layer 2 and a strained material layer 3 in this order.
  • mechanical pressure is applied to the strained material layer 3 by some mechanical pressure means 7 , e.g., a piston 7 , or a piston 7 directed onto a stiffener laid on the strained material layer 3 or a pressurized gas or liquid.
  • another borophosphosilicate glass layer 8 may be deposited on the strained material layer 3 or on a piston 7 or on a stiffener laid on the strained material layer, e.g., a wafer may be laid on the strained material layer 3 trough the borophosphosilicate glass layer 8 and the piston 7 applies pressure to the strained material layer 3 via the other borophosphosilicate glass layer 8 and/or the stiffener.
  • the borophosphosilicate glass layer 8 may alternatively be deposited on the piston 7 rather than the strained material layer 3 before application of pressure to the strained material layer 3 .
  • the surface of the strained material layer 3 that is opposite to the one bonded to first substrate and/or the surface of the piston 7 and/or the surface of the stiffener that are applied to the strained material layer 3 may be provided with a relatively rough surface e.g. above 1 nm roughness on a 1 by 1 micron scan for facilitating detachment after the heat treatment. Moreover, for accurate control of the application of the pressure a piston 7 with a wedge-like or circular cross-section may be preferred.
  • the formation of wrinkles in the strained material layer 3 during the heat treatment is reliably suppressed by the application of pressure by the pressure means 7 .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
US13/056,572 2008-08-06 2009-08-06 Relaxation of strained layers Abandoned US20110143522A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
EP08290757A EP2151856A1 (en) 2008-08-06 2008-08-06 Relaxation of strained layers
EP08290757.7 2008-08-06
EP09290577.7 2009-07-21
EP09290577 2009-07-21
PCT/EP2009/005694 WO2010015401A2 (en) 2008-08-06 2009-08-06 Relaxation of strained layers

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2009/005694 A-371-Of-International WO2010015401A2 (en) 2008-08-06 2009-08-06 Relaxation of strained layers

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/458,587 Division US8481408B2 (en) 2008-08-06 2012-04-27 Relaxation of strained layers

Publications (1)

Publication Number Publication Date
US20110143522A1 true US20110143522A1 (en) 2011-06-16

Family

ID=41600799

Family Applications (2)

Application Number Title Priority Date Filing Date
US13/056,572 Abandoned US20110143522A1 (en) 2008-08-06 2009-08-06 Relaxation of strained layers
US13/458,587 Active US8481408B2 (en) 2008-08-06 2012-04-27 Relaxation of strained layers

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/458,587 Active US8481408B2 (en) 2008-08-06 2012-04-27 Relaxation of strained layers

Country Status (7)

Country Link
US (2) US20110143522A1 (ja)
EP (1) EP2324493B1 (ja)
JP (1) JP5582617B2 (ja)
KR (1) KR101227580B1 (ja)
CN (2) CN102113102B (ja)
TW (1) TWI457984B (ja)
WO (1) WO2010015401A2 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110127640A1 (en) * 2008-08-25 2011-06-02 Bruce Faure Stiffening layers for the relaxation of strained layers
US20110284993A1 (en) * 2010-05-19 2011-11-24 Philips Lumileds Lighting Company, Llc Composite growth substrate for growing simiconductor device
US8481408B2 (en) 2008-08-06 2013-07-09 Soitec Relaxation of strained layers
US8951887B2 (en) 2011-06-23 2015-02-10 Soitec Process for fabricating a semiconductor structure employing a temporary bond

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2973157B1 (fr) * 2011-03-25 2014-03-14 Soitec Silicon On Insulator Procédé de réalisation d'ilots de matériau contraint au moins partiellement relaxe
JP7053055B2 (ja) * 2017-03-17 2022-04-12 ソイテック 光電子デバイスを形成するための成長基板、そのような基板を作製するための方法、及び特にマイクロディスプレイスクリーンの分野における基板の使用
WO2019163646A1 (ja) * 2018-02-23 2019-08-29 株式会社カネカ 太陽電池の製造方法
FR3091005B1 (fr) * 2018-12-21 2021-01-29 Soitec Silicon On Insulator Substrat de croissance et procede de fabrication d’un tel substrat

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670411A (en) * 1992-01-31 1997-09-23 Canon Kabushiki Kaisha Process of making semiconductor-on-insulator substrate
US5965939A (en) * 1992-04-16 1999-10-12 Samsung Electronics Co., Ltd. Semiconductor device and a method of manufacture
US6071795A (en) * 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
US6946373B2 (en) * 2002-11-20 2005-09-20 International Business Machines Corporation Relaxed, low-defect SGOI for strained Si CMOS applications
US20070069225A1 (en) * 2005-09-27 2007-03-29 Lumileds Lighting U.S., Llc III-V light emitting device
US20070287273A1 (en) * 2000-11-27 2007-12-13 Alice Boussagol Methods for making substrates and substrates formed therefrom
US7348260B2 (en) * 2003-02-28 2008-03-25 S.O.I.Tec Silicon On Insulator Technologies Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US20080296609A1 (en) * 2002-07-08 2008-12-04 Nichia Corporation Nitride Semiconductor Device Comprising Bonded Substrate and Fabrication Method of the Same
US8058663B2 (en) * 2007-09-26 2011-11-15 Iii-N Technology, Inc. Micro-emitter array based full-color micro-display

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4994867A (en) 1988-07-22 1991-02-19 Xerox Corporation Intermediate buffer films with low plastic deformation threshold for lattice mismatched heteroepitaxy
US5461243A (en) 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5391257A (en) 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
DE69739376D1 (de) 1996-08-27 2009-06-04 Seiko Epson Corp Ablösungsverfahren und Verfahren zum Übertragen eines Dünnfilm-Bauelements
FR2775121B1 (fr) 1998-02-13 2000-05-05 Picogiga Sa Procede de fabrication de substrats en film mince de materiau semiconducteur, structures epitaxiales de materiau semiconducteur formees sur de tels substrats, et composants obtenus a partir de ces structures
US6406795B1 (en) 1998-11-25 2002-06-18 Applied Optoelectronics, Inc. Compliant universal substrates for optoelectronic and electronic devices
US6214733B1 (en) 1999-11-17 2001-04-10 Elo Technologies, Inc. Process for lift off and handling of thin film materials
US6447604B1 (en) 2000-03-13 2002-09-10 Advanced Technology Materials, Inc. Method for achieving improved epitaxy quality (surface texture and defect density) on free-standing (aluminum, indium, gallium) nitride ((al,in,ga)n) substrates for opto-electronic and electronic devices
FR2817394B1 (fr) 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
US20030064535A1 (en) 2001-09-28 2003-04-03 Kub Francis J. Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate
US6562127B1 (en) 2002-01-16 2003-05-13 The United States Of America As Represented By The Secretary Of The Navy Method of making mosaic array of thin semiconductor material of large substrates
US7175704B2 (en) * 2002-06-27 2007-02-13 Diamond Innovations, Inc. Method for reducing defect concentrations in crystals
FR2851847B1 (fr) * 2003-02-28 2005-10-14 Soitec Silicon On Insulator Relaxation d'une couche mince apres transfert
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US20040192067A1 (en) 2003-02-28 2004-09-30 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US7812340B2 (en) 2003-06-13 2010-10-12 International Business Machines Corporation Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same
FR2860248B1 (fr) 2003-09-26 2006-02-17 Centre Nat Rech Scient Procede de realisation de substrats autosupportes de nitrures d'elements iii par hetero-epitaxie sur une couche sacrificielle
FR2860249B1 (fr) 2003-09-30 2005-12-09 Michel Bruel Procede de fabrication d'une structure en forme de plaque, en particulier en silicium, application de procede, et structure en forme de plaque, en particulier en silicium
US20080211061A1 (en) 2004-04-21 2008-09-04 California Institute Of Technology Method For the Fabrication of GaAs/Si and Related Wafer Bonded Virtual Substrates
CN100377377C (zh) * 2004-10-29 2008-03-26 夏普株式会社 半导体发光元件的制造方法
JP2006156950A (ja) * 2004-10-29 2006-06-15 Sharp Corp 半導体発光素子の製造方法
US7585792B2 (en) 2005-02-09 2009-09-08 S.O.I.Tec Silicon On Insulator Technologies Relaxation of a strained layer using a molten layer
CN101248519B (zh) 2005-02-28 2011-08-24 硅源公司 衬底硬化方法及所得器件
US7273798B2 (en) 2005-08-01 2007-09-25 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Gallium nitride device substrate containing a lattice parameter altering element
US7399686B2 (en) 2005-09-01 2008-07-15 International Business Machines Corporation Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate
US8334155B2 (en) 2005-09-27 2012-12-18 Philips Lumileds Lighting Company Llc Substrate for growing a III-V light emitting device
FR2895562B1 (fr) 2005-12-27 2008-03-28 Commissariat Energie Atomique Procede de relaxation d'une couche mince contrainte
FR2895420B1 (fr) 2005-12-27 2008-02-22 Tracit Technologies Sa Procede de fabrication d'une structure demontable en forme de plaque, en particulier en silicium, et application de ce procede.
JP2006186382A (ja) * 2006-01-27 2006-07-13 Toshiba Corp 電界効果トランジスタ
JP2007281257A (ja) 2006-04-07 2007-10-25 Toyoda Gosei Co Ltd Ｉｉｉ族窒化物半導体発光素子
JP5160080B2 (ja) 2006-06-23 2013-03-13 アイメック 歪マルチゲートトランジスタの製造方法およびそこから得られるデバイス
US7494902B2 (en) 2006-06-23 2009-02-24 Interuniversitair Microelektronica Centrum Vzw (Imec) Method of fabricating a strained multi-gate transistor
JP5003033B2 (ja) 2006-06-30 2012-08-15 住友電気工業株式会社 ＧａＮ薄膜貼り合わせ基板およびその製造方法、ならびにＧａＮ系半導体デバイスおよびその製造方法
EP1901345A1 (en) 2006-08-30 2008-03-19 Siltronic AG Multilayered semiconductor wafer and process for manufacturing the same
EP2087507A4 (en) 2006-11-15 2010-07-07 Univ California METHOD FOR THE HETEROEPITAXIAL GROWTH OF QUALITATIVELY HIGH-QUALITY N-SIDE-GAN, INN AND AIN AND THEIR ALLOYS THROUGH METALLORGANIC CHEMICAL IMMUNE
EP1933384B1 (en) * 2006-12-15 2013-02-13 Soitec Semiconductor heterostructure
US7858995B2 (en) 2007-08-03 2010-12-28 Rohm Co., Ltd. Semiconductor light emitting device
EP2151861A1 (en) 2008-08-06 2010-02-10 S.O.I. TEC Silicon Passivation of etched semiconductor structures
TWI457984B (zh) 2008-08-06 2014-10-21 Soitec Silicon On Insulator 應變層的鬆弛方法
EP2151852B1 (en) 2008-08-06 2020-01-15 Soitec Relaxation and transfer of strained layers
EP2151856A1 (en) 2008-08-06 2010-02-10 S.O.I. TEC Silicon Relaxation of strained layers
EP2159836B1 (en) 2008-08-25 2017-05-31 Soitec Stiffening layers for the relaxation of strained layers

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670411A (en) * 1992-01-31 1997-09-23 Canon Kabushiki Kaisha Process of making semiconductor-on-insulator substrate
US5965939A (en) * 1992-04-16 1999-10-12 Samsung Electronics Co., Ltd. Semiconductor device and a method of manufacture
US6071795A (en) * 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
US20070287273A1 (en) * 2000-11-27 2007-12-13 Alice Boussagol Methods for making substrates and substrates formed therefrom
US20080296609A1 (en) * 2002-07-08 2008-12-04 Nichia Corporation Nitride Semiconductor Device Comprising Bonded Substrate and Fabrication Method of the Same
US6946373B2 (en) * 2002-11-20 2005-09-20 International Business Machines Corporation Relaxed, low-defect SGOI for strained Si CMOS applications
US7348260B2 (en) * 2003-02-28 2008-03-25 S.O.I.Tec Silicon On Insulator Technologies Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US20070069225A1 (en) * 2005-09-27 2007-03-29 Lumileds Lighting U.S., Llc III-V light emitting device
US8058663B2 (en) * 2007-09-26 2011-11-15 Iii-N Technology, Inc. Micro-emitter array based full-color micro-display

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Huang, R. et al., 'Relaxation of a strained elastic film on a viscous layer,' 2002 Mat. Res. Soc. Symp. Proc. Vol. 695 p L3.14.1 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8481408B2 (en) 2008-08-06 2013-07-09 Soitec Relaxation of strained layers
US20110127640A1 (en) * 2008-08-25 2011-06-02 Bruce Faure Stiffening layers for the relaxation of strained layers
US8912081B2 (en) 2008-08-25 2014-12-16 Soitec Stiffening layers for the relaxation of strained layers
US20110284993A1 (en) * 2010-05-19 2011-11-24 Philips Lumileds Lighting Company, Llc Composite growth substrate for growing simiconductor device
US8536022B2 (en) * 2010-05-19 2013-09-17 Koninklijke Philips N.V. Method of growing composite substrate using a relaxed strained layer
US8951887B2 (en) 2011-06-23 2015-02-10 Soitec Process for fabricating a semiconductor structure employing a temporary bond

Also Published As

Publication number Publication date
KR20110050637A (ko) 2011-05-16
WO2010015401A2 (en) 2010-02-11
CN103123895A (zh) 2013-05-29
JP5582617B2 (ja) 2014-09-03
TWI457984B (zh) 2014-10-21
EP2324493B1 (en) 2014-05-07
TW201023249A (en) 2010-06-16
WO2010015401A3 (en) 2010-05-14
EP2324493A2 (en) 2011-05-25
JP2011530181A (ja) 2011-12-15
CN103123895B (zh) 2016-01-20
KR101227580B1 (ko) 2013-01-31
US8481408B2 (en) 2013-07-09
CN102113102B (zh) 2013-09-18
US20120214291A1 (en) 2012-08-23
CN102113102A (zh) 2011-06-29

Similar Documents

Publication Publication Date Title
EP2151856A1 (en) Relaxation of strained layers
US8481408B2 (en) Relaxation of strained layers
EP2151852B1 (en) Relaxation and transfer of strained layers
JP2669368B2 (ja) Ｓｉ基板上化合物半導体積層構造の製造方法
EP2936550B1 (en) Substrates for semiconductor devices
US8564019B2 (en) Heterostructures comprising crystalline strain relaxation layers
US8093686B2 (en) Process for obtaining a hybrid substrate comprising at least one layer of a nitrided material
US9041165B2 (en) Relaxation and transfer of strained material layers
KR101216367B1 (ko) 변형층들의 이완을 위한 보강층들
CN117344384A (zh) 高质量氮化物薄膜的远程外延生长方法、复合衬底及应用

Legal Events

Date Code Title Description
AS Assignment

Owner name: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, FRANC

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LETERTRE, FABRICE;MAZURE, CARLOS;REEL/FRAME:025979/0180

Effective date: 20110103

AS Assignment

Owner name: SOITEC, FRANCE

Free format text: CHANGE OF NAME;ASSIGNOR:S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES;REEL/FRAME:027800/0911

Effective date: 20110906

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION