JP2012501071A - 歪み層緩和のための硬化層 - Google Patents
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- 238000000034 method Methods 0.000 claims abstract description 38
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- 239000005380 borophosphosilicate glass Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
【解決手段】 歪み材料層と、歪み材料層の第1の面上に形成された低粘度層とを準備するステップと、該第1の面と反対側の該歪み材料層の第2の面の少なくとも一部分上に硬化層を形成し、それによって多層スタックを形成するステップと、該多層スタックを加熱処理し、それによって該歪み材料層を少なくとも部分的に緩和させるステップと、を含む。
【選択図】 図1
Description
歪み材料層と、コンプライアント材料を含み且つ歪み材料層の第1の面上に形成された低粘度層と、を準備するステップと、
歪み材料層を完全に覆うことなしに、(第1の面と反対側の)歪み材料層の第2の面の少なくとも一部分上に硬化層を形成し、それによって多層スタックを形成するステップと、
(コンプライアント材料層のリフローが生じるように)多層スタックを加熱処理し、それによって歪み材料層を少なくとも部分的に緩和させるステップと、
を含む。
硬化層のいかなる残部を取り除いて、歪み材料の全面を露出させ、加熱処理するステップと、
緩和した歪み材料を他の基板上に堆積した層に結合することによって、(完全にあるいは部分的に)緩和した歪み材料を他の基板に移すステップと、
低粘度層を緩和した歪み材料層から取り外すステップと、を含む。
Claims (15)
- 歪み材料層を緩和する方法であって、
歪み材料層と、該歪み材料層の第1の面上に形成された低粘度層と、を準備するステップと、
該歪み材料層の該第1の面と反対側の第2の面の少なくとも一部分上に硬化層を形成し、それによって多層スタックを形成するステップと、
該多層スタックを加熱処理し、それによって該歪み材料層を少なくとも部分的に緩和させるステップと、
を含む、前記方法。 - 該硬化層を形成するステップが、前記硬化層を連続層として該歪み材料層上に堆積させるステップと、続いて、該硬化層が該歪み材料層から部分的に取り除かれるように、該堆積された硬化層をパターニングするステップとを含む、請求項1に記載の方法。
- 続いて行われる該硬化層をパターニングするステップと前記多層スタックを加熱処理するステップは、この順番で少なくとも1回繰り返される、請求項2に記載の方法。
- 該加熱処理の前に、該歪み材料層をパターニングし、それによって歪み材料島を形成するステップを更に含む、請求項1〜3のいずれか一項に記載の方法。
- 該低粘度層をパターニングするステップを更に含む、請求項4に記載の方法。
- 該硬化層が、該硬化層の島が該歪み材料層の島の中央に形成されるようにパターニングされる、請求項4又は5に記載の方法。
- 該硬化層が、SiN、SiON、SiO2、あるいはIII−N材料を含む、またはそれらからなる、請求項1〜6のいずれか一項に記載の方法。
- 該歪み材料層が、InGaNを含む、またはそれからなる、請求項1〜7のいずれか一項に記載の方法。
- 該低粘度層が、ボロホスホシリケートガラス(BPSG)またはホウ素あるいは燐を含むSiO2化合物を含む、またはそれからなる、請求項1〜8のいずれか一項に記載の方法。
- 該硬化層が、50nmから該歪み材料層の厚さの5倍までの厚さで堆積される、請求項1〜9のいずれか一項に記載の方法。
- 該硬化層をパターニングする各繰り返しステップにおいて、該歪み材料の先の加熱処理におけるよりも1つの横方向寸法で約100μm〜400μmだけ多く、該パターニングされた硬化材料間が露出される、請求項8に記載の方法。
- 該硬化層の全ての残部を取り除いて、該歪み材料の全面を露出させて加熱処理するステップと、
緩和した該歪み材料をターゲット基板に結合することによって、緩和した該歪み材料の少なくとも一部分を、該ターゲット基板に移動させるステップと、
該低粘度層を緩和した該歪み材料から取り外すステップと、
を更に含む、請求項1〜11のいずれか一項に記載の方法。 - 該歪み材料層、特にInGaN歪み層が、シード基板、特にGaN層上で成長し、該シード基板が、該低粘度層、特にボロホスホシリケートガラスを該歪み材料層上に堆積するステップの前に第1の支持基板上に堆積されあるいは取付けられ、
該歪み材料層が、該シード基板から取り外され、該低粘度層によって第2の支持基板に結合され、その後、特にSi3N4を含む該硬化層を該歪み材料層に堆積する、請求項1〜12のいずれか一項に記載の方法。 - 半導体デバイスを製造する方法であって、
請求項1〜13のいずれか一項に記載の歪み材料を緩和するステップと、
該硬化層の全ての残部を取り除いて、該歪み材料の全面を露出させて、加熱処理するステップと、
形成された少なくとも部分的に緩和した該歪み材料上に材料層をエピタキシャル成長、特に、少なくとも部分的に緩和した該歪み材料島上に活性層を成長させるステップと、
を含むことを特徴とする方法。 - 支持基板と、該基板上の低粘度層と、該低粘度層上の、特にInGaN材料からなる連続歪み材料層または歪み材料島と、該連続歪み材料層または歪み材料島を、特に該歪み材料層または歪み材料島の露出幅が100〜400マイクロメートルとなるように、部分的に覆う硬化層と、を含む半導体構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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EP08290797.3A EP2159836B1 (en) | 2008-08-25 | 2008-08-25 | Stiffening layers for the relaxation of strained layers |
EP08290797.3 | 2008-08-25 | ||
PCT/EP2009/004790 WO2010022814A1 (en) | 2008-08-25 | 2009-07-02 | Stiffening layers for the relaxation of strained layers |
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JP2012501071A true JP2012501071A (ja) | 2012-01-12 |
JP5505845B2 JP5505845B2 (ja) | 2014-05-28 |
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US (1) | US8912081B2 (ja) |
EP (1) | EP2159836B1 (ja) |
JP (1) | JP5505845B2 (ja) |
KR (1) | KR101216367B1 (ja) |
CN (1) | CN102124557B (ja) |
WO (1) | WO2010022814A1 (ja) |
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TWI457984B (zh) | 2008-08-06 | 2014-10-21 | Soitec Silicon On Insulator | 應變層的鬆弛方法 |
RU2620068C2 (ru) | 2011-11-23 | 2017-05-22 | МЕДИММЬЮН, ЭлЭлСи | Связывающие молекулы, специфичные по отношению к her3, и их применения |
FR3064820B1 (fr) * | 2017-03-31 | 2019-11-29 | Soitec | Procede d'ajustement de l'etat de contrainte d'un film piezoelectrique |
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US8912081B2 (en) | 2014-12-16 |
CN102124557A (zh) | 2011-07-13 |
KR20110044330A (ko) | 2011-04-28 |
EP2159836B1 (en) | 2017-05-31 |
EP2159836A1 (en) | 2010-03-03 |
CN102124557B (zh) | 2016-08-10 |
JP5505845B2 (ja) | 2014-05-28 |
WO2010022814A1 (en) | 2010-03-04 |
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