JP2011192824A - 超接合半導体装置の製造方法 - Google Patents
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- JP2011192824A JP2011192824A JP2010058069A JP2010058069A JP2011192824A JP 2011192824 A JP2011192824 A JP 2011192824A JP 2010058069 A JP2010058069 A JP 2010058069A JP 2010058069 A JP2010058069 A JP 2010058069A JP 2011192824 A JP2011192824 A JP 2011192824A
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
【解決手段】高濃度第1導電型半導体基板1上に、ドリフト層として、第1導電型領域4と第2導電型領域5からなる超接合構造部10を形成する超接合半導体装置の製造方法において、前記第1導電型領域4および第2導電型領域5にそれぞれイオン注入する総不純物量を等しくするとともに、イオン注入直後の深さ方向の不純物濃度ピーク位置が前記第1導電型領域4と第2導電型領域5とでほぼ一致する加速エネルギーでそれぞれイオン注入する。
【選択図】 図1
Description
2 n−層
3 低濃度n−エピタキシャル層
4 n型カラム
4a n型不純物
5 p型カラム
5a p型不純物
6 レジストマスク
10 超接合構造部
100 素子活性部
200 周縁耐圧構造部
Claims (4)
- 高濃度第1導電型半導体基板上に、ドリフト層として、エピタキシャル成長と第1導電型不純物および第2導電型不純物のイオン注入を複数回繰り返して積み重ねることにより、前記半導体基板の主面に垂直方向に長い形状であって、主面に平行方向では交互に隣接配置される第1導電型領域と第2導電型領域からなる超接合構造部を形成する超接合半導体装置の製造方法において、前記第1導電型領域および第2導電型領域にそれぞれイオン注入する総不純物量を等しくするとともに、イオン注入直後の深さ方向の不純物濃度ピーク位置が前記第1導電型領域と第2導電型領域とでほぼ一致する加速エネルギーでそれぞれイオン注入することを特徴とする超接合半導体装置の製造方法。
- 前記イオン注入直後の不純物濃度ピーク位置が0.2μmより深いことを特徴とする請求項1に記載の超接合半導体装置の製造方法。
- 高濃度第1導電型半導体基板上に、ドリフト層として、エピタキシャル成長と第1導電型不純物および第2導電型不純物のイオン注入を複数回繰り返して積み重ねることにより、前記半導体基板の主面に垂直方向に長い形状であって、主面に平行方向では交互に隣接配置される第1導電型領域と第2導電型領域からなる超接合構造部を形成する超接合半導体装置の製造方法において、前記第1導電型領域をエピタキシャル成長によって形成する際に、前記エピタキシャル成長前の水素アニール温度とエピタキシャル成長の開始温度とを1100℃未満にすることを特徴とする接合半導体装置の製造方法。
- 高濃度第1導電型半導体基板上に、ドリフト層として、エピタキシャル成長と第1導電型不純物および第2導電型不純物のイオン注入を複数回繰り返して積み重ねることにより、前記半導体基板の主面に垂直方向に長い形状であって、主面に平行方向では交互に隣接配置される第1導電型領域と第2導電型領域からなる超接合構造部を形成する超接合半導体装置の製造方法において、前記第1導電型領域をエピタキシャル成長によって形成する際に、前記エピタキシャル成長前の前処理として、過酸化水素水とアンモニア水を用いる基板洗浄処理と希釈フッ酸処理を行った後、エピタキシャル成長の開始温度を950℃以下で行うことを特徴とする接合半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010058069A JP5985789B2 (ja) | 2010-03-15 | 2010-03-15 | 超接合半導体装置の製造方法 |
CN201110058206.6A CN102194701B (zh) | 2010-03-15 | 2011-03-08 | 超级结半导体器件的制造方法 |
TW100108553A TWI503872B (zh) | 2010-03-15 | 2011-03-14 | Method for manufacturing super-connected semiconductor devices |
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JP2010058069A JP5985789B2 (ja) | 2010-03-15 | 2010-03-15 | 超接合半導体装置の製造方法 |
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JP2014088808A Division JP5757355B2 (ja) | 2014-04-23 | 2014-04-23 | 超接合半導体装置の製造方法 |
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JP2011192824A true JP2011192824A (ja) | 2011-09-29 |
JP5985789B2 JP5985789B2 (ja) | 2016-09-06 |
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CN (1) | CN102194701B (ja) |
TW (1) | TWI503872B (ja) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140097350A (ko) * | 2011-12-01 | 2014-08-06 | 비쉐이-실리코닉스 | 초접합 mosfet 디바이스를 위한 에지 종단 |
WO2016002963A1 (ja) * | 2014-07-04 | 2016-01-07 | 富士電機株式会社 | 半導体装置 |
US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
US9646836B2 (en) | 2014-07-15 | 2017-05-09 | Fuji Electric Co., Ltd. | Semiconductor device manufacturing method |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
US9881997B2 (en) | 2015-04-02 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
US9887260B2 (en) | 2015-04-02 | 2018-02-06 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
US11145744B2 (en) | 2017-06-19 | 2021-10-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US8785306B2 (en) * | 2011-09-27 | 2014-07-22 | Alpha And Omega Semiconductor Incorporated | Manufacturing methods for accurately aligned and self-balanced superjunction devices |
US9105717B2 (en) * | 2013-12-04 | 2015-08-11 | Infineon Technologies Austria Ag | Manufacturing a semiconductor device using electrochemical etching, semiconductor device and super junction semiconductor device |
US10636660B2 (en) | 2018-09-28 | 2020-04-28 | General Electric Company | Super-junction semiconductor device fabrication |
TWI787819B (zh) * | 2021-05-14 | 2022-12-21 | 國立臺灣大學 | 具有濃度變化的三維超接面功率半導體 |
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JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
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JP2008258443A (ja) * | 2007-04-05 | 2008-10-23 | Toshiba Corp | 電力用半導体素子及びその製造方法 |
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JP3636345B2 (ja) * | 2000-03-17 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | 半導体素子および半導体素子の製造方法 |
EP1267415A3 (en) * | 2001-06-11 | 2009-04-15 | Kabushiki Kaisha Toshiba | Power semiconductor device having resurf layer |
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2010
- 2010-03-15 JP JP2010058069A patent/JP5985789B2/ja not_active Expired - Fee Related
-
2011
- 2011-03-08 CN CN201110058206.6A patent/CN102194701B/zh not_active Expired - Fee Related
- 2011-03-14 TW TW100108553A patent/TWI503872B/zh not_active IP Right Cessation
Patent Citations (8)
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JPH11100299A (ja) * | 1997-09-29 | 1999-04-13 | Mitsubishi Materials Silicon Corp | 薄膜エピタキシャルウェーハの製造方法およびこの方法により製造された薄膜エピタキシャルウェーハ |
JP2006100862A (ja) * | 1998-11-12 | 2006-04-13 | Fuji Electric Device Technology Co Ltd | 超接合半導体素子 |
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
JP2001139399A (ja) * | 1999-11-10 | 2001-05-22 | Shin Etsu Handotai Co Ltd | シリコンエピタキシャルウェーハの製造方法及びシリコンエピタキシャルウェーハ |
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JP2007012858A (ja) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | 半導体素子及びその製造方法 |
JP2008258443A (ja) * | 2007-04-05 | 2008-10-23 | Toshiba Corp | 電力用半導体素子及びその製造方法 |
Cited By (20)
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JP2015505155A (ja) * | 2011-12-01 | 2015-02-16 | ビシェイ−シリコニクス | スーパージャンクションmosfetデバイスのためのエッジ終端 |
KR20140097350A (ko) * | 2011-12-01 | 2014-08-06 | 비쉐이-실리코닉스 | 초접합 mosfet 디바이스를 위한 에지 종단 |
US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
KR101709565B1 (ko) * | 2011-12-01 | 2017-02-23 | 비쉐이-실리코닉스 | 초접합 mosfet 디바이스를 위한 에지 종단 |
US9935193B2 (en) | 2012-02-09 | 2018-04-03 | Siliconix Technology C. V. | MOSFET termination trench |
US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
US10229988B2 (en) | 2012-05-30 | 2019-03-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
US10283587B2 (en) | 2014-06-23 | 2019-05-07 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
WO2016002963A1 (ja) * | 2014-07-04 | 2016-01-07 | 富士電機株式会社 | 半導体装置 |
US10276654B2 (en) | 2014-07-04 | 2019-04-30 | Fuji Electric Co., Ltd. | Semiconductor device with parallel PN structures |
US9646836B2 (en) | 2014-07-15 | 2017-05-09 | Fuji Electric Co., Ltd. | Semiconductor device manufacturing method |
US10340377B2 (en) | 2014-08-19 | 2019-07-02 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
US9887260B2 (en) | 2015-04-02 | 2018-02-06 | Fuji Electric Co., Ltd. | Semiconductor device and semiconductor device manufacturing method |
US10211286B2 (en) | 2015-04-02 | 2019-02-19 | Fuji Electric Co., Ltd. | Semiconductor device |
US10008562B1 (en) | 2015-04-02 | 2018-06-26 | Fuji Electric Co., Ltd. | Semiconductor device manufacturing method |
US9881997B2 (en) | 2015-04-02 | 2018-01-30 | Fuji Electric Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
US11145744B2 (en) | 2017-06-19 | 2021-10-12 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JP5985789B2 (ja) | 2016-09-06 |
TWI503872B (zh) | 2015-10-11 |
TW201145361A (en) | 2011-12-16 |
CN102194701A (zh) | 2011-09-21 |
CN102194701B (zh) | 2014-03-26 |
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