WO2021042643A1 - 自平衡超结结构及其制备方法 - Google Patents

自平衡超结结构及其制备方法 Download PDF

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WO2021042643A1
WO2021042643A1 PCT/CN2019/130473 CN2019130473W WO2021042643A1 WO 2021042643 A1 WO2021042643 A1 WO 2021042643A1 CN 2019130473 W CN2019130473 W CN 2019130473W WO 2021042643 A1 WO2021042643 A1 WO 2021042643A1
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doping type
type
epitaxial layer
implantation
ion implantation
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PCT/CN2019/130473
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French (fr)
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王代利
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华润微电子（重庆）有限公司
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Priority to US17/624,337 priority Critical patent/US20220262897A1/en
Priority to KR1020217041954A priority patent/KR102608860B1/ko
Publication of WO2021042643A1 publication Critical patent/WO2021042643A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of semiconductor structures, in particular to a self-balanced super junction structure and a preparation method thereof.
  • the Super Junction structure uses an alternating PN junction structure to replace a single conductivity type material as the drift region, and introduces a lateral electric field in the drift region, so that the drift region of the device can be completely depleted under a small turn-off voltage, and breakdown
  • the voltage is only related to the thickness of the depletion layer and the critical electric field. Therefore, under the same withstand voltage condition, the doping concentration of the drift region of the super junction structure can be increased by an order of magnitude, which greatly reduces the on-resistance.
  • the key to the super-junction structure to achieve a higher breakdown voltage lies in the charge balance between the P and N areas.
  • the super-junction structure can obtain a higher breakdown voltage, and when the P and N areas are The charge in the area is out of balance, which will cause the breakdown voltage to decrease rapidly.
  • the line width fluctuation of the photolithography process will seriously affect the charge balance, and the line width control of the photolithography process is affected by multiple factors, and it is difficult to achieve precise control.
  • the current multi-layer epitaxial structure super-junction process has very strict requirements for photolithography process control, the process is difficult, the process tolerance is small, and the final product parameters fluctuate greatly.
  • the purpose of the present invention is to provide a self-balanced super junction structure and a preparation method thereof, which are used to solve the problem of the photolithography process in the preparation process of the multilayer epitaxial super junction structure in the prior art. This leads to problems such as high control difficulty and low fault tolerance.
  • the present invention provides a preparation method of a self-balanced super junction structure, the preparation method at least comprising the steps:
  • the first doped type substrate has a first side and a second side opposite to each other, and an initial epitaxial layer is formed on the first side of the first doped type substrate ;
  • a barrier layer with an implantation window is formed on the surface of the initial epitaxial layer, and based on the implantation window, an ion implantation process is used to form a first doping type implantation area and a second doping type implantation in the initial epitaxial layer respectively
  • the charge type of the ions in the implantation area of the first doping type is opposite to the charge type of the ions in the implantation area of the second doping type;
  • a barrier layer with an implantation window is formed on the surface of the intrinsic epitaxial layer, and based on the implantation window, an ion implantation process is used to respectively form a first doping type implantation region and a second doping in the intrinsic epitaxial layer Type implantation area, the charge type of the ions in the first doping type implantation area is opposite to the charge type of the ions in the second doping type implantation area;
  • the implanted regions of the first doping type are diffused and connected to form a first doping type column, and the implanted regions of the second doping type are diffused and connected to form a column of the second doping type, and the columns of the second doping type are separated
  • the first doping type pillar is formed to form a self-balanced super junction structure, wherein the total amount of the first doping type ions of the first doping type pillar and the second doping type ions of the second doping type pillar are The total amount is equal;
  • the first doping type is N-type and the second doping type is P-type, or the first doping type is P-type and the second doping type is N-type.
  • the present invention also provides a self-balanced super junction structure, which is prepared by the following method:
  • the first doped type substrate has a first side and a second side opposite to each other, and an initial epitaxial layer is formed on the first side of the first doped type substrate ;
  • a barrier layer with an implantation window is formed on the surface of the initial epitaxial layer, and based on the implantation window, an ion implantation process is used to form a first doping type implantation area and a second doping type implantation in the initial epitaxial layer respectively Area;
  • a barrier layer with an implantation window is formed on the surface of the intrinsic epitaxial layer, and based on the implantation window, an ion implantation process is used to respectively form a first doping type implantation region and a second doping in the intrinsic epitaxial layer Type injection area;
  • the implanted regions of the first doping type are diffused and connected to form a first doping type column, and the implanted regions of the second doping type are diffused and connected to form a column of the second doping type, and the columns of the second doping type are separated.
  • the first doped type pillar is formed to form a self-balanced super junction structure
  • the total amount of the first doping type ions of the first doping type column is equal to the total amount of the second doping type ions of the second doping type column;
  • the second doping type is P-type, or when the first doping type is P-type, the second doping type is N-type.
  • the preparation method of the self-balanced super junction structure of the present invention forms an epitaxial laminated layer structure through multiple epitaxial processes and ion implantation processes, and the first doped type ions and the second doped type in the same layer of the epitaxial laminated layer structure
  • the ions are all achieved by ion implantation after the same photolithography, that is, the balance of the two ions in each layer is only determined by the implantation, so the total number of ions of the first doping type and the second doping type of the epitaxial layer structure
  • the total number of ions is only determined by the implantation, so that the change of the lithography line width will not affect the balance relationship between the two ions, greatly reducing the impact of the lithography line width on the two ion implantation amounts, greatly relaxing the lithography line width specification, and reducing the light
  • the process is difficult to engrave, and the process tolerance is improved.
  • Fig. 1 shows a schematic flow chart of the preparation method of the self-balanced super junction structure of the present invention.
  • FIGS. 2 to 10 show schematic diagrams of the structure corresponding to each step in the preparation method of the self-balanced super junction structure of the present invention.
  • FIGs provided in this embodiment only illustrate the basic idea of the present invention in a schematic manner.
  • the diagrams only show the components related to the present invention instead of being drawn according to the number, shape and size of the components in actual implementation.
  • the type, quantity, and ratio of each component can be changed at will during implementation, and its component layout type may also be more complicated.
  • this embodiment provides a method for preparing a self-balanced super junction structure, the method at least including the following steps:
  • step S1 is first performed to provide a first doped type substrate 10, the first doped type substrate 10 has a first surface and a second surface opposite to each other, and The first surface of the first doping type substrate 10 forms an initial epitaxial layer 11.
  • the first doping type substrate 10 may be, but not limited to, a silicon substrate doped with first doping type ions.
  • the substrate 10 of the first doping type may be a substrate formed by implanting ions of the first doping type into the substrate using an ion implantation process.
  • the first doping type substrate 10 is a heavily doped substrate.
  • the doping concentration of the first doping type substrate 10 is greater than 1 ⁇ e 19 /cm 3 .
  • the initial epitaxial layer 11 is an epitaxial layer of the first doping type.
  • An epitaxial process may be used to form an intrinsic epitaxial layer on the upper surface of the first doped type substrate 10, and then ions of the first doped type may be implanted into the intrinsic epitaxial layer through an ion implantation process to form the initial Epitaxial layer 11.
  • the initial epitaxial layer 11 may be directly epitaxially formed on the upper surface of the first doped type substrate 10 by using an epitaxial process.
  • the thickness D1 of the initial epitaxial layer is between 2 ⁇ m and 20 ⁇ m, such as 6 ⁇ m, 10 ⁇ m, 14 ⁇ m, or 18 ⁇ m.
  • the specific thickness and ion implantation concentration are determined by the process design.
  • the thickness D1 of the initial epitaxial layer is less than When it is 2 ⁇ m, the resulting super junction structure will have a poor withstand voltage effect.
  • the thickness D1 of the initial epitaxial layer is greater than 20 ⁇ m, the on-resistance of the final super junction structure will be higher.
  • step S2 is then performed to form a barrier layer 12 with an implantation window 120 on the surface of the initial epitaxial layer 11.
  • an ion implantation process is used to A first doping type implantation region 13 and a second doping type implantation region 14 are respectively formed in the initial epitaxial layer 11, and the charge type of the ions in the first doping type implantation region 13 is the same as the second doping type
  • the charge types of the ions in the implantation region 14 are opposite.
  • the arrows in FIGS. 4 and 5 indicate the direction of ion implantation; the first doping type implantation region 13 and the second doping type implantation region 14 formed may be separated by a predetermined distance or partially overlapped.
  • the preset The distance and overlap distance are determined by the specific process design.
  • forming the first doping type implantation region 13 and the second doping type implantation region 14 includes the following steps:
  • barrier layer 12 (not shown) on the upper surface of the initial epitaxial layer 11;
  • the barrier layer 12 is etched by photolithography to form an implantation window 120 in the barrier layer 12.
  • the implantation window 120 defines the shape and position of the subsequent ion implantation process.
  • Photolithography etches the barrier layer 12 into strips, as shown in FIG. 3;
  • an ion implantation process is used to form a first doping type implantation region 13 in the initial epitaxial layer 11, as shown in FIG. 4;
  • an ion implantation process is used to form a second doping type implantation region 14 in the initial epitaxial layer 11, as shown in FIG. 5.
  • step 2-3) and step 2-4) can be interchanged, that is, after step 2-2) is finished, step 2-4) can be performed first, and then step 2-3).
  • the first doping type implantation region 13 and the second doping type implantation region 14 are formed by an ion implantation process of oblique angle ion implantation, wherein the first doping type implantation region 13 is formed.
  • the direction of the first ion implantation beam 20 of the impurity type implantation region 13 and the direction of the second ion implantation beam 21 forming the second doping type implantation region 14 are in a positive and negative oblique relationship, and the first ion implantation beam 20 And the projection of the second ion implantation beam 21 on the surface of the initial epitaxial layer 11 is perpendicular to the barrier layer 12.
  • the angle ⁇ 1 between the first ion implantation beam 20 and the initial epitaxial layer 11 is equal to the angle ⁇ 2 between the second ion implantation beam 21 and the initial epitaxial layer 11, and ⁇ 1 and ⁇ 2 are between 3° and 60°.
  • FIGS. 4 and 5 it is defined as the positive direction from the left to the right of the initial epitaxial layer 11, and the direction of the first ion implantation beam 20 is the positive tilt direction.
  • the direction of the second ion beam 21 is a negative oblique direction; it can also be defined in FIGS. 4 and 5 that the direction from the right to the left of the initial epitaxial layer 11 is a positive direction, then the direction of the first ion implantation beam 20 It is a negative tilt direction, and the direction of the second ion beam 21 is a positive tilt direction.
  • the first The tilt direction of an ion implantation beam 20 and the tilt direction of the second ion implantation beam 21 may be the same or different.
  • the width L of the injection window is between 1 ⁇ m and 10 ⁇ m, for example, it may be 3 ⁇ m, 5 ⁇ m, or 7 ⁇ m.
  • the ion implantation dose of the first doping type in the first doping type implantation region 13 is between 1 ⁇ e 12 /cm 2 and 1 ⁇ e 14 /cm 2
  • the second doping type is implanted
  • the ion implantation dose of the second doping type in the region 14 is between 1 ⁇ e 12 /cm 2 and 1 ⁇ e 14 /cm 2 .
  • step S3 of FIG. 1 and FIG. 6 step S3 is then performed to remove the barrier layer 12 and form an intrinsic epitaxial layer 15 on the surface of the initial epitaxial layer 11.
  • the thickness of the intrinsic epitaxial layer 15 is between 2 ⁇ m and 12 ⁇ m, such as 6 ⁇ m, 8 ⁇ m, or 10 ⁇ m, and the specific thickness is determined by process design.
  • step S4 is performed to form a barrier layer 12 with an implantation window 120 on the surface of the intrinsic epitaxial layer 15.
  • an ion implantation process is used
  • a first doping type implantation region 13 and a second doping type implantation region 14 are respectively formed in the intrinsic epitaxial layer 15.
  • the charge type of the ions in the first doping type implantation region 13 is the same as that of the second doping type.
  • the charge types of the ions in the hetero-type implantation region 14 are opposite.
  • the arrows in FIGS. 7 and 8 indicate the direction of ion implantation; the first doping type implantation region 13 and the second doping type implantation region 14 formed may be separated by a predetermined distance or partially overlapped. The distance and overlap distance are determined by the specific process design.
  • forming the first doping type implantation region 13 and the second doping type implantation region 14 includes the following steps:
  • the barrier layer 12 is etched by photolithography to form an implantation window 120 in the barrier layer 12.
  • the implantation window 120 defines the shape and position of the subsequent ion implantation process.
  • an ion implantation process is used to form a second doping type implantation region 14 in the intrinsic epitaxial layer 15, as shown in FIG. 8.
  • step 4-3) and step 4-4) can be interchanged, that is, after step 4-2) is completed, step 4-4) can be performed first, and then step 4-3) can be performed.
  • the first doping type implantation region 13 and the second doping type implantation region 14 are formed by an ion implantation process of oblique angle ion implantation, wherein the first doping type implantation region 13 is formed.
  • the direction of the first ion implantation beam 20 of the impurity type implantation region 13 and the direction of the second ion implantation beam 21 forming the second doping type implantation region 14 are in a positive and negative oblique relationship, and the first ion implantation beam 20 And the projection of the second ion implantation beam 21 on the surface of the intrinsic epitaxial layer 15 is perpendicular to the barrier layer 12.
  • the angle between the first ion implantation beam 20 and the intrinsic epitaxial layer 15 is And the angle between the second ion implantation beam 21 and the intrinsic epitaxial layer 15 Equal, and Between 3° ⁇ 60°.
  • the direction of the first ion implantation beam 20 is the positive tilt direction.
  • the direction of the second ion beam 21 is a negative oblique direction; it can also be defined as a positive direction from the right to the left of the intrinsic epitaxial layer 15 in FIGS. 4 and 5, then the first ion implantation beam 20
  • the direction of is a negative oblique direction
  • the direction of the second ion beam 21 is a positive oblique direction.
  • the first The tilt direction of the ion implantation beam 20 and the tilt direction of the second ion implantation beam 21 may be the same or different.
  • the width L of the injection window is between 1 ⁇ m and 10 ⁇ m, for example, it may be 3 ⁇ m, 5 ⁇ m, or 7 ⁇ m.
  • the ion implantation dose of the first doping type in the first doping type implantation region 13 is between 1 ⁇ e 12 /cm 2 and 1 ⁇ e 14 /cm 2
  • the second doping type is implanted
  • the ion implantation dose of the second doping type in the region 14 is between 1 ⁇ e 12 /cm 2 and 1 ⁇ e 14 /cm 2 .
  • step S5 is performed, and steps S3 to S4 are repeated to form an epitaxial layer having a plurality of first doping type implantation regions 13 and a plurality of second doping type implantation regions 14
  • steps S3 to S4 are repeated to form an epitaxial layer having a plurality of first doping type implantation regions 13 and a plurality of second doping type implantation regions 14
  • a plurality of first doping type implantation regions 13 are aligned with each other in a vertical direction
  • a plurality of second doping type implantation regions 14 are aligned with each other in a vertical direction.
  • the ion implantation dose of the first doping type implantation region 13 formed in each layer of the epitaxial laminated layer structure 16 and the ion implantation dose of the second doping type implantation region 14 may be the same or different, as long as it satisfies the requirements of the epitaxy
  • the total ion implantation dose of the plurality of first doping type implantation regions 13 in the stacked layer structure 16 may be the same as the total ion implantation dose of the plurality of second doping type implantation regions 14; of course, from the perspective of easy process control,
  • the ion implantation dose of the first doping type implantation region 13 formed in each layer of the epitaxial laminated layer structure 16 and the ion implantation dose of the second doping type implantation region 14 may also be set to be the same.
  • the epitaxial layered layer structure 16 of this embodiment is formed by multiple epitaxial processes and ion implantation processes.
  • the first doping type ions and the second doping type ions in the same layer are both implanted after the same photolithography. , That is, the balance of the two ions in each layer is only determined by the implantation, so the total number of ions of the first doping type and the total number of ions of the second doping type in the epitaxial layer structure 16 is only determined by the implantation, so that the lithography line
  • the width change will not affect the balance relationship between the two ions, greatly reduce the impact of the lithography line width on the two ion implantation amounts, greatly relax the lithography line width specification, reduce the difficulty of the lithography process, and increase the process tolerance.
  • the thickness D2 of the intrinsic epitaxial layer 15 of each layer in the epitaxial laminated layer structure 16 may be the same or different, which is determined by process design requirements.
  • step S6 is finally performed.
  • Each first doping type implantation region 13 is diffusion-connected and penetrated to form a first doping type pillar 17, and each second doping type implantation region 14 is diffusion-connected and penetrated
  • the second doping type pillars 18 are formed, and the first doping type pillars 17 are spaced between the second doping type pillars 18 to form a self-balanced super junction structure, wherein the first doping type pillars 17 are
  • the total amount of doping type ions is equal to the total amount of second doping type ions of the second doping type column 18.
  • the first doping type implantation region 13 is diffusion-connected and penetrated to form the first doping type pillar 17, and the second doping type implantation region 14 is diffusion-connected and penetrated to form the second doping type pillar 18, which can be achieved by thermal processes such as thermal annealing. Diffusion; it can also be achieved when the first doping type implantation region 13 and the second doping type implantation region 14 are formed by ion implantation.
  • the initial epitaxial layer 11 is an epitaxial layer of the first doping type
  • the first doping type pillar 17 and the initial epitaxial layer 11 are connected together.
  • the ion doping concentration of the first doping type pillar 17 and the initial epitaxial layer 11 may be the same or different, and the thermal diffusion conditions may be adjusted according to the process design requirements of the specific device.
  • the average concentration of the first doping type ions of the first doping type column 17 and the average concentration of the second doping type ions of the second doping type column 18 are between 1 ⁇ e 14 /cm 3 ⁇ Between 1 ⁇ e 16 /cm 3.
  • the first doping type is N-type
  • the second doping type is P-type
  • the first doping type is P-type
  • the second doping type is N type.
  • the N-type doping ions can be selected as phosphorus (P), arsenic (As), antimony (Sb) and other group V elements
  • the P-type doping ions can be selected as boron (B), gallium (Ga), etc.
  • this embodiment also provides a self-balanced super-junction structure, which is prepared by the above-mentioned preparation method of the self-balanced super-junction structure.
  • the present invention also provides a semiconductor device including the self-balanced super junction structure in this embodiment.
  • ion implantation of the second heavily doped type may also be performed on the second surface of the first doped type substrate 10, combined with other conventional steps of IGBT manufacturing, so as to form an IGBT with a super junction structure.
  • the total number of ions of the first doping type and the total number of ions of the second doping type in the epitaxial layer structure are determined only by the implantation, and the photoetching line
  • the width change will not affect the balance relationship between the two ions, greatly reduce the impact of the lithography line width on the two ion implantation amounts, greatly relax the lithography line width specification, reduce the difficulty of the lithography process, and increase the process tolerance.

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Abstract

本发明提供一种自平衡超结结构及其制备方法，包括：于第一掺杂类型衬底表面形成初始外延层；于初始外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；于初始外延层表面形成本征外延层；于本征外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；重复以上步骤，形成外延层叠层结构再进行热扩散处理，形成自平衡超结结构。外延层叠层结构同一层中的第一掺杂类型离子及第二掺杂类型离子均是通过同一次光刻后进行离子注入实现，所以外延层叠层结构中两种离子总数仅由注入决定，从而光刻线宽的变化不会影响两种离子的平衡关系，大幅降低光刻线宽对两种离子注入量的影响，大幅放宽光刻线宽规范，降低光刻工艺难度，提高工艺容差。

Description

自平衡超结结构及其制备方法 技术领域
本发明涉及半导体结构技术领域，特别是涉及一种自平衡超结结构及其制备方法。
背景技术
超结(Super Junction)结构采用交替的PN结结构取代单一导电类型材料作为漂移区，在漂移区引入了横向电场，使得器件漂移区在较小的关断电压下即可完全耗尽，击穿电压仅与耗尽层厚度及临界电场有关。因此，在相同耐压条件下，超结结构漂移区的掺杂浓度可以提高一个数量级，大大降低了导通电阻。
超结结构能够实现较高的击穿电压关键在于P区域和N区域的电荷平衡，当P区域和N区域的电荷平衡时超结结构可以得到较高的击穿电压，而当P区域和N区域的电荷失去平衡，则会导致击穿电压迅速降低。
目前，超结结构的制备方法主要有两种，一种为深槽刻蚀后外延填充形成，具体为：先在衬底上形成N型(或P型)外延层，并在所述N型(或P型)外延层内形成沟槽；然后再在所述沟槽内形成P型(或N型)填充层以得到超结结构。然而，上述超结结构的制备方法为了实现P区域和N区域的电荷平衡，需要严格控制N型(或P型)外延层浓度、沟槽刻蚀宽度、P型(或N型)填充层浓度等关键参数，并要求这些参数之间相互匹配。然而，对上述关键参数控制要求严格，工艺难度大且工艺兼容性小，使得最终产品的参数波动比较大。另一种为多次外延+注入+退火的方式形成超结结构，但是该制备方法为实现电荷平衡需要通过光刻工艺定义P/N杂质中的一种或两种杂质的注入区域，因此，光刻工艺的线宽波动将会严重的影响电荷平衡，而光刻工艺的线宽控制受多重因素影响，很难做到精确控制。目前的多层外延结构超结工艺对光刻工艺控制要求非常苛刻，工艺难度大且工艺容差性小，最终产品参数波动大。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种自平衡超结结构及其制备方法，用于解决现有技术中多层外延超结结构的制备工艺由于光刻工艺的影响导致控制难度大、容错性小等的问题。
为实现上述目的及其他相关目的，本发明提供一种自平衡超结结构的制备方法，所述制备方法至少包括步骤：
1)提供第一掺杂类型衬底，所述第一掺杂类型衬底具有相对的第一面及第二面，并于所述第一掺杂类型衬底的第一面形成初始外延层；
2)于所述初始外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述初始外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区，所述第一掺杂类型注入区内离子的电荷类型与所述第二掺杂类型注入区内离子的电荷类型相反；
3)去除所述阻挡层，于所述初始外延层表面形成本征外延层；
4)于所述本征外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述本征外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区，所述第一掺杂类型注入区内离子的电荷类型与所述第二掺杂类型注入区内离子的电荷类型相反；
5)重复进行步骤3)～步骤4)，形成具有多个第一掺杂类型注入区及多个第二掺杂类型注入区的外延层叠层结构，其中，多个第一掺杂类型注入区沿垂直方向互相对准，多个第二掺杂类型注入区沿垂直方向互相对准；
6)各第一掺杂类型注入区扩散连接贯通形成第一掺杂类型柱，各第二掺杂类型注入区扩散连接贯通形成第二掺杂类型柱，各第二掺杂类型柱之间间隔出第一掺杂类型柱，形成自平衡超结结构，其中，所述第一掺杂类型柱的第一掺杂类型离子总量与所述第二掺杂类型柱的第二掺杂类型离子总量相等；
所述第一掺杂类型为N型，所述第二掺杂类型为P型，或所述第一掺杂类型为P型，所述第二掺杂类型为N型。
本发明还提供一种自平衡超结结构，所述自平衡超结结构通过以下方法制备得到，
1)提供第一掺杂类型衬底，所述第一掺杂类型衬底具有相对的第一面及第二面，并于所述第一掺杂类型衬底的第一面形成初始外延层；
2)于所述初始外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述初始外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；
3)去除所述阻挡层，于所述初始外延层表面形成本征外延层；
4)于所述本征外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述本征外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；
5)重复进行步骤3)～步骤4)，形成具有多个第一掺杂类型注入区及多个第二掺杂类型注入区的外延层叠层结构，其中，多个第一掺杂类型注入区沿垂直方向互相对准，多个第二掺杂类型注入区沿垂直方向互相对准；
6)各第一掺杂类型注入区扩散连接贯通形成第一掺杂类型柱，各第二掺杂类型注入 区扩散连接贯通形成第二掺杂类型柱，各第二掺杂类型柱之间间隔出第一掺杂类型柱，形成自平衡超结结构，
其中，所述第一掺杂类型柱的第一掺杂类型离子总量与所述第二掺杂类型柱的第二掺杂类型离子总量相等；
所述第一掺杂类型为N型时，所述第二掺杂类型为P型，或所述第一掺杂类型为P型时，所述第二掺杂类型为N型。
如上所述，本发明的自平衡超结结构的制备方法通过多次外延工艺加离子注入过程形成外延层叠层结构，外延层叠层结构同一层中的第一掺杂类型离子及第二掺杂类型离子均是通过同一次光刻后进行离子注入实现，即每层中两种离子的平衡仅由注入决定，所以外延层叠层结构中第一掺杂类型离子的离子总数及第二掺杂类型离子的离子总数仅由注入决定，从而光刻线宽的变化不会影响两种离子的平衡关系，大幅降低光刻线宽对两种离子注入量的影响，大幅放宽光刻线宽规范，降低光刻工艺难度，提高工艺容差。
附图说明
图1显示为本发明的自平衡超结结构制备方法的流程示意图。
图2至图10显示为本发明的自平衡超结结构制备方法中各步骤对应的结构示意图。
具体实施方式
请参阅图1至图10。本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1至图10所示，本实施例提供一种自平衡超结结构的制备方法，所述制备方法至少包括步骤：
如图1的S1步骤及图2所示，首先进行步骤S1，提供第一掺杂类型衬底10，所述第一掺杂类型衬底10具有相对的第一面及第二面，并于所述第一掺杂类型衬底10的第一面形成初始外延层11。
作为示例，所述第一掺杂类型衬底10可以为但不限于掺杂有第一掺杂类型离子的硅衬底。所述第一掺杂类型的衬底10可以为采用离子注入工艺在衬底中注入第一掺杂类型的离子而形成的衬底。
作为示例，所述第一掺杂类型衬底10为重掺杂的衬底。较佳地，所述第一掺杂类型衬底10的掺杂浓度大于1×e 19/cm 3。
作为示例，所述初始外延层11为第一掺杂类型的外延层。在一示例中。可以先采用外延工艺在所述第一掺杂类型衬底10的上表面形成本征外延层，然后再通过离子注入工艺在本征外延层内注入第一掺杂类型的离子以形成所述初始外延层11。在另一示例中，可以采用外延工艺直接在所述第一掺杂类型衬底10的上表面外延形成所述初始外延层11。
作为示例，所述初始外延层的厚度D1介于2μm～20μm之间，例如可以是6μm、10μm、14μm或18μm，具体厚度与离子注入浓度由工艺设计决定当所述初始外延层的厚度D1小于2μm时，会导致最后形成的超结结构的耐压效果较差，当所述初始外延层的厚度D1大于20μm时，会导致最后形成的超结结构的导通电阻较高。
如图1的S2步骤及图3至图5所示，接着进行步骤S2，于所述初始外延层11表面形成带注入窗口120的阻挡层12，基于所述注入窗口120，采用离子注入工艺于所述初始外延层11中分别形成第一掺杂类型注入区13及第二掺杂类型注入区14，所述第一掺杂类型注入区13内离子的电荷类型与所述第二掺杂类型注入区14内离子的电荷类型相反。
图4及图5中的箭头表示离子注入的方向；形成的所述第一掺杂类型注入区13及第二掺杂类型注入区14可间隔预设距离或有部分重叠，这里所述预设距离及重叠距离由具体工艺设计决定。
作为示例，形成所述第一掺杂类型注入区13及所述第二掺杂类型注入区14包括如下步骤：
2-1)，于所述初始外延层11的上表面形成阻挡层12(未图示)；
2-2)，采用光刻刻蚀所述阻挡层12，以在所述阻挡层12内形成注入窗口120，所述注入窗口120定义出后续离子注入工艺的形状及位置，较佳地，采用光刻刻蚀将所述阻挡层12刻蚀为条形，如图3所示；
2-3)，基于所述注入窗口120，采用离子注入工艺于所述初始外延层11中形成第一掺杂类型注入区13，如图4所示；
2-4)，基于所述注入窗口120，采用离子注入工艺于所述初始外延层11中形成第二掺杂类型注入区14，如图5所示。
步骤2-3)及步骤2-4)的顺序可以互换，即步骤2-2)结束后可以先进行步骤2-4)，再进行步骤2-3)。
如图4及图5所示，作为示例，采用倾斜角离子注入的离子注入工艺形成所述第一掺杂 类型注入区13及第二掺杂类型注入区14，其中，形成所述第一掺杂类型注入区13的第一离子注入束20的方向与形成所述第二掺杂类型注入区14的第二离子注入束21的方向呈正负倾斜关系，且所述第一离子注入束20及所述第二离子注入束21在所述初始外延层11表面的投影与所述阻挡层12垂直。较佳地，所述第一离子注入束20与所述初始外延层11之间的夹角θ1与所述第二离子注入束21与所述初始外延层11之间的夹角θ2相等，且θ1、θ2介于3°～60°之间。
上述所述正负倾斜关系可以这样理解，在图4及图5中定义自所述初始外延层11的左边向右边为正方向，则所述第一离子注入束20的方向为正倾斜方向，所述第二离子束21的方向为负倾斜方向；也可在图4及图5中定义自所述初始外延层11的右边向左边为正方向，则所述第一离子注入束20的方向为负倾斜方向，所述第二离子束21的方向为正倾斜方向。所以不论以所述初始外延层11的哪边为正方向，只要满足所述第一离子注入束20的方向与所述第二离子注入束21的方向呈正负倾斜关系即可，所述第一离子注入束20的倾斜方向与所述第二离子注入束21的倾斜方向可以相同也可以不同。
作为示例，所述注入窗口的宽度L介于1μm～10μm之间，例如可以是3μm、5μm或7μm。
作为示例，所述第一掺杂类型注入区13中第一掺杂类型离子注入剂量介于1×e 12/cm 2～1×e 14/cm 2之间，所述第二掺杂类型注入区14中第二掺杂类型离子注入剂量介于1×e 12/cm 2～1×e 14/cm 2之间。
如图1的S3步骤及图6所示，接着进行步骤S3，去除所述阻挡层12，于所述初始外延层11表面形成本征外延层15。
作为示例，所述本征外延层15的厚度介于2μm～12μm之间，例如可以是6μm、8μm或10μm，具体厚度由工艺设计决定。
如图1的S4步骤及图7至图8所示，然后进行步骤S4，于所述本征外延层15表面形成带注入窗口120的阻挡层12，基于所述注入窗口120，采用离子注入工艺于所述本征外延层15中分别形成第一掺杂类型注入区13及第二掺杂类型注入区14，所述第一掺杂类型注入区13内离子的电荷类型与所述第二掺杂类型注入区14内离子的电荷类型相反。
图7及图8中的箭头表示离子注入的方向；形成的所述第一掺杂类型注入区13及第二掺杂类型注入区14可间隔预设距离或有部分重叠，这里所述预设距离及重叠距离由具体工艺设计决定。
作为示例，形成所述第一掺杂类型注入区13及所述第二掺杂类型注入区14包括如下步骤：
4-1)，于所述本征外延层15的上表面形成阻挡层12(未图示)；
4-2)，采用光刻刻蚀所述阻挡层12，以在所述阻挡层12内形成注入窗口120，所述注入窗口120定义出后续离子注入工艺的形状及位置，较佳地，采用光刻刻蚀将所述阻挡层12刻蚀为条形；
4-3)，基于所述注入窗口120，采用离子注入工艺于所述本征外延层15中形成第一掺杂类型注入区13，如图7所示；
4-4)，基于所述注入窗口120，采用离子注入工艺于所述本征外延层15中形成第二掺杂类型注入区14，如图8所示。
所述步骤4-3)及步骤4-4)的顺序可以互换，即步骤4-2)结束后可以先进行步骤4-4)，再进行步骤4-3)。
如图7及图8所示，作为示例，采用倾斜角离子注入的离子注入工艺形成所述第一掺杂类型注入区13及第二掺杂类型注入区14，其中，形成所述第一掺杂类型注入区13的第一离子注入束20的方向与形成所述第二掺杂类型注入区14的第二离子注入束21的方向呈正负倾斜关系，且所述第一离子注入束20及所述第二离子注入束21在所述本征外延层15表面的投影与所述阻挡层12垂直。较佳地，所述第一离子注入束20与所述本征外延层15之间的夹角
Figure PCTCN2019130473-appb-000001
与所述第二离子注入束21与所述本征外延层15之间的夹角
Figure PCTCN2019130473-appb-000002
相等，且
Figure PCTCN2019130473-appb-000003
介于3°～60°之间。
上述所述正负倾斜关系可以这样理解，在图7及图8中定义自所述本征外延层15的左边向右边为正方向，则所述第一离子注入束20的方向为正倾斜方向，所述第二离子束21的方向为负倾斜方向；也可在图4及图5中定义自所述本征外延层15的右边向左边为正方向，则所述第一离子注入束20的方向为负倾斜方向，所述第二离子束21的方向为正倾斜方向。所以不论以所述初始外延层11的哪边为正方向，只要满足所述第一离子注入束20的方向与所述第二离子注入束21的方向呈正负倾斜关系即可，所以第一离子注入束20的倾斜方向与所述第二离子注入束21的倾斜方向可以相同也可以不同。
作为示例，所述注入窗口的宽度L介于1μm～10μm之间，例如可以是3μm、5μm或7μm。
作为示例，所述第一掺杂类型注入区13中第一掺杂类型离子注入剂量介于1×e 12/cm 2～1×e 14/cm 2之间，所述第二掺杂类型注入区14中第二掺杂类型离子注入剂量介于1×e 12/cm 2～1×e 14/cm 2之间。
如图1的S5步骤及图9所示，接着进行步骤S5，重复进行步骤S3～步骤S4，形成具有多个第一掺杂类型注入区13及多个第二掺杂类型注入区14的外延层叠层结构16，其中，多 个第一掺杂类型注入区13沿垂直方向互相对准，多个第二掺杂类型注入区14沿垂直方向互相对准。
所述外延层叠层结构16每层中形成的所述第一掺杂类型注入区13的离子注入剂量与第二掺杂类型注入区14的离子注入剂量可以相同也可以不同，只要满足所述外延层叠层结构16中多个所述第一掺杂类型注入区13的离子注入总剂量与多个第二掺杂类型注入区14的离子注入总剂量相同即可；当然从易于工艺控制角度出发，也可将所述外延层叠层结构16每层中形成的所述第一掺杂类型注入区13的离子注入剂量与第二掺杂类型注入区14的离子注入剂量设置为相同。本实施例的所述外延层叠层结构16是通过多次外延工艺加离子注入过程形成，同一层中第一掺杂类型离子及第二掺杂类型离子均是通过同一次光刻后进行注入实现，即每层中两种离子的平衡仅由注入决定，所以外延层叠层结构16中第一掺杂类型离子的离子总数及第二掺杂类型离子的离子总数仅由注入决定，从而光刻线宽的变化不会影响两种离子的平衡关系，大幅降低光刻线宽对两种离子注入量的影响，大幅放宽光刻线宽规范，降低光刻工艺难度，提高工艺容差。
作为示例，所述外延层叠层结构16中各层所述本征外延层15的厚度D2可以相同也可以不相同，由工艺设计需求决定。
如图1的S6步骤及图10所示，最后进行步骤S6，各第一掺杂类型注入区13扩散连接贯通形成第一掺杂类型柱17，各第二掺杂类型注入区14扩散连接贯通形成第二掺杂类型柱18，各第二掺杂类型柱18之间间隔出第一掺杂类型柱17，形成自平衡超结结构，其中，所述第一掺杂类型柱17的第一掺杂类型离子总量与所述第二掺杂类型柱18的第二掺杂类型离子总量相等。
第一掺杂类型注入区13扩散连接贯通形成第一掺杂类型柱17，及第二掺杂类型注入区14扩散连接贯通形成第二掺杂类型柱18可通过热退火等热过程实现离子的扩散；也可是在离子注入形成各所述第一掺杂类型注入区13及第二掺杂类型注入区14时已实现离子的扩散连接。
如图10所示，作为示例，当所述初始外延层11为第一掺杂类型的外延层时，所述第一掺杂类型柱17与所述初始外延层11会连接在一起。
所述第一掺杂类型柱17与所述初始外延层11的离子掺杂浓度可以相同也可以不同，根据具体器件的工艺设计需求调整热扩散条件即可。
作为示例，所述第一掺杂类型柱17的第一掺杂类型离子平均浓度及所述第二掺杂类型柱18的第二掺杂类型离子平均浓度介于1×e 14/cm 3～1×e 16/cm 3之间。
作为示例，本实施例中的所述第一掺杂类型为N型，所述第二掺杂类型为P型，或所述第一掺杂类型为P型，所述第二掺杂类型为N型。其中，N型的掺杂离子可以选择为磷(P)，砷(As)，锑(Sb)等V族元素，P型的掺杂离子可以选择为硼(B)，稼(Ga)等。
如图1至图10所示，本实施例还提供一种自平衡超结结构，所述自平衡超结结构由上述自平衡超结结构的制备方法制备而得到。
此外，本发明还提供一种半导体器件，其包含本实施例中的自平衡超结结构。
作为示例，结合MOSFET制造的其他常规步骤，从而形成超结MOSFET结构。
作为示例，还可在所述第一掺杂类型衬底10的第二面进行第二重掺杂类型离子注入，结合IGBT制造的其他常规步骤，从而形成含超结结构的IGBT。
此外，还可形成其他含所述自平衡超结结构的其他半导体器件等。
综上所述，根据本发明的自平衡超结结构的制备方法，外延层叠层结构中第一掺杂类型离子的离子总数及第二掺杂类型离子的离子总数仅由注入决定，光刻线宽的变化不会影响两种离子的平衡关系，大幅降低光刻线宽对两种离子注入量的影响，大幅放宽光刻线宽规范，降低光刻工艺难度，提高工艺容差。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种自平衡超结结构的制备方法，其特征在于，所述制备方法至少包括步骤：
    1)提供第一掺杂类型衬底，所述第一掺杂类型衬底具有相对的第一面及第二面，并于所述第一掺杂类型衬底的第一面形成初始外延层；
    2)于所述初始外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述初始外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；
    3)去除所述阻挡层，于所述初始外延层表面形成本征外延层；
    4)于所述本征外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述本征外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；
    5)重复进行步骤3)～步骤4)，形成具有多个第一掺杂类型注入区及多个第二掺杂类型注入区的外延层叠层结构，其中，多个第一掺杂类型注入区沿垂直方向互相对准，多个第二掺杂类型注入区沿垂直方向互相对准；
    6)各第一掺杂类型注入区扩散连接贯通形成第一掺杂类型柱，各第二掺杂类型注入区扩散连接贯通形成第二掺杂类型柱，各第二掺杂类型柱之间间隔出第一掺杂类型柱，形成自平衡超结结构；
    其中，所述第一掺杂类型柱的第一掺杂类型离子总量与所述第二掺杂类型柱的第二掺杂类型离子总量相等；
    所述第一掺杂类型为N型时，所述第二掺杂类型为P型，或所述第一掺杂类型为P型时，所述第二掺杂类型为N型。
  2. 根据权利要求1所述的自平衡超结结构的制备方法，其特征在于：步骤2)中，采用倾斜角离子注入工艺形成所述第一掺杂类型注入区及第二掺杂类型注入区，其中，形成所述第一掺杂类型注入区的第一离子注入束的方向与形成所述第二掺杂类型注入区的第二离子注入束的方向呈正负倾斜关系，且所述第一离子注入束及所述第二离子注入束在所述初始外延层表面的投影与所述阻挡层垂直；步骤4)中，采用倾斜角离子注入工艺形成所述第一掺杂类型注入区及第二掺杂类型注入区，其中，形成所述第一掺杂类型注入区的第一离子注入束的方向与形成所述第二掺杂类型注入区的第二离子注入束的方向呈正负倾斜关系，且所述第一离子注入束及所述第二离子注入束在所述本征外延层表面的投影与所述阻挡层垂直。
  3. 根据权利要求2所述的自平衡超结结构的制备方法，其特征在于：步骤2)中，所述第一离子注入束与所述初始外延层之间的夹角与所述第二离子注入束与所述初始外延层之间 的夹角相等且介于3°～60°之间；步骤4)中，所述第一离子注入束与所述本征外延层之间的夹角与所述第二离子注入束与所述本征外延层之间的夹角相等且介于3°～60°之间。
  4. 根据权利要求1所述的自平衡超结结构的制备方法，其特征在于：步骤2)中，所述注入窗口的宽度介于1μm～10μm之间；步骤4)中，所述注入窗口的宽度介于1μm～10μm之间。
  5. 根据权利要求1所述的自平衡超结结构的制备方法，其特征在于：步骤1)中，所述初始外延层为第一掺杂类型的外延层。
  6. 根据权利要求1所述的自平衡超结结构的制备方法，其特征在于：步骤1)中，所述第一掺杂类型衬底为重掺杂衬底，所述第一掺杂类型衬底的掺杂浓度大于1×e 19/cm 3。
  7. 根据权利要求1所述的自平衡超结结构的制备方法，其特征在于：步骤1)中，所述初始外延层的厚度介于2μm～20μm之间；步骤3)中，所述本征外延层的厚度介于2μm～12μm之间。
  8. 根据权利要求1所述的自平衡超结结构的制备方法，其特征在于：所述第一掺杂类型注入区中第一掺杂类型离子注入剂量介于1×e 12/cm 2～1×e 14/cm 2之间，所述第二掺杂类型注入区中第二掺杂类型离子注入剂量介于1×e 12/cm 2～1×e 14/cm 2之间。
  9. 根据权利要求1所述的自平衡超结结构的制备方法，其特征在于，所述制备方法还包括：
    于所述第一掺杂类型衬底的第二面进行第二重掺杂类型离子注入的步骤。
  10. 一种自平衡超结结构，其特征在于，所述自平衡超结结构通过以下方法制备得到，
    1)提供第一掺杂类型衬底，所述第一掺杂类型衬底具有相对的第一面及第二面，并于所述第一掺杂类型衬底的第一面形成初始外延层；
    2)于所述初始外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述初始外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；
    3)去除所述阻挡层，于所述初始外延层表面形成本征外延层；
    4)于所述本征外延层表面形成带注入窗口的阻挡层，基于所述注入窗口，采用离子注入工艺于所述本征外延层中分别形成第一掺杂类型注入区及第二掺杂类型注入区；
    5)重复进行步骤3)～步骤4)，形成具有多个第一掺杂类型注入区及多个第二掺杂 类型注入区的外延层叠层结构，其中，多个第一掺杂类型注入区沿垂直方向互相对准，多个第二掺杂类型注入区沿垂直方向互相对准；
    6)各第一掺杂类型注入区扩散连接贯通形成第一掺杂类型柱，各第二掺杂类型注入区扩散连接贯通形成第二掺杂类型柱，各第二掺杂类型柱之间间隔出第一掺杂类型柱，形成自平衡超结结构，
    其中，所述第一掺杂类型柱的第一掺杂类型离子总量与所述第二掺杂类型柱的第二掺杂类型离子总量相等；
    所述第一掺杂类型为N型时，所述第二掺杂类型为P型，或所述第一掺杂类型为P型时，所述第二掺杂类型为N型。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114843192A (zh) * 2022-05-09 2022-08-02 瑶芯微电子科技(上海)有限公司 提高超结结构外延生长稳定性及半导体器件制备的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117393586B (zh) * 2023-12-13 2024-04-05 合肥晶合集成电路股份有限公司 一种功率半导体器件及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101258587A (zh) * 2005-07-08 2008-09-03 意法半导体股份有限公司 具有多漏结构的半导体功率器件及其相应的制造工艺
CN103021863A (zh) * 2011-09-27 2013-04-03 万国半导体股份有限公司 精确校准及自平衡的超级结器件的制备方法
US20180006147A1 (en) * 2016-06-29 2018-01-04 Infineon Technologies Austria Ag Method of Manufacturing a Super Junction Semiconductor Device and Super Junction Semiconductor Device
EP3422418A1 (en) * 2017-06-27 2019-01-02 Infineon Technologies Austria AG Method of manufacturing a superjunction semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7645659B2 (en) * 2005-11-30 2010-01-12 Fairchild Korea Semiconductor, Ltd. Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same
WO2011107832A1 (en) * 2010-03-04 2011-09-09 X-Fab Semiconductor Foundries Ag Manufacturing of a semiconductor device and corresponding semiconductor device
CN102947928B (zh) * 2010-06-17 2015-04-01 富士电机株式会社 半导体器件及其制造方法
KR101201382B1 (ko) * 2010-12-02 2012-11-14 (주) 트리노테크놀로지 감소된 셀 피치를 가지는 전력 반도체 소자
KR20130078356A (ko) * 2011-12-30 2013-07-10 주식회사 동부하이텍 반도체 소자의 슈퍼정션 구조 및 형성 방법
CN103730355B (zh) * 2013-12-27 2016-05-11 西安龙腾新能源科技发展有限公司 一种超结结构的制造方法
JP6485034B2 (ja) * 2014-06-16 2019-03-20 富士電機株式会社 半導体装置の製造方法
CN104979214B (zh) * 2015-05-12 2019-04-05 电子科技大学 一种超结结构的制备方法
CN106328532B (zh) * 2015-07-02 2020-06-09 北大方正集团有限公司 一种超结器件外延片的制作方法及结构
CN105977161A (zh) * 2016-06-21 2016-09-28 中航（重庆）微电子有限公司 超结结构及其制备方法
CN108074963B (zh) * 2016-11-16 2020-04-24 深圳尚阳通科技有限公司 超结器件及其制造方法
CN107507857B (zh) * 2017-08-10 2020-06-19 华润微电子（重庆）有限公司 自对准超结结构及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101258587A (zh) * 2005-07-08 2008-09-03 意法半导体股份有限公司 具有多漏结构的半导体功率器件及其相应的制造工艺
CN103021863A (zh) * 2011-09-27 2013-04-03 万国半导体股份有限公司 精确校准及自平衡的超级结器件的制备方法
US20180006147A1 (en) * 2016-06-29 2018-01-04 Infineon Technologies Austria Ag Method of Manufacturing a Super Junction Semiconductor Device and Super Junction Semiconductor Device
EP3422418A1 (en) * 2017-06-27 2019-01-02 Infineon Technologies Austria AG Method of manufacturing a superjunction semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114843192A (zh) * 2022-05-09 2022-08-02 瑶芯微电子科技(上海)有限公司 提高超结结构外延生长稳定性及半导体器件制备的方法

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