JP5556293B2 - 超接合半導体装置の製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 239000012535 impurity Substances 0.000 claims description 61
- 238000005468 ion implantation Methods 0.000 claims description 48
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- 238000000034 method Methods 0.000 claims description 23
- 229910052796 boron Inorganic materials 0.000 claims description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- 239000002826 coolant Substances 0.000 claims description 3
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
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- 239000011574 phosphorus Substances 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 7
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- 238000010586 diagram Methods 0.000 description 5
- -1 phosphorus ions Chemical class 0.000 description 5
- 108091006146 Channels Proteins 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000001704 evaporation Methods 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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Description
前記第2導電型不純物のイオン注入は、前記高濃度第1導電型半導体基板の保持温度を−40℃〜−200℃のいずれかの温度とすることが好ましい。また、第2導電型不純物のイオン注入がボロンであることがより好ましい。さらに、前記イオン注入の際の前記高濃度第1導電型半導体基板の冷却剤として、液体窒素を用いることができる。
本発明によれば、高濃度第1導電型半導体基板上に、ドリフト層として、前記高濃度第1導電型半導体基板の主面に垂直方向に長い形状であって、主面に平行方向では交互に隣接配置される第1導電型カラムと第2導電型カラムからなる並列pnカラムを有する超接合構造部を形成する超接合半導体装置の製造方法において、前記超接合構造部の形成は、第1導電型半導体層のエピタキシャル成長と、前記高濃度第1導電型半導体基板を冷却された状態で行う該第1導電型半導体層への第2導電型不純物のイオン注入と、を複数回繰り返し積み重ねる工程を備え、前記第2導電型不純物のイオン注入は、前記高濃度第1導電型半導体基板を室温(24℃)未満に冷却された状態に保持して行うことを特徴とする超接合半導体装置の製造方法とする。
2、2a、2b n−層
3、3a、3b 低濃度n−エピタキシャル層
4 n型カラム
5 p型カラム
6 レジストマスク
6a レジスト開口部
10 超接合構造部
100 素子活性部
200 周縁耐圧構造部
Claims (10)
- 高濃度第1導電型半導体基板上に、ドリフト層として、前記高濃度第1導電型半導体基板の主面に垂直方向に長い形状であって、主面に平行方向では交互に隣接配置される第1導電型カラムと第2導電型カラムからなる並列pnカラムを有する超接合構造部を形成する超接合半導体装置の製造方法において、
前記超接合構造部の形成は、
半導体層のエピタキシャル成長と、
該半導体層への第1導電型不純物のイオン注入および前記高濃度第1導電型半導体基板を冷却された状態で行う該半導体層への第2導電型不純物のイオン注入と、を複数回繰り返し積み重ねる工程を備え、
前記第2導電型不純物のイオン注入は、前記高濃度第1導電型半導体基板を室温(24℃)未満に冷却された状態に保持して行うことを特徴とする超接合半導体装置の製造方法。 - 前記第1導電型不純物のイオン注入は前記半導体層の全面に行うことを特徴とする請求項1に記載の超接合半導体装置の製造方法。
- 前記高濃度第1導電型半導体基板上に前記半導体層のエピタキシャル成長と前記第1導電型不純物および前記第2導電型不純物のイオン注入を複数回繰り返して積み重ねた後に熱拡散を行うことを特徴とする請求項1または2に記載の超接合半導体装置の製造方法。
- 前記第2導電型不純物のイオン注入は、レジストマスクの開口部の幅が前記レジストマスクの幅の1/4とする前記レジストマスクをマスクとして行い、
前記第2導電型不純物のイオン注入の不純物量は、前記第1導電型不純物のイオン注入の不純物量の4倍とすることを特徴とする請求項1乃至3いずれか一項に記載の超接合半導体装置の製造方法。 - 高濃度第1導電型半導体基板上に、ドリフト層として、前記高濃度第1導電型半導体基板の主面に垂直方向に長い形状であって、主面に平行方向では交互に隣接配置される第1導電型カラムと第2導電型カラムからなる並列pnカラムを有する超接合構造部を形成する超接合半導体装置の製造方法において、
前記超接合構造部の形成は、
第1導電型半導体層のエピタキシャル成長と、
前記高濃度第1導電型半導体基板を冷却された状態で行う該第1導電型半導体層への第2導電型不純物のイオン注入と、を複数回繰り返し積み重ねる工程を備え、
前記第2導電型不純物のイオン注入は、前記高濃度第1導電型半導体基板を室温(24℃)未満に冷却された状態に保持して行うことを特徴とする超接合半導体装置の製造方法。 - 前記高濃度第1導電型半導体基板上に前記第1導電型半導体層のエピタキシャル成長と前記第2導電型不純物のイオン注入を複数回繰り返して積み重ねた後に熱拡散を行うことを特徴とする請求項5に記載の超接合半導体装置の製造方法。
- 前記第2導電型不純物のイオン注入は、レジストマスクの開口部の幅が前記レジストマスクの幅の1/4とする前記レジストマスクをマスクとして行い、
前記第2導電型不純物のイオン注入の不純物量は、前記高濃度第1導電型半導体基板の不純物量の4倍とすることを特徴とする請求項5または6に記載の超接合半導体装置の製造方法。 - 前記第2導電型不純物のイオン注入は前記高濃度第1導電型半導体基板の保持温度を−40℃〜−200℃のいずれかの温度とすることを特徴とする請求項1乃至7のいずれか一項に記載の超接合半導体装置の製造方法。
- 前記第2導電型不純物のイオン注入がボロンであることを特徴とする請求項1乃至8のいずれか一項に記載の超接合半導体装置の製造方法。
- 前記第2導電型不純物のイオン注入は前記高濃度第1導電型半導体基板の冷却剤として、液体窒素を用いることを特徴とする請求項1乃至9のいずれか一項に記載の超接合半導体装置の製造方法。
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JP2014187200A (ja) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | 半導体装置の製造方法 |
CN108292605B (zh) | 2016-06-24 | 2021-08-27 | 富士电机株式会社 | 半导体装置的制造方法和半导体装置 |
JP7135422B2 (ja) * | 2018-05-11 | 2022-09-13 | 富士電機株式会社 | 半導体装置の製造方法 |
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JPH0536617A (ja) * | 1991-07-26 | 1993-02-12 | Fujitsu Ltd | イオンビーム照射方法および装置 |
JP2001119022A (ja) * | 1999-10-20 | 2001-04-27 | Fuji Electric Co Ltd | 半導体装置及びその製造方法 |
JP4581270B2 (ja) * | 2001-03-05 | 2010-11-17 | 住友電気工業株式会社 | SiC半導体のイオン注入層及びその製造方法 |
JP5160001B2 (ja) * | 2001-04-02 | 2013-03-13 | 富士電機株式会社 | 半導体装置の製造方法 |
JP3960174B2 (ja) * | 2002-09-09 | 2007-08-15 | 富士電機デバイステクノロジー株式会社 | 半導体装置の製造方法 |
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