JP2011155149A - 配線基板及びその製造方法並びに半導体パッケージ - Google Patents

配線基板及びその製造方法並びに半導体パッケージ Download PDF

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Publication number
JP2011155149A
JP2011155149A JP2010015937A JP2010015937A JP2011155149A JP 2011155149 A JP2011155149 A JP 2011155149A JP 2010015937 A JP2010015937 A JP 2010015937A JP 2010015937 A JP2010015937 A JP 2010015937A JP 2011155149 A JP2011155149 A JP 2011155149A
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JP
Japan
Prior art keywords
layer
metal layer
substrate
wiring
ceramic
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Pending
Application number
JP2010015937A
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English (en)
Japanese (ja)
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JP2011155149A5 (https=
Inventor
Sunao Arai
直 荒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010015937A priority Critical patent/JP2011155149A/ja
Priority to US12/954,953 priority patent/US20110180930A1/en
Publication of JP2011155149A publication Critical patent/JP2011155149A/ja
Publication of JP2011155149A5 publication Critical patent/JP2011155149A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2010015937A 2010-01-27 2010-01-27 配線基板及びその製造方法並びに半導体パッケージ Pending JP2011155149A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010015937A JP2011155149A (ja) 2010-01-27 2010-01-27 配線基板及びその製造方法並びに半導体パッケージ
US12/954,953 US20110180930A1 (en) 2010-01-27 2010-11-29 Wiring board, manufacturing method of the wiring board, and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010015937A JP2011155149A (ja) 2010-01-27 2010-01-27 配線基板及びその製造方法並びに半導体パッケージ

Publications (2)

Publication Number Publication Date
JP2011155149A true JP2011155149A (ja) 2011-08-11
JP2011155149A5 JP2011155149A5 (https=) 2013-03-07

Family

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JP2010015937A Pending JP2011155149A (ja) 2010-01-27 2010-01-27 配線基板及びその製造方法並びに半導体パッケージ

Country Status (2)

Country Link
US (1) US20110180930A1 (https=)
JP (1) JP2011155149A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015029951A1 (ja) 2013-08-26 2015-03-05 日立金属株式会社 実装基板用ウエハ、多層セラミックス基板、実装基板、チップモジュール、及び実装基板用ウエハの製造方法
JP2019114617A (ja) * 2017-12-22 2019-07-11 京セラ株式会社 配線基板
WO2020138278A1 (ja) * 2018-12-26 2020-07-02 京セラ株式会社 電子部品の接合方法および接合構造体
US11664302B2 (en) * 2018-11-30 2023-05-30 International Business Machines Corporation Integrated circuit module with a structurally balanced package using a bottom side interposer

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835217B2 (en) * 2010-12-22 2014-09-16 Intel Corporation Device packaging with substrates having embedded lines and metal defined pads
US9791470B2 (en) * 2013-12-27 2017-10-17 Intel Corporation Magnet placement for integrated sensor packages
US10251270B2 (en) * 2016-09-15 2019-04-02 Innovium, Inc. Dual-drill printed circuit board via
CN111599687B (zh) * 2019-02-21 2022-11-15 奥特斯科技(重庆)有限公司 具有高刚度的超薄部件承载件及其制造方法
US12205877B2 (en) 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831835A (ja) * 1994-07-20 1996-02-02 Fujitsu Ltd 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
JP2002299486A (ja) * 2001-03-29 2002-10-11 Kyocera Corp 光半導体素子収納用パッケージ
JP2002335082A (ja) * 2001-05-07 2002-11-22 Sony Corp 多層プリント配線基板及び多層プリント配線基板の製造方法
JP2004273980A (ja) * 2003-03-12 2004-09-30 Canon Inc 基板間配線電極接合の方法及び構造体
JP2006012687A (ja) * 2004-06-28 2006-01-12 Tdk Corp 低温焼成基板材料及びそれを用いた多層配線基板
JP2007123371A (ja) * 2005-10-26 2007-05-17 Kyocera Corp 多数個取り電子装置およびその製造方法
JP2008160019A (ja) * 2006-12-26 2008-07-10 Shinko Electric Ind Co Ltd 電子部品
US20080265399A1 (en) * 2007-04-27 2008-10-30 Clinton Chao Low-cost and ultra-fine integrated circuit packaging technique

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3407716B2 (ja) * 2000-06-08 2003-05-19 株式会社村田製作所 複合積層電子部品
US20020074637A1 (en) * 2000-12-19 2002-06-20 Intel Corporation Stacked flip chip assemblies

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831835A (ja) * 1994-07-20 1996-02-02 Fujitsu Ltd 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
JP2002299486A (ja) * 2001-03-29 2002-10-11 Kyocera Corp 光半導体素子収納用パッケージ
JP2002335082A (ja) * 2001-05-07 2002-11-22 Sony Corp 多層プリント配線基板及び多層プリント配線基板の製造方法
JP2004273980A (ja) * 2003-03-12 2004-09-30 Canon Inc 基板間配線電極接合の方法及び構造体
JP2006012687A (ja) * 2004-06-28 2006-01-12 Tdk Corp 低温焼成基板材料及びそれを用いた多層配線基板
JP2007123371A (ja) * 2005-10-26 2007-05-17 Kyocera Corp 多数個取り電子装置およびその製造方法
JP2008160019A (ja) * 2006-12-26 2008-07-10 Shinko Electric Ind Co Ltd 電子部品
US20080265399A1 (en) * 2007-04-27 2008-10-30 Clinton Chao Low-cost and ultra-fine integrated circuit packaging technique

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015029951A1 (ja) 2013-08-26 2015-03-05 日立金属株式会社 実装基板用ウエハ、多層セラミックス基板、実装基板、チップモジュール、及び実装基板用ウエハの製造方法
JP2019114617A (ja) * 2017-12-22 2019-07-11 京セラ株式会社 配線基板
JP7002321B2 (ja) 2017-12-22 2022-01-20 京セラ株式会社 配線基板
US11664302B2 (en) * 2018-11-30 2023-05-30 International Business Machines Corporation Integrated circuit module with a structurally balanced package using a bottom side interposer
WO2020138278A1 (ja) * 2018-12-26 2020-07-02 京セラ株式会社 電子部品の接合方法および接合構造体
JPWO2020138278A1 (ja) * 2018-12-26 2021-11-04 京セラ株式会社 電子部品の接合方法および接合構造体
JP7223772B2 (ja) 2018-12-26 2023-02-16 京セラ株式会社 電子部品の接合方法および接合構造体

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