JP2011022645A5 - - Google Patents

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Publication number
JP2011022645A5
JP2011022645A5 JP2009164672A JP2009164672A JP2011022645A5 JP 2011022645 A5 JP2011022645 A5 JP 2011022645A5 JP 2009164672 A JP2009164672 A JP 2009164672A JP 2009164672 A JP2009164672 A JP 2009164672A JP 2011022645 A5 JP2011022645 A5 JP 2011022645A5
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JP
Japan
Prior art keywords
data strobe
control circuit
signal
memory
mask
Prior art date
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Application number
JP2009164672A
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English (en)
Japanese (ja)
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JP2011022645A (ja
JP5258687B2 (ja
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Priority to JP2009164672A priority Critical patent/JP5258687B2/ja
Priority claimed from JP2009164672A external-priority patent/JP5258687B2/ja
Priority to US12/824,745 priority patent/US8320204B2/en
Publication of JP2011022645A publication Critical patent/JP2011022645A/ja
Publication of JP2011022645A5 publication Critical patent/JP2011022645A5/ja
Application granted granted Critical
Publication of JP5258687B2 publication Critical patent/JP5258687B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009164672A 2009-07-13 2009-07-13 メモリインタフェース制御回路 Expired - Fee Related JP5258687B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009164672A JP5258687B2 (ja) 2009-07-13 2009-07-13 メモリインタフェース制御回路
US12/824,745 US8320204B2 (en) 2009-07-13 2010-06-28 Memory interface control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009164672A JP5258687B2 (ja) 2009-07-13 2009-07-13 メモリインタフェース制御回路

Publications (3)

Publication Number Publication Date
JP2011022645A JP2011022645A (ja) 2011-02-03
JP2011022645A5 true JP2011022645A5 (enExample) 2012-04-05
JP5258687B2 JP5258687B2 (ja) 2013-08-07

Family

ID=43427377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009164672A Expired - Fee Related JP5258687B2 (ja) 2009-07-13 2009-07-13 メモリインタフェース制御回路

Country Status (2)

Country Link
US (1) US8320204B2 (enExample)
JP (1) JP5258687B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8760945B2 (en) 2011-03-28 2014-06-24 Samsung Electronics Co., Ltd. Memory devices, systems and methods employing command/address calibration
US8897084B2 (en) 2011-09-08 2014-11-25 Apple Inc. Dynamic data strobe detection
US9065413B2 (en) * 2012-01-25 2015-06-23 Texas Instruments Incorporated Method and apparatus for circuit with low IC power dissipation and high dynamic range
US9025399B1 (en) * 2013-12-06 2015-05-05 Intel Corporation Method for training a control signal based on a strobe signal in a memory module

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100521049B1 (ko) * 2003-12-30 2005-10-11 주식회사 하이닉스반도체 더블 데이터 레이트 싱크로너스 디램의 쓰기 회로
JP4284527B2 (ja) * 2004-03-26 2009-06-24 日本電気株式会社 メモリインターフェイス制御回路
KR100574989B1 (ko) * 2004-11-04 2006-05-02 삼성전자주식회사 데이터 스트로브 버스라인의 효율을 향상시키는메모리장치 및 이를 구비하는 메모리 시스템, 및 데이터스트로브 신호 제어방법
JP4747621B2 (ja) * 2005-03-18 2011-08-17 日本電気株式会社 メモリインターフェイス制御回路
JP4353330B2 (ja) * 2006-11-22 2009-10-28 エルピーダメモリ株式会社 半導体装置および半導体チップ
US7558132B2 (en) * 2007-03-30 2009-07-07 International Business Machines Corporation Implementing calibration of DQS sampling during synchronous DRAM reads
JP5106942B2 (ja) 2007-07-31 2012-12-26 ルネサスエレクトロニクス株式会社 メモリリード制御回路

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