JP5258687B2 - メモリインタフェース制御回路 - Google Patents

メモリインタフェース制御回路 Download PDF

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Publication number
JP5258687B2
JP5258687B2 JP2009164672A JP2009164672A JP5258687B2 JP 5258687 B2 JP5258687 B2 JP 5258687B2 JP 2009164672 A JP2009164672 A JP 2009164672A JP 2009164672 A JP2009164672 A JP 2009164672A JP 5258687 B2 JP5258687 B2 JP 5258687B2
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JP
Japan
Prior art keywords
circuit
signal
data strobe
output
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009164672A
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English (en)
Japanese (ja)
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JP2011022645A (ja
JP2011022645A5 (enExample
Inventor
秀望 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009164672A priority Critical patent/JP5258687B2/ja
Priority to US12/824,745 priority patent/US8320204B2/en
Publication of JP2011022645A publication Critical patent/JP2011022645A/ja
Publication of JP2011022645A5 publication Critical patent/JP2011022645A5/ja
Application granted granted Critical
Publication of JP5258687B2 publication Critical patent/JP5258687B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization

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  • Dram (AREA)
  • Memory System (AREA)
JP2009164672A 2009-07-13 2009-07-13 メモリインタフェース制御回路 Expired - Fee Related JP5258687B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009164672A JP5258687B2 (ja) 2009-07-13 2009-07-13 メモリインタフェース制御回路
US12/824,745 US8320204B2 (en) 2009-07-13 2010-06-28 Memory interface control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009164672A JP5258687B2 (ja) 2009-07-13 2009-07-13 メモリインタフェース制御回路

Publications (3)

Publication Number Publication Date
JP2011022645A JP2011022645A (ja) 2011-02-03
JP2011022645A5 JP2011022645A5 (enExample) 2012-04-05
JP5258687B2 true JP5258687B2 (ja) 2013-08-07

Family

ID=43427377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009164672A Expired - Fee Related JP5258687B2 (ja) 2009-07-13 2009-07-13 メモリインタフェース制御回路

Country Status (2)

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US (1) US8320204B2 (enExample)
JP (1) JP5258687B2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8760945B2 (en) 2011-03-28 2014-06-24 Samsung Electronics Co., Ltd. Memory devices, systems and methods employing command/address calibration
US8897084B2 (en) 2011-09-08 2014-11-25 Apple Inc. Dynamic data strobe detection
US9065413B2 (en) * 2012-01-25 2015-06-23 Texas Instruments Incorporated Method and apparatus for circuit with low IC power dissipation and high dynamic range
US9025399B1 (en) * 2013-12-06 2015-05-05 Intel Corporation Method for training a control signal based on a strobe signal in a memory module

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100521049B1 (ko) * 2003-12-30 2005-10-11 주식회사 하이닉스반도체 더블 데이터 레이트 싱크로너스 디램의 쓰기 회로
JP4284527B2 (ja) * 2004-03-26 2009-06-24 日本電気株式会社 メモリインターフェイス制御回路
KR100574989B1 (ko) * 2004-11-04 2006-05-02 삼성전자주식회사 데이터 스트로브 버스라인의 효율을 향상시키는메모리장치 및 이를 구비하는 메모리 시스템, 및 데이터스트로브 신호 제어방법
JP4747621B2 (ja) * 2005-03-18 2011-08-17 日本電気株式会社 メモリインターフェイス制御回路
JP4353330B2 (ja) * 2006-11-22 2009-10-28 エルピーダメモリ株式会社 半導体装置および半導体チップ
US7558132B2 (en) * 2007-03-30 2009-07-07 International Business Machines Corporation Implementing calibration of DQS sampling during synchronous DRAM reads
JP5106942B2 (ja) 2007-07-31 2012-12-26 ルネサスエレクトロニクス株式会社 メモリリード制御回路

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Publication number Publication date
JP2011022645A (ja) 2011-02-03
US20110007586A1 (en) 2011-01-13
US8320204B2 (en) 2012-11-27

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