CN103608793B - 用于dqs选通的系统和方法 - Google Patents
用于dqs选通的系统和方法 Download PDFInfo
- Publication number
- CN103608793B CN103608793B CN201280029420.1A CN201280029420A CN103608793B CN 103608793 B CN103608793 B CN 103608793B CN 201280029420 A CN201280029420 A CN 201280029420A CN 103608793 B CN103608793 B CN 103608793B
- Authority
- CN
- China
- Prior art keywords
- signal
- timing
- circuit
- control signal
- timing signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Abstract
Description
Claims (20)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161496965P | 2011-06-14 | 2011-06-14 | |
US61/496,965 | 2011-06-14 | ||
US201161540142P | 2011-09-28 | 2011-09-28 | |
US61/540,142 | 2011-09-28 | ||
PCT/US2012/040710 WO2012173807A1 (en) | 2011-06-14 | 2012-06-04 | System and method for dqs gating |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103608793A CN103608793A (zh) | 2014-02-26 |
CN103608793B true CN103608793B (zh) | 2016-10-26 |
Family
ID=46276015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201280029420.1A Active CN103608793B (zh) | 2011-06-14 | 2012-06-04 | 用于dqs选通的系统和方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9001599B2 (zh) |
EP (1) | EP2721500B1 (zh) |
JP (1) | JP6057438B2 (zh) |
KR (1) | KR101903718B1 (zh) |
CN (1) | CN103608793B (zh) |
WO (1) | WO2012173807A1 (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013164699A2 (en) * | 2012-05-01 | 2013-11-07 | Marvell World Trade Ltd. | Systems and methods for dqs gating |
WO2013188272A2 (en) * | 2012-06-12 | 2013-12-19 | Rambus Inc. | Optimizing power in a memory device |
US9524255B2 (en) | 2013-05-28 | 2016-12-20 | Marvell World Trade Ltd. | System and method for automatic DQS gating based on counter signal |
US9368172B2 (en) * | 2014-02-03 | 2016-06-14 | Rambus Inc. | Read strobe gating mechanism |
US9627031B1 (en) * | 2016-03-11 | 2017-04-18 | Mediatek Inc. | Control methods and memory systems using the same |
GB2550854B (en) * | 2016-05-25 | 2019-06-26 | Ge Aviat Systems Ltd | Aircraft time synchronization system |
JP6395919B1 (ja) | 2017-12-13 | 2018-09-26 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
US10176862B1 (en) | 2018-01-26 | 2019-01-08 | Micron Technology, Inc. | Data strobe gating |
CN108416176B (zh) * | 2018-04-28 | 2023-09-08 | 珠海一微半导体股份有限公司 | 一种dram控制器的抗干扰方法和电路及芯片 |
CN108899057B (zh) * | 2018-06-12 | 2020-09-18 | 豪威科技(上海)有限公司 | 读dqs信号门选通训练方法、装置以及数据传输系统 |
CN110648703B (zh) * | 2018-06-26 | 2021-06-15 | 龙芯中科技术股份有限公司 | 数据采集电路、读数据窗口的控制方法及装置 |
JP2021150843A (ja) | 2020-03-19 | 2021-09-27 | キオクシア株式会社 | 半導体集積回路、受信装置、及び受信装置の制御方法 |
CN115116530A (zh) * | 2022-05-09 | 2022-09-27 | 腾讯科技(深圳)有限公司 | 存储器的校验管脚处理方法、装置、设备和存储介质 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101030441A (zh) * | 2006-02-28 | 2007-09-05 | 中国科学院计算技术研究所 | Ddr和ddr2内存控制器的读数据采样方法及装置 |
CN101042925A (zh) * | 2006-03-21 | 2007-09-26 | 联发科技股份有限公司 | 存储器控制器,存储器装置以及选通信号校准方法 |
US7911857B1 (en) * | 2009-06-10 | 2011-03-22 | Juniper Networks, Inc. | Preamble detection and postamble closure for a memory interface controller |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6085345A (en) * | 1997-12-24 | 2000-07-04 | Intel Corporation | Timing control for input/output testability |
TWI228259B (en) * | 2000-05-22 | 2005-02-21 | Samsung Electronics Co Ltd | Method and circuit for inputting and outputting data, and system using semiconductor memory device including the same |
JP3605033B2 (ja) * | 2000-11-21 | 2004-12-22 | Necエレクトロニクス株式会社 | 固定長遅延生成回路 |
US6600681B1 (en) | 2002-06-10 | 2003-07-29 | Lsi Logic Corporation | Method and apparatus for calibrating DQS qualification in a memory controller |
US7089509B2 (en) * | 2002-12-23 | 2006-08-08 | Sun Microsystems, Inc. | Controlling the propagation of a control signal by means of variable I/O delay compensation using a programmable delay circuit and detection sequence |
US7299306B2 (en) * | 2003-06-20 | 2007-11-20 | Broadcom Corporation | Dual numerically controlled delay logic for DQS gating |
JP4284527B2 (ja) * | 2004-03-26 | 2009-06-24 | 日本電気株式会社 | メモリインターフェイス制御回路 |
JP2005292947A (ja) * | 2004-03-31 | 2005-10-20 | Hitachi Ltd | データ処理装置、遅延回路及び遅延素子 |
US7215584B2 (en) * | 2005-07-01 | 2007-05-08 | Lsi Logic Corporation | Method and/or apparatus for training DQS strobe gating |
US7685393B2 (en) | 2006-06-30 | 2010-03-23 | Mosaid Technologies Incorporated | Synchronous memory read data capture |
JP2008103013A (ja) * | 2006-10-18 | 2008-05-01 | Nec Electronics Corp | メモリリード制御回路およびその制御方法 |
JP5061722B2 (ja) * | 2007-05-24 | 2012-10-31 | 富士通セミコンダクター株式会社 | 信号マスキング回路、及び、その回路を搭載した半導体集積回路 |
JP4967850B2 (ja) * | 2007-06-26 | 2012-07-04 | ソニー株式会社 | メモリインタフェース回路 |
US7590025B2 (en) * | 2007-12-19 | 2009-09-15 | Integrated Device Technology, Inc. | Systems and methods for clean DQS signal generation in source-synchronous DDR2 interface design |
-
2012
- 2012-06-04 JP JP2014515863A patent/JP6057438B2/ja active Active
- 2012-06-04 US US13/487,737 patent/US9001599B2/en active Active
- 2012-06-04 EP EP12727523.8A patent/EP2721500B1/en active Active
- 2012-06-04 KR KR1020137033243A patent/KR101903718B1/ko active IP Right Grant
- 2012-06-04 CN CN201280029420.1A patent/CN103608793B/zh active Active
- 2012-06-04 WO PCT/US2012/040710 patent/WO2012173807A1/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101030441A (zh) * | 2006-02-28 | 2007-09-05 | 中国科学院计算技术研究所 | Ddr和ddr2内存控制器的读数据采样方法及装置 |
CN101042925A (zh) * | 2006-03-21 | 2007-09-26 | 联发科技股份有限公司 | 存储器控制器,存储器装置以及选通信号校准方法 |
US7911857B1 (en) * | 2009-06-10 | 2011-03-22 | Juniper Networks, Inc. | Preamble detection and postamble closure for a memory interface controller |
Also Published As
Publication number | Publication date |
---|---|
US20120324193A1 (en) | 2012-12-20 |
EP2721500A1 (en) | 2014-04-23 |
US9001599B2 (en) | 2015-04-07 |
WO2012173807A1 (en) | 2012-12-20 |
KR20140043390A (ko) | 2014-04-09 |
KR101903718B1 (ko) | 2018-10-04 |
JP6057438B2 (ja) | 2017-01-11 |
JP2014517422A (ja) | 2014-07-17 |
EP2721500B1 (en) | 2015-08-12 |
CN103608793A (zh) | 2014-02-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103608793B (zh) | 用于dqs选通的系统和方法 | |
US6724684B2 (en) | Apparatus for pipe latch control circuit in synchronous memory device | |
TWI239014B (en) | Data input circuits and methods of inputting data for a synchronous semiconductor memory device | |
JP4795032B2 (ja) | タイミング調整回路及び半導体装置 | |
KR100784905B1 (ko) | 반도체 메모리의 데이터 입력 장치 및 방법 | |
CN104272283A (zh) | 用于dqs选通的系统和方法 | |
KR101966084B1 (ko) | 전이 검출기를 갖는 신호 값 저장 회로 | |
US20070286012A1 (en) | Method for controlling data output timing of memory device and device therefor | |
JP2000276877A (ja) | ポステッドcasラテンシ機能を備えた同期式半導体メモリ装置及びcasラテンシ制御方法 | |
US8144530B2 (en) | Semiconductor memory device and method for generating output enable signal | |
JP2016540291A (ja) | メモリモジュールにおけるストローブ信号に基づいた制御信号のトレーニング方法 | |
CN103003882B (zh) | 用于源同步信息传送的装置和关联方法 | |
TWI303830B (en) | Data input apparatus of ddr sdram and method thereof | |
CN103035285B (zh) | 半导体存储器件及其制造方法 | |
CN100442394C (zh) | 半导体存储装置及其控制方法 | |
TW586119B (en) | Semiconductor memory device | |
CN105281751B (zh) | 半导体装置及其调节电路 | |
US9324409B1 (en) | Method and apparatus for gating a strobe signal from a memory and subsequent tracking of the strobe signal over time | |
CN106847319B (zh) | 一种fpga电路及窗口信号调整方法 | |
US7616030B2 (en) | Semiconductor device and operation method thereof | |
US6804756B2 (en) | Synchronization circuit for read paths of an electronic memory | |
US20060007759A1 (en) | Alignment of memory read data and clocking | |
US20010036121A1 (en) | Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit | |
KR100546319B1 (ko) | 반도체 메모리 장치의 입출력 데이터 파이프라인회로 및상기 반도체 메모리 장치 | |
US20100266081A1 (en) | System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20200427 Address after: Singapore City Patentee after: Marvell Asia Pte. Ltd. Address before: Ford street, Grand Cayman, Cayman Islands Patentee before: Kaiwei international Co. Effective date of registration: 20200427 Address after: Ford street, Grand Cayman, Cayman Islands Patentee after: Kaiwei international Co. Address before: Hamilton, Bermuda Patentee before: Marvell International Ltd. Effective date of registration: 20200427 Address after: Hamilton, Bermuda Patentee after: Marvell International Ltd. Address before: Babado J San Mega Le Patentee before: MARVELL WORLD TRADE Ltd. |
|
TR01 | Transfer of patent right |