JP4795032B2 - タイミング調整回路及び半導体装置 - Google Patents
タイミング調整回路及び半導体装置 Download PDFInfo
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- JP4795032B2 JP4795032B2 JP2006020782A JP2006020782A JP4795032B2 JP 4795032 B2 JP4795032 B2 JP 4795032B2 JP 2006020782 A JP2006020782 A JP 2006020782A JP 2006020782 A JP2006020782 A JP 2006020782A JP 4795032 B2 JP4795032 B2 JP 4795032B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
Description
101、102:入力アンプ
103:遅延調整回路
104〜106、109:ラッチ回路(FF)
107:判定回路
108:遅延回路
131、132:インバータ
133、134:トランジスタ
135、136:キャパシタ
Claims (11)
- データ入力端子から入力されたデータ信号をラッチする際のラッチタイミングを調整するタイミング調整回路において、
外部から入力されるタイミング信号を、可変に設定される遅延時間だけ遅延して出力する遅延調整回路と、
前記遅延されたタイミング信号と所定の位相関係を有する第1のクロック信号に基づいて前記データ信号をラッチする第1のラッチ回路と、
前記第1のクロック信号を第1の遅延時間だけ遅延した第2のクロック信号に基づいて前記データ信号をラッチする第2のラッチ回路と、
前記第1のクロック信号を、前記第1の遅延時間よりも大きな第2の遅延時間だけ遅延した第3のクロック信号に基づいて前記データ信号をラッチする第3のラッチ回路と、
前記第1から第3のラッチ回路の出力を相互に比較し、該比較結果に基づいて前記遅延調整回路の遅延時間を設定する判定回路とを備えたことを特徴とするタイミング調整回路。 - 前記遅延調整回路は、少なくとも3段階の遅延時間の範囲で遅延時間を調整可能である、請求項1に記載のタイミング調整回路。
- 前記第1の遅延時間は、前記第2の遅延時間の1/2である、請求項1又は2に記載のタイミング調整回路。
- 前記判定回路は、前記第1〜第3のラッチ回路の出力の全てが一致するとき、前記遅延調整時間の遅延時間を維持する請求項1〜3の何れか一に記載のタイミング調整回路。
- 前記判定回路は、前記第2のラッチ回路の出力と前記第3のラッチ回路の出力とが相互に一致し、かつ、前記第1のラッチ回路の出力が前記第2のラッチ回路の出力と一致しないとき、前記遅延調整回路の遅延時間を増加させ、前記第1のラッチ回路の出力と前記第2のラッチ回路の出力とが相互に一致し、かつ、前記第3のラッチ回路の出力が前記第2のラッチ回路の出力と一致しないとき、前記遅延調整回路の遅延時間を減少させる、請求項1〜3の何れか一に記載のタイミング調整回路。
- 前記遅延調整回路が、3段階以上のアップダウンカウンタと、該アップダウンカウンタのカウント値の増加又は減少に応じて遅延時間が増加又は減少する可変遅延回路とを備えており、前記判定回路は、前記第2のラッチ回路の出力と前記第3のラッチ回路の出力とが相互に一致し、かつ、前記第1のラッチ回路の出力が前記第2のラッチ回路の出力と一致しないとき、前記アップダウンカウンタのカウント値を、前記可変遅延回路の遅延時間が増加するようにアップ又はダウンさせ、前記第1のラッチ回路の出力と前記第2のラッチ回路の出力とが相互に一致し、かつ、前記第3のラッチ回路の出力が前記第2のラッチ回路の出力と一致しないとき、前記アップダウンカウンタのカウント値を、前記可変遅延回路の遅延時間が減少するようにアップ又はダウンさせる、請求項5に記載のタイミング調整回路。
- 前記判定回路は、前記第2のラッチ回路の出力が、前記第1及び第3のラッチ回路の出力と一致しないときにアラームを発生する、請求項1〜3の何れか一に記載のタイミング調整回路。
- データ入力端子から入力されたデータ信号を、外部から入力されるタイミング信号に基づいてラッチする半導体装置において、
請求項1〜7の何れか一に記載のタイミング調整回路を備え、前記第2のラッチ回路の出力を内部データ信号として内部回路に受け渡すことを特徴とする半導体装置。 - データ入力端子を複数備え、前記タイミング調整回路が前記複数のデータ入力端子のそれぞれに対応して配置されている、請求項8に記載の半導体装置。
- データ入力端子を複数備え、前記タイミング調整回路が前記複数のデータ入力端子のうちの何れかに対応して配置されており、前記タイミング調整回路が配置されていないデータ入力端子から入力するデータ信号をラッチするラッチ回路に、前記第2のクロック信号と同相のクロック信号を入力する、請求項8に記載の半導体装置。
- 1つのデータ入力端子に対応して、前記タイミング信号の立上りエッジに対応して入力されるデータ信号のラッチタイミングを調整する第1のタイミング調整回路と、前記タイミング信号の立下りエッジに対応して入力されるデータ信号のラッチタイミングを調整する第2のタイミング調整回路とを備え、
前記第1のタイミング調整回路では、前記第1〜第3のラッチ回路がそれぞれ前記第1〜第3のクロック信号の立ち上がりで前記データ信号をラッチし、前記第2のタイミング調整回路では、前記第1〜第3のラッチ回路がそれぞれ前記第1〜第3のクロック信号の立ち下がりで前記データ信号をラッチする、請求項8〜10の何れか一に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2006020782A JP4795032B2 (ja) | 2006-01-30 | 2006-01-30 | タイミング調整回路及び半導体装置 |
US11/698,892 US7759998B2 (en) | 2006-01-30 | 2007-01-29 | Timing adjustment circuit |
Applications Claiming Priority (1)
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JP2006020782A JP4795032B2 (ja) | 2006-01-30 | 2006-01-30 | タイミング調整回路及び半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007202033A JP2007202033A (ja) | 2007-08-09 |
JP4795032B2 true JP4795032B2 (ja) | 2011-10-19 |
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JP2006020782A Expired - Fee Related JP4795032B2 (ja) | 2006-01-30 | 2006-01-30 | タイミング調整回路及び半導体装置 |
Country Status (2)
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US (1) | US7759998B2 (ja) |
JP (1) | JP4795032B2 (ja) |
Families Citing this family (17)
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US20080144405A1 (en) | 2006-12-18 | 2008-06-19 | Intel Corporation | Data strobe timing compensation |
JP5201208B2 (ja) * | 2008-06-03 | 2013-06-05 | 富士通株式会社 | 情報処理装置及びその制御方法 |
WO2010080172A1 (en) | 2009-01-12 | 2010-07-15 | Rambus Inc. | Clock-forwarding low-power signaling system |
TWI401695B (zh) * | 2009-01-23 | 2013-07-11 | Nanya Technology Corp | 訊號調整系統與訊號調整方法 |
US8040153B1 (en) * | 2009-01-31 | 2011-10-18 | Xilinx, Inc. | Method and apparatus for configuring the internal memory cells of an integrated circuit |
US8098085B2 (en) * | 2009-03-30 | 2012-01-17 | Qualcomm Incorporated | Time-to-digital converter (TDC) with improved resolution |
CN102124451A (zh) | 2009-05-27 | 2011-07-13 | 松下电器产业株式会社 | 延迟调整装置以及延迟调整方法 |
JP4992938B2 (ja) | 2009-05-27 | 2012-08-08 | 富士通株式会社 | パラレル−シリアル変換器 |
TWI419174B (zh) * | 2009-06-08 | 2013-12-11 | Nanya Technology Corp | 訊號調整系統與訊號調整方法 |
US8407509B2 (en) * | 2010-10-11 | 2013-03-26 | Freescale Semiconductor, Inc. | Method for compensating for variations in data timing |
WO2013038562A1 (ja) * | 2011-09-16 | 2013-03-21 | 富士通株式会社 | 伝送システム、送信装置、受信装置および伝送方法 |
US8897083B1 (en) * | 2012-12-14 | 2014-11-25 | Altera Corporation | Memory interface circuitry with data strobe signal sharing capabilities |
US9337817B2 (en) | 2014-06-17 | 2016-05-10 | Via Alliance Semiconductor Co., Ltd. | Hold-time optimization circuit and receiver with the same |
US9503065B1 (en) * | 2015-08-31 | 2016-11-22 | Teradyne, Inc. | Deskew of rising and falling signal edges |
US9485080B1 (en) * | 2015-09-01 | 2016-11-01 | Qualcomm Incorporated | Multiphase clock data recovery circuit calibration |
KR20180028613A (ko) * | 2016-09-09 | 2018-03-19 | 삼성전자주식회사 | 메모리 시스템 및 메모리 제어 방법 |
US10552169B2 (en) * | 2017-03-17 | 2020-02-04 | Sandisk Technologies Llc | On-die signal calibration |
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JP4416580B2 (ja) * | 2004-06-28 | 2010-02-17 | 株式会社リコー | 遅延制御装置 |
JP2006333150A (ja) * | 2005-05-27 | 2006-12-07 | Matsushita Electric Ind Co Ltd | 集積回路装置 |
-
2006
- 2006-01-30 JP JP2006020782A patent/JP4795032B2/ja not_active Expired - Fee Related
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2007
- 2007-01-29 US US11/698,892 patent/US7759998B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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US7759998B2 (en) | 2010-07-20 |
US20070176658A1 (en) | 2007-08-02 |
JP2007202033A (ja) | 2007-08-09 |
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