WO2001052015A2

WO2001052015A2 - Circuit and method for filtering oscillations and synchronizing signals

Info

Publication number: WO2001052015A2
Application number: PCT/US2001/001376
Authority: WO
Inventors: Corporation Qlogic; Kevin Vashi; William W. Dennin
Original assignee: Qlogic Corp
Priority date: 2000-01-15
Filing date: 2001-01-16
Publication date: 2001-07-19
Also published as: AU3280801A

Abstract

A filtering and synchronization circuit synchronizes an asynchronous input signal to a clock signal and generates a synchronous output signal. The circuit synchronizes both the leading edge and the trailing edge of the input signal and also blocks or filters out oscillations in the input signal for a period following the edges. The circuit includes an input signal latch which receives the input signal and provides a latched signal which does not change state even if the input signal subsequently changes state until the latched signal is synchronized to the clock signal. The circuit further includes a synchronizer which synchronizes the latched signal with the clock signal. The synchronizer provides feedback signals to the input signal latch to permit the input signal latch to recognize a change in the state of the input signal only after the synchronizer has synchronized the previous state of the input signal. The feedback signals can be selectively delayed to extend the time during which the input signal latch does not recognize changes in the state of the input signal.

Description

CIRCUIT AND METHOD FOR FILTERING OSCILLATIONS AND SYNCHRONIZING SIGNALS

Background of the Invention

Field of the Invention

The present invention relates generally to circuits. Specifically, the invention relates to a circuit and method for blocking or filtering out oscillations of a signal and for synchronizing a signal to a local clock.

Description of the Related Art

Computer systems commonly include one or more peripheral storage devices that are used to store and/or provide access to data. One common type of peripheral storage device is a hard disk drive. Other types of peripheral storage devices include tape drives, CD drives (both read-only and read/write), and DVD devices. The most basic parts of a hard disk drive include at least one platter or "disk" that is rotated, an actuator that moves a transducer to various locations over the disk, and electrical circuitry that is used to write and read data to and from the disk. The disk drive also includes circuitry for encoding data so that data can be successfully retrieved from and written to the disk surface. The circuitry for encoding the data and circuitry that is used to perform the read and write operations on the disk is usually in a controller. The controller may be an integrated circuit placed within the hard disk drive. A disk drive microprocessor can be either embedded within or external to the controller integrated circuit.

The microprocessor controls most of the operations of the disk drive by configuring and monitoring the operation of the controller. For example, a host computer can initiate an operation by sending the microprocessor and/or the controller a read command. The microprocessor recognizes the command and sets up registers in the controller to perform the read operation. The data are then read from the disk into a buffer. When a minimum amount of data are in the buffer, the microprocessor sets up the controller to send the data from the buffer to the host.

The controller and the microprocessor employ signals to control the transfer of data. For example, the microprocessor generates a handshaking pulse along with control and address information to indicate a sector to transfer from the platter to the data port. The controller detects the pulse and retrieves the data from the platter. As data are retrieved from the platter, the controller generates pulses to let the processor know that data are available on the bus.

When a signal is generated on a line in a digital environment, the signal transitions between logical levels are not perfect. Many transitions are accompanied by some noise, in the form of oscillations, occurring near the time the signal changes states. The problem can be especially disruptive to high frequency systems where signal transitions are close together. Circuitry used to detect pulses generated on a signal line is usually constructed such that it reacts to a transition either from a high to low logical level or from a low to high logical level. For example, if the input signal is an interrupt signal or a handshake signal, either a particular rising edge (low-to-high transition) or falling edge (high-to-low transition) is used to indicate or initiate an event. Unwanted oscillations in pulses can sometimes resemble a series of consecutive pulses. When signals are used to control data transfers, the oscillations can be erroneously detected as two pulses, instead of one, and can lead to errors in operation. Therefore, there is a need for a circuit that can detect pulses while filtering out unwanted oscillations.

Digital circuits in an electronic system are typically controlled by a common system clock signal or by a plurality of clock signals derived from a common system clock signal. Thus, the circuits are "synchronized" with respect to each other such that a signal generated by a first circuit in the system can be received by and clocked into other circuits in the system because the signal generated by the first circuit has a known phase relationship with respect to the common system clock signal.

The known phase relationships typically do not exist for circuits that are controlled by independent clock signals. For example, a peripheral component of a computer system often uses an independent clock such that the peripheral component operates at a known frequency irrespective of the operating frequency of the computer system to which the peripheral component is interconnected. Although the clock signals of a peripheral component and a computer system may have the same or similar frequencies, even very small differences in the clock frequencies may cause the phase relationships between the clock signals to vary. Thus, the independent clock signals are "asynchronous" with respect to each other. If a signal is generated by a circuit controlled by a clock which is asynchronous with the system clock of a computer system, the signal cannot be simply provided to the circuits of the computer system and clocked by the clock signals derived from the system clock. Rather, the signal must be synchronized to the system clock before the signal can be applied to the circuits of the computer system. Synchronization of an asynchronous signal is accomplished by outputting a reproduction of the asynchronous signal in phase with a local system clock. In some applications, many synchronization circuits operate only to synchronize a particular edge of an asynchronous input signal. The actual state of the input signal may not be relevant and the opposite transition may not need to be synchronized. In other applications, the current states of input signals may be relevant, and it may be necessary to synchronize both the transition to each state and the transition from each state. For example, when a pulse signal is transmitted, it may be of variable width and rate, depending on the application. There is a need, when operating with certain signals, to know when both a leading edge and a falling edge of the same signal occur. For example, in the new ATA protocol, Ultra-DMA, data are clocked on both edges of a signal. When receiving data, the system has to detect when both edges occur to determine when data are available. Thus, a synchronization circuit that synchronizes both transitions is needed.

Summary of the Invention A circuit is also provided for adaptivelγ blocking or filtering out oscillations in an input signal. The oscillations of the input signal are adaptivelγ filtered by selecting a first period during which falling edges of the input signal are blocked out, and a second period during which rising edges of the input signal are blocked out. The circuit is thereby able to filter out oscillations for variable periods of time. A register is used to store values for the two blocking periods. The register values are compared to counters that count the number of clock cycles following the detection of an edge. The circuit controls input latches such that a latch is enabled once the blocking period is over. Another aspect of the invention relates to a circuit which filters out the oscillations for a variable masking period negotiated according to a chosen protocol used for signaling. A first masking period can be seen as corresponding to a minimum signal width, while a second masking period can be seen as corresponding to a minimum time between signals. By properly setting the two masking periods, the circuit can be effectively used to provide optimal filtration of oscillation for a chosen protocol.

One aspect of the present invention is an oscillation-blocking circuit that receives an input signal with oscillations and generates an output signal without oscillations. The circuit comprises a detector adapted to detect a first logic level and a second logic level of the input signal. A delay generator is coupled to the detector. The delay generator is adapted to generate an output signal corresponding to the input signal after the detector detects a transition from the first logic level to the second logic level of the input signal. The delay generator is further adapted to disable the detector from detecting a subsequent transition in the logic level of the input signal during a first configurable delay period. A register within the delay generator is adapted to store the first configurable delay period. A counter within the delay generator is adapted to count a number of system clock cycles after the detector detects a transition from the first logic level to the second logic level of the input signal. The delay generator enables the detector to detect a subsequent transition in the logic level of the input signal when the number of system clock cycles counted by the counter matches the delay period. Preferably, the register stores a second configurable delay period during which the delay generator disables the detector from detecting a transition in the input signal from the second logic level to the first logic level of the input signal. In the preferred embodiment, a delay selector selects between the first and second configurable delay periods depending on the transition of the input signal detected by the detector. In particularly preferred embodiments, the circuit further comprises a synchronization circuit adapted to synchronize the input signal to a clock signal and to generate a synchronized output.

Another aspect of the present invention is a method of blocking oscillations in an input signal. The method detects a transition between a first logic level and a second logic level of the input signal. The method generates an output signal corresponding to the input signal after detecting the transition from the first logic level to the second logic level of the input signal. The method disables detection of a subsequent transition in the logic level of the input signal during a first configurable delay period. The method counts a number of clock cycles after detecting the transition from the first logic level to the second logic level of the input signal. The method enables detection of a subsequent transition in the logic level of the input signal when the number of clock cycles counted matches the delay period. Preferably, the method also detects a subsequent transition between the second logic level and the first logic level of the input signal, generates an output signal corresponding to the input signal after detecting the transition from the second logic level to the first logic level of the input signal; disables detection of a subsequent transition in the logic level of the input signal during a second configurable delay period; counts a number of clock cycles after detecting the transition from the second logic level to the first logic level of the input signal; and enables detection of a subsequent transition in the logic level of the input signal when the number of clock cycles counted matches the second delay period. Another aspect of the present invention is an oscillation filtering circuit that receives an input pulse having two logic levels and at least two transitions from one logic level to the other logic level and that generates an output pulse of a predefined minimum width that is free of oscillations. The circuit comprises an edge selector adapted to select one of the edges of the input pulse to which to react by propagating a logic level following said edge, wherein the selection of the edge depends on a control signal. A latch is adapted to receive and hold the propagated level such that the propagated level is available at an output. A delay selector is adapted to receive the propagated level. The delay selector outputs the propagated level and generates the control signal to the edge selector to select a second edge of the input pulse after a predetermined number of clock cycles.

Another aspect of the present invention is a method of detecting an input pulse. The method detects a leading edge of an input pulse. The method disables the detection of a subsequent edge of the input pulse during a first predetermined time period after detecting the leading edge. The method counts a number of system clock cycles after detecting the leading edge. The method enables detection of a subsequent edge of the input pulse when the number of system clock cycles counted matches the time period.

Brief Description of the Drawings The present invention will be described below in connection with the accompanying drawings in which:

Figure 1 illustrates a logic diagram of an embodiment of an oscillation blocking circuit;

Figure 2 (comprising Figures 2A-2J) is a timing diagram that illustrates the operation of the embodiment of Figure 1;

Figure 3 (comprising Figures 3A-3J) is an additional timing diagram that illustrates the operation of the embodiment of Figure 1;

Figure 4 illustrates a logic diagram of an oscillation blocking circuit in accordance with the present invention;

Figure 5 is a logic diagram of one embodiment of a variable delay generator within the embodiment of Figure 4;

Figure 6 is a timing diagram that illustrates the results of the variable delay generator of Figure 5; Figures 7A-7L are exemplifying timing diagrams that illustrate the operation of the circuit of Figure 4; and

Figures 8A-8I are exemplifying timing diagrams that illustrates the operation of the variable delay generator of Figure 5.

Detailed Description of the Preferred Embodiment

Figure 1 illustrates an exemplary synchronization circuit 100 which will be used to explain the basic operation of one mode of the present invention. The circuit 100 comprises an input signal selector and latch circuit

102 and a signal synchronizer 104. As described below, the input signal selector and latch circuit 102 receives the input signal and latches the input signal until the latched input signal has been synchronized by the signal synchronizer 104. The input signal and latch circuit 102 receives feedback from the signal synchronizer 104 which indicates when the synchronization has been completed and controls the logic level of the input signal to which the input signal selector and latch circuit 102 is currently responsive.

The input signal selector and latch circuit 102 comprises an inverter 1 10, a first NAND gate 1 12, a second NAND gate 114, a third NAND gate 1 16 and a fourth NAND gate 1 18. The signal synchronizer 104 comprises a first D-type flip-flop 120 and a second D-type flip-flop 122.

The inverter 110 has an input 130 and an output 132. The first NAND gate 1 12 has a first input 140, a second input 142 and an output 144. The second NAND gate 1 14 has a first input 150, a second input 152 and an output 154. The third NAND gate 1 16 has a first input 160, a second input 162 and an output 164. The fourth NAND gate 114 has a first input 170, a second input 172 and an output 174.

The first flip-flop 120 has an inverted clock ( CLK ) input 180, a data (D) input 182, a true (Q) output 184 and a complement ( Q ) output 186. The first flip-flop 120 may also have an active low reset ( R ) input 188. The second flip-flop 122 has a clock (CLK) input 190, a data (D) input 192, a true (Q) output 194 and a complement ( Q ) output 196. The second flip-flop 122 may also have an active low reset ( R ) input 198. The input 130 of the inverter 1 10 and the first input 140 of the first NAND gate 1 12 are connected together and are connected to an input line 200 which receives an input signal (INPUT) that is to be synchronized. The output 132 of the inverter 1 10 generates a signal A. The output 132 is connected to the first input 150 of the second NAND gate 1 14. The second input 142 of the first NAND gate 1 12 is connected to the ( Q ) output 196 of the second flip- flop 122. The ( Q ) output 196 generates a signal H which will be described below. The second input 152 of the second NAND gate 1 14 is connected to the Q output 194 of the second flip-flop 122. The Q output 194 generates a signal G which will be described below. As will be understood from the following description, the signal G and the signal H together comprise a feedback signal from the signal synchronizer 104 to the input signal selector and latch circuit 102.

The output 144 of the first NAND gate 112 generates a signal B which is provided to the first input 160 of the third NAND gate 1 16. The output 154 of the second NAND gate 1 14 generates a signal C which is provided to the first input 170 of the fourth NAND gate 1 18. As will be understood from the following description, the inverter 1 10, the first NAND gate 112 and the second NAND gate 1 14 operate as an input level selector portion of the input signal selector and latch circuit 102. That is, the input level selector portion is responsive to the feedback signal to determine which level of the INPUT signal causes the output of the input signal selector and latch circuit 102 to change state.

The output 164 of the third NAND gate 1 16 generates a signal D which is provided to the second input 172 of the fourth NAND gate 118 and to the D input 182 of the first flip-flop 120. The output 174 of the fourth NAND gate 1 18 generates a signal E which is provided to the second input 162 of the third NAND gate 1 16. Thus, as will be described more fully below, the third NAND gate 1 16 and the fourth NAND gate 1 18 operate as the latch portion of the input signal selector and latch circuit 102. The latch portion receives the B signal and the C signal from the selector portion, and the D signal changes from a first latched output state to a second latched output state when the corresponding B signal or the C signal transitions to a low logic level.

The Q output 184 of the first flip-flop 120 generates a signal F which is provided to the D input 192 of the second flip-flop 122. The ( Q ) output 186 of the first flip-flop 120 is not connected in the embodiment of Figure 1.

The Q output 194 of the second flip-flop 122 is the G signal which is also provided as the synchronized output signal (OUTPUT) on an output signal line 202. The G signal is also provided as a first feedback signal to the input signal selector and latch circuit 102. The ( Q ) output 196 of the second flip-flop 122 is the H signal which is provided as a second feedback signal to the input signal selector and latch 102. It should be understood that because the H signal is the inverse (i.e., complement) of the G signal, only a single signal needs to be fed back to the input selector and latch circuit 102 and that the signal can be inverted within the input selector and latch circuit 102. Thus, the two signals can be considered as a single feedback signal.

The inverted clock input ( CLK ) of the first flip-flop 120 and the πoninverted clock input (CLK) of the second flip-flop 122 are connected to receive a system clock (SYSCLK) signal on a SYSCLK line 204. It should be understood that the first flip-flop 120 and the second flip-flop 122 are edge-triggered flip-flops wherein the signal on the respective D input is propagated to the respective 0 output on the active edge of the signal applied to the clock input line. Thus, the first flip-flop 120 is triggered by the high-to-low transition of the system clock signal on the line 204 in the middle of each cycle of the system clock, and the second flip-flop 122 is triggered on the low-to-high transition of the system clock signal on the line 204 at the beginning of each cycle of the system clock (where the beginning of a system clock cycle is understood to be the low-to-high transition of the system clock).

The reset input 188 of the first flip-flop 120 and the reset input 198 of the second flip-flop 122 are connected to a reset line 206 which is connected to receive an active low ( RESET ) input signal. Optionally, the reset line 206 can be connected to a pullup signal to maintain the reset line 206 at an inactive high signal level.

The operation of the synchronization circuit 100 can be understood by referring to the timing diagrams in Figure 2 (comprising Figures 2A-2J). Figure 2A illustrates the system clock (SYSCLK) signal 300 to which the input signal is to be synchronized. Figure 2B illustrates the asynchronous INPUT signal 302 to be synchronized to the system clock signal 300. Figure 2C illustrates the A signal 304 at the output 132 of the inverter 1 10. Figure 2D illustrates the B signal 306 on the output 144 of the first NAND gate 1 12. Figure 2E illustrates the C signal 308 on the output 154 of the second NAND gate 1 14. Figure 2F illustrates the D signal 310 on the output 164 of the third NAND gate 1 16. Figure 2G illustrates the E signal 312 on the output 174 of the fourth NAND gate 1 18. Figure 2H illustrates the F signal 314 on the Q output 184 of the first flip-flop 120. Figure 21 illustrates the G signal 316 on the Q output 194 of the second flip-flop 122 which is also the OUTPUT signal on the line 202. Figure 2J illustrates the H signal 318 on the ( Q ) output 196 of the second flip-flop 122. In Figures 2B-2J, the signals are shown at the left margin with their respective logic levels when the INPUT signal 302 has been at a logic zero (i.e., low level) for a sufficient time for the circuit 100 to have reached a steady- state condition.

The SYSCLK signal 300 in Figure 2A is illustrated as a generally square wave signal (i.e., a signal having an approximately 50 percent duty cycle of high and low logic levels). At the beginning of each cycle, the signal 300 switches from a low logic level to a high logic level at a low-to-high transition (rising edge) 330. In the middle of each cycle, the signal 300 switches from a high logic level to a low logic level at a high-to-low transition (falling edge) 332. At the end of each cycle, the signal 300 switches from a low logic level to a high logic level at the next rising edge 330 which is also the beginning of the next cycle of the signal 300. The INPUT signal 302 in Figure 2B is an asynchronous input signal which has a low state and a high state.

Either state of the INPUT signal may be considered an active state because the circuit 100 operates to synchronize the transitions of the INPUT signal 302 from either state to the other state and also operates to reproduce the current logic level of the INPUT signal 302 when the INPUT signal 302 remains at either logic level. Because the INPUT signal 302 is asynchronous, a transition in the logic level of the INPUT signal 302 can occur at any time with respect to the SYSCLK signal 300. For example, in Figure 2B, the INPUT signal 302 has a first low-to-high transition 340 during the second half of a cycle of the SYSCLK signal 300 in Figure 2A and has a first high-to-low transition 342 during the first half of a subsequent cycle of the SYSCLK signal 300. Thereafter, the INPUT signal 302 has a second low-to-high transition 344 during the first half of a cycle of the SYSCLK signal 300, followed by a second high-to-low transition 346 during the same half cycle of the SYSCLK signal 300. The A signal 304 in Figure 2C is the complement of the INPUT signal 302 delayed by a small propagation delay. Thus, the A signal 304 has a first high-to-low transition 350 (corresponding to the first low-to-high transition 340 of the INPUT signal 302), followed by a first low-to-high transition 352, a second high-to-low transition 354 and a second low-to-high transition 356.

As illustrated in Figure 2D, the first low-to-high transition 340 of the INPUT signal 302 also causes a high-to- low transition 360 in the B signal 306 on the output 144 of the first NAND gate 1 12, because, as illustrated in Figure 2J, the H signal 318 is at a high logic level. Thus, when the low-to-high transition 340 occurs, both inputs (140, 142) to the first NAND gate 1 12 are active high, and the output 144 becomes active low.

Although the A signal 304 makes the high-to-low transition 350 on the input 150 of the second NAND gate 1 14, the C signal 308 on the output 154 of the second NAND gate 1 14 does not change because the G signal 316 (Figure 21) is already low which forces the output 154 high.

The high-to-low transition 360 of the B signal 306 on the input 160 of the third NAND gate 116 causes a low-to-high transition 362 of the D signal 310 (Figure 2F) on the output 164 of the third NAND gate 1 16. The low-to- high transition 362 of the D signal 310 on the input 172 of the fourth NAND gate 1 18 causes a high-to-low transition 364 of the signal E (Figure 2G) on the output 174 of the fourth NAND gate 118 because the signal D on the input 170 is already high. The third NAND gate 1 16 and the fourth NAND gate 1 18 operate as a cross-coupled flip-flop. That is, the low state of the E signal is coupled to the input 162 of the third NAND gate 1 16 to cause the D signal on the output 164 of the third NAND gate 1 16 to remain high irrespective of whether the INPUT signal 302 changes logic levels until, as described below, the synchronization of the low-to-high transition 340 of the INPUT signal 302 has been completed. This has the advantage that a short pulse on the INPUT signal 302 is recognized and synchronized, as will also be described more fully below. A 'pulse' is defined herein as a rising edge followed by a falling edge of a signal.

The D signal is provided to the input 182 of the first flip-flop 120. As discussed above, the first flip-flop 120 is triggered by falling edges 332 of the SYSCLK signal 300. Thus, on the next falling edge 332A of the SYSCLK signal 300, the high level of the D signal is clocked into the first flip-flop 120, and, after a short propagation delay, the F signal 314 on the Q output 184 of the first flip-flop 120 makes a low-to-high transition 366. The F signal 314 is provided to the D input 192 of the second flip-flop 122, which, as discussed above, is triggered on the rising edges 330 of the SYSCLK signal 300. Thus, the high level on the F signal 314 is clocked into the second flip-flop 122 on the very next rising edge 330A, and, after a short propagation delay, the G signal on the Q output 194 of the second flip-flop

122 makes a low-to-high transition 368, and the H signal on the ( Q ) output 196 makes a high-to-low transition 370. The high logic level of the G signal 316 is fed back to the second input 152 of the second NAND gate 1 14; however, as illustrated, the A signal on the first input 150 is still at a low level, which forces the C signal on the output 154 high. Thus, the high logic level of the G signal 316 has no effect at this time.

The low logic level of the H signal 318 is fed back to the second input 142 of the first NAND gate 1 12. Although the INPUT signal 302 remains high in this example, the low logic level of the H signal 318 causes the B signal 306 on the output 144 of the first NAND gate 1 12 to make a low-to-high transition 372. The low-to-high transition 372 of the B signal on the first input 160 of the third NAND gate 1 16 has no immediate effect for this example because the E signal 312 on the second input 162 remains low and thus causes the D signal 310 on the output 164 to remain high. Thus, the first flip-flop 120 will again clock a high logic level through to the F signal 314 on the output 184 on the next falling edge 332B. Similarly, the second flip-flop 122 will again clock the high logic level F signal 314 to the G signal 316 and will clock the complement (i.e., low logic level) to the H signal 318 on the next rising edge 330B.

When the INPUT signal 302 makes the high-to-low transition 342, the circuit operates in a similar manner to clock the low logic level through to the G signal 316. It should be noted however that the A signal 304 (i.e., the complement of the INPUT signal 302) initiates the operation. In particular, when the INPUT signal 302 makes the high-to-low transition 342 at the first input 140 of the first NAND gate 1 12, the transition 342 has no effect on the B signal on the output 144 of the first NAND gate 1 12 because the H signal 318 on the second input 142 is already at a low logic level to force the B signal to a high logic level. On the other hand, the low-to-high transition 352 of the A signal 304 on the first input 150 of the second NAND gate 1 14 causes the C signal 308 to make a high-to-low transition 380, which in turn causes the E signal 312 to make a low-to-high transition 382. At this time, both the B signal 306 and the E signal 312 are at a high logic level at the inputs 160, 162 of the third NAND gate 1 16. Thus, the D signal 310 on the output 164 makes a high-to-low transition 384. The low logic level on the D signal 310 is clocked into the first flip-flop 120 on the next falling edge 332C of the SYSCLK signal 300, causing the F signal 314 to make a high-to-low transition 386. The low logic level on the F signal 314 is clocked into the second flip-flop 122 on the next rising edge 330C of the SYSCLK signal 300 causing the G signal 316 to make a high-to-low transition 388 and the H signal 318 to make a low-to-high transition 390. The low logic level of the G signal 316 causes the C signal 308 to make a low-to-high transition 392.

It can be seen from the foregoing that the circuit 100 operates to generate an OUTPUT signal (corresponding to the G signal 316) on the line 202 that is a reproduction of the INPUT signal 302 synchronized with the rising edges 330 of the SYSCLK signal 300. Thus, the OUTPUT signal 316 is synchronized with other circuits which are clocked by the SYSCLK signal 300.

It should be appreciated that the first feedback signal (G) and the second feedback signal (H) are complementary (i.e., the signal G and the signal H always have opposite logic levels). Thus, one feedback signal can be readily generated by inverting the other feedback signal. Thus, the two feedback signals can be considered as being a single feedback signal which has a first active level which enables the first NAND gate 1 12 to be responsive to the next low-to-high transition of the INPUT signal on the line 200 and which has a second active level which enables the second NAND gate 1 14 to be responsive to the next high-to-low transition of the INPUT signal.

The foregoing example described an INPUT signal 302 having a duration of at least one cycle of the SYSCLK signal 300. As further illustrated in Figures 2A-2J, the INPUT signal 302 can have a duration shorter than one cycle, and can be a pulse having both the low-to-high transition 344 and the high-to-low transition 346 occur between the transition 330 and the transition 332 of the SYSCLK signal 300. As illustrated, the low-to-high transition 344 of the INPUT signal 302 causes the high-to-low transition 354 in the A signal 304. The low-to-high transition 344 of the INPUT signal 302 also causes a high-to-low transition 400 of the B signal 306. The high-to-low transition 400 of the B signal 306 causes a low-to-high transition 402 of the D signal 310, which causes a high-to-low transition 404 of the E signal 312. The low logic level on the E signal 312 causes the cross-coupled flip-flop formed by the third NAND gate 116 and the fourth NAND gate 1 18 to latch up. Thus, although the INPUT signal 302 makes the high-to-low transition 346 which results in the low-to-high transition of the A signal 304 and a low-to-high transition of 406 of the B signal 306, the D signal 310 does not change and remains at high logic level. Thus, although the INPUT signal 302 is no longer at a high logic level when the next falling edge 332D of the SYSCLK 300 occurs, the high logic level of the D signal 310 is clocked into the first flip-flop 120 which causes a low-to-high transition 408 of the F signal 314. Thereafter, at the next rising edge 330D of the SYSCLK signal 300, the high level of the F signal 314 is clocked into the second flip-flop 122 to cause a low-to-high transition 410 of the G signal 316 and a high-to-low transition 412 of the H signal 318.

In this example, the high-to-low transition 412 of the H signal 318 has no immediate effect because the INPUT signal 302 on the first input 140 of the first NAND gate 112 is already low to force the B signal 306 high. On the other hand, the low-to-high transition 410 of the G signal 316 has an immediate effect because the A signal 304 on the first input 150 of the second NAND gate 114 is already high. Thus, the low-to-high transition 410 of the G signal 316 causes a high-to-low transition 414 of the C signal 308, which causes a low-to-high transition 416 of the E signal 312. The high level of the E signal 314 on the second input 162 of the third NAND gate 1 16 combined with the already high B signal 308 on the first input 160 causes the D signal 310 on the output 164 of the third NAND gate 116 to make a high-to-low transition 418.

The low logic level of the D signal 310 is clocked into the first flip-flop 120 on the next falling edge 332E of the SYSCLK signal 300 to cause the F signal 314 to make a high-to-low transition 420. The low logic level on the F signal 314 is clocked into the second flip-flop 122 on the next rising edge 330E of the SYSCLK 300 to cause the G signal 316 to make a high-to-low transition 422 and to cause the H signal to make a low-to-high transition 424. It can be seen in this second example that the circuit 100 operates to synchronize a pulse of the INPUT signal 302 that has a duration less than a cycle of the SYSCLK signal 300 and which may have changed to its original logic level before the next falling edge of the SYSCLK signal 300 occurs. The circuit operates to make every output pulse have a duration of at least one cycle of the SYSCLK signal 300 and to have rising edges and falling edges synchronous with the rising edges of the SYSCLK signal 300. It can be additionally seen that in the two preceding examples, the circuit 100 filters out oscillations occurring after the low-to-high or high-to-low signal transition as is illustrated by Figures 3A-3J. With reference to Figure 3B, the input signal 302 transitions from low-to-high on an edge 510. The input signal 302 oscillates for a time following the assertion of the edge 510. Referring to Figure 3D, the B signal 306 changes to a low logic level on an edge 508 at the time the edge 510 reaches the NAND gate 1 12 since the gate is enabled by the high logic level from the H signal. The B signal then demonstrates the oscillation 514 that has propagated through the NAND gate 1 12. The first falling edge of the B signal forces the D signal 310 of the NAND gate 1 16 to a high level as illustrated in Figure 3F. The oscillation 514 in the B signal does not propagate to the D signal 310 because of the operation of the cross-coupled NAND gates 1 16, 188 of Figure 1. The D signal 310 is clocked into the flip-flop 120 on the trailing edge 526 of the system clock 300 to provide a rising edge 524 to the F signal 314 and a resultant oscillation-free G output signal as is illustrated by Figures 3H and 31.

The oscillation in the input signal 302 following the edge 510 does not propagate to the D signal because the cross-coupled NAND gates 1 16, 1 18 prevent such propagation. The cross-coupled NAND gates 1 16, 1 18 act as a SET-RESET latch. In a SET-RESET latch, only a logical high on the SET line can produce a high level output and only a logical high on the RESET line can produce a low level output. In the circuit 100 of Figure 1, the input 160 of the gate 1 16 is an inverted SET and the input 170 of the gate 1 18 is an inverted RESET input.

Therefore, once a low level signal propagates through to the B signal line of the cross-coupled NAND gates 1 16, 1 18, the latch is set so as to provide a high level output. Changes in the B signal do not affect the high level output unless the C signal goes low to reset the latch. The C signal cannot go low until the NAND gate 1 14 is enabled because the G signal low level forces the NAND gate 1 14 output to a high level. Therefore, the C signal cannot go low and reset the cross-coupled NAND gates 1 16, 1 18 until the original rising edge detected by the NAND gate 1 12 reaches the output of the second flip-flop 122 to change the G signal to a high level to thereby enable the NAND gate 1 12.

The first flip-flop 120 and the second flip-flop 122 operate together to provide a minimum of V≥ clock cycle of filtering. In particular, a leading edge or a trailing edge of the input signal having an oscillation that lasts for less than a % system clock cycle causes one and only one change in the output signal level. If the oscillation lasts longer than a ¹/2 system clock cycle, it is possible for the initial portion of the oscillation at the enabled signal level to be clocked into the first flip-flop 120 on the falling edge of the system clock and to then be clocked into the second flip-flop 122 on the next rising edge of the system clock. The G signal and the H signal change states to enable an opposite level to be clocked into the first flip-flop 120. Therefore, circuit of Figure 1 is able to reliably filter out oscillations in the INPUT signal that occur up to % system clock cycle after an assertion of an edge.

Variable Delay Generator

Although the circuit of Figure 1 is able to filter out oscillations that last for up to 14 system clock cycle, as system clock cycles become shorter (i.e., the system clock becomes faster), ¹i clock cycle of oscillation filtering may not be adequate. Figure 4 illustrates a logic diagram of an embodiment of the present invention which is adapted for use in systems where oscillation filtering for a larger number of clock cycles is desired. Specifically, Figure 4 illustrates a circuit 600 with a variable delay generator 622 (shown in Figure 5) that is programmable to adaptively filter out oscillations in the INPUT signal 200 for a variable number of system clock cycles. For example, the circuit 600 of Figure 4 may filter out oscillations 952, 954 in the INPUT signal 950 that are longer than a system clock cycle, as shown in Figure 6 and described further below. Figure 6 is a timing diagram that illustrates the results of the variable delay generator 622 of Figure 5.

The circuit 600 of Figure 4 is substantially similar to the circuit 100 of Figure 1 with modifications described below. In contrast to the circuit 100 of Figure 1 , the circuit 600 of Figure 4 further comprises a variable delay generator 622, a fifth NAND gate 806 and a sixth NAND gate 810. In Figure 4, the output Q 194 of the second flip- flop 122 is connected to an input 620 of a variable delay generator 622 instead of being connected to the input 152 of the NAND gate 1 14. The inverted output ( Q ) 198 of the second flip-flop 122 is not connected in Figure 4.

The variable delay generator 622 receives a G input 620 coupled to the G output of the second flip-flop 122, a WRAP BACK input 819 coupled to a WRAP BACK signal line 818, a clock CLK input 630 synchronized by the system clock SYSCLK line 204, an inverted reset input R 820 coupled to the reset signal line ( RESET ) 206, a data input 817 coupled to a data bus 816. The data bus 816 has eight data signals D7-D0. The delay generator 622 receives a LOAD DELAYS input 815, which is coupled to a LOAD DELAYS signal line 814. The delay generator 622 generates a DEL SEL1 output on a line 800 (also labeled as T) coupled to an input 828 of the fifth NAND gate 806. The delay generator 622 also generates a DEL_SEL2 output on a line 802 (also labeled as 'J') coupled to an input 830 of the sixth NAND gate 810. A FEEDBACK ENABLE signal 804 is also coupled to input of the fifth and sixth NAND gates 806, 810. The output 808 of the fifth NAND gate 806 is coupled to the input 142 of the first NAND gate 1 12. The output 812 of the sixth NAND gate 810 is coupled to an input 152 of the second NAND gate 1 14.

The WRAP BACK signal line 818, the FEEDBACK ENABLE signal line 804, the data bus D7-D0 816 and LOAD DELAYS line 814 are provided from a data source (not shown), such as, for example, a microprocessor, a SCSI controller, or the like, which provides control and data signals to the circuit 600.

The operation of the circuit 600 of Figure 4 is described with reference to Figures 5-8. The delay generator 622 has two modes of operation. In a first mode, the FEEDBACK ENABLE signal 804 (Figure 4) is set to a high logic level, and the WRAP BACK signal 818 is also set to a high logic level. In the first mode, the circuit 600 and the signals A, B, C, D, E, F, and G in Figure 4 function in a similar manner to that described above with reference to Figures 1, 2 and 3. In the first mode, the DEL_SEL1 signal of the delay generator 622 supplies an equivalent to the H signal 196 shown in Figure 1, and the DEL_SEL2 signal of the delay generator 622 supplies an equivalent G signal 194 shown in Figure 1. The DEL_SEL1 signal is provided as an input to the NAND gate 806. The DEL_SEL2 signal is provided as an input to the NAND gate 810. Note that the DEL_SEL1 signal and the DEL_SEL2 signal are inverted with respect to the H signal and the G signal to compensate for the inverting effects of the NAND gates 806, 810. In a second mode, the FEEDBACK ENABLE signal 804 is set to a high logic level, and the WRAP BACK signal

818 is set to a low logic level. In the second mode, the variable delay generator 622 enables the circuit 600 to block or filter out oscillations 952, 954 in the INPUT signal 200, as shown in Figure 6. Specifically, in Figure 6, the circuit 600 detects the first rising edge 951 of the INPUT signal 950. Thereafter, the delay generator 622 within the circuit 600 blocks any oscillations 952 after the first rising edge 951 of the INPUT signal 950 for a predetermined delay period 958. The delay generator 622 of Figure 4 provides the DEL SEL1 signal on the line 800 and the DEL SEL2 signal on the line 802 as in the first mode; however, in the second mode, the two signals are delayed by a predetermined number of clock cycles of the SYSCLK signal 300 (Figure 6).

In Figure 6, during a first delay period 958, zeros on the INPUT signal line 950 (INPUT signal line 200 in Figure 4) are ignored by the circuit 600. The delay period 958 during which zeros on the INPUT signal line 200 are ignored is referred to herein as an "assertion delay" period. The length of the assertion delay period is preferably determined by a variable stored within a register 922 (Figure 5 described below) in the delay generator 622. The assertion delay period may be modified by data on the data bus 816 from the data source (not shown).

In Figure 6, during a second delay period 960, zeros on the INPUT signal line 950 (INPUT signal line 200 in Figure 4) are accepted by the circuit 600, and ones on the INPUT signal line 950 are ignored. In other words, the circuit 600 detects the first falling edge 953 of the INPUT signal 950, and the delay generator 622 blocks any oscillations 954 after the first falling edge 953 of the INPUT signal 950. The delay period 960 during which zeros on the INPUT signal line 950 are accepted and ones on the INPUT signal line 200 are ignored is referred to herein as a "de-assertion delay" period. The length of the de-assertion delay period is determined by a variable stored within the register 922 (Figure 5 described below) in the delay generator 622. The de-assertion delay period may also be modified by data on the data bus 816 from the data source (not shown). The assertion delay period (for the rising edge) may be controlled independently of the de assertion delay period (for the falling edge) and vice versa so that the two periods may be the same or so that the two periods may be different.

In the second mode of operation, when the FEEDBACK signal 804 (Figure 4) is enabled, and the DEL_SEL1 and DEL_SEL2 signals 800, 802 are transmitted to the inputs 142, 152 respectively, the G signal 194 does not control the NAND gates 1 14, 1 12, directly. Rather, the G signal 194 controls the operation of the delay generator 622, and the outputs of the delay generator 622 control the NAND gates 1 14, 1 12.

Figures 7A-7L are exemplifying timing diagrams that illustrate the operation of the circuit 600 of Figure 4 in the second mode of operation when the feedback signal is enabled and the WRAP BACK signal is inactive. Figures 7A 7J are substantially similar to Figures 2A-2J. When the delay generator 622 detects the first iow-to-high transition 368 of the G signal 316 in Figure 71, the delay generator 622 begins to count the number of subsequent clock cycles of the SYSCLK signal 300. After the predetermined assertion delay period is over, the delay generator 622 changes the logic levels of the J and K signals 501, 503 at transitions 528, 530 respectively. The DEL SEL2 (J) signal 802 is a delayed representation of the G signal 194, and the DEL_SEL1 (K) signal 800 is a delayed representation of the H signal 196 (Figure 1 ). Because the input latch formed by the third and fourth NAND gates 1 16, 1 18 (Figure 4) cannot change states until the DEL SEL1 and DEL SEL2 signals 800, 802 (and the inputs 142, 152) change states, any oscillations on the INPUT signal 200 are blocked from reaching the first flip-flop 120. Thus, the delay generator 622 may add one or more clock cycles to the minimum Vi clock cycle delay (Figure 3A-J) during which oscillations 952, 954 in the INPUT signal 950 are blocked or filtered out, as shown in Figure 6. As further shown in Figures 7A-7L, after the assertion delay period is over, the delay generator 622 causes a low-to-high transition 528 of the J signal 501 (Figure 7K) and a high-to-low transition 530 of the K signal 503 (Figure 7L). The high logic level of the J signal 501 enables a falling edge 532 of the INPUT signal 302 to pass through the NAND gate 1 12 (Figure 4), which resets the cross-coupled NAND gates 1 16, 1 18 and causes a high-to-low transition 531 in the D signal 310 (Figure 7F). The low level of the D signal 310 causes the first flip-flop 120 (Figure 4) to generate a falling edge 703 of the F signal 314 (Figure 7H). The F signal 314 causes the second flip-flop 122 (Figure 4) to generate a falling edge 534 of the G signal 316 (Figure 71) and to generate a rising edge 707 of the H signal 318 (Figure 7J). The low level of the G signal 316 causes the delay generator 622 to start counting clock cycles for the de assertion delay period.

When the de-assertion delay period is over, the delay generator 622 causes a low-to-high transition 538 in the K signal 503 (Figure 7L) and causes a high-to-low transition 536 in the J signal 501 (Figure 7K). The high level of the K signal 503 propagates via the fifth NAND gate 806 and the NAND gate 1 12 (Figure 4) to enable the detection of another rising edge of the INPUT signal 302 (Figure 7B).

The structure of the delay generator 622 is described with reference to Figures 5-8. Figure 5 is a logic diagram of one embodiment of the variable delay generator 622 within the circuit 600 of Figure 4. The delay generator 622 comprises a first AND gate 822, a first EXCLUSIVE OR (XOR) gate 838, an edge-triggered D flip-flop 846, a second XOR gate 854, a second AND gate 858, a four-bit synchronous counter 872, a four-bit comparator 890, a single-bit, 2:1 multiplexer 902, an eight-bit register 922, an inverter 914 and a four-bit, 2:1 multiplexer 941.

In Figure 5, the first AND gate 822 has two inputs 824, 826 which comprise a MATCH signal and a COUNT ENABLE signal. The first AND gate 822 has an output 832 coupled to an input 834 of the first XOR gate 838 and also coupled to a synchronous reset input 866 of the counter 872. The output 832 is also coupled to the synchronous reset (SYNC RESET) input 866 of the counter 872. The signal on the output 832 is referred to herein as the TOGGLE CLAMP signal.

In Figure 5, the first XOR gate 838 receives a second input 836, referred to herein as the CLAMP signal, the CLAMP signal is generated by an output 844 of the D flip-flop 846. The output of the first XOR gate 838, referred to herein as the PRE-CLAMP signal, is coupled to an input 842 of the D flip-flop 846. The RESET signal on the line

820 is coupled to an active low, asynchronous reset ( R ) input 847 of the D flip-flop 846. The system clock (SYSCLK) 630 is coupled to a clock input 848 of the D flip-flop 846 and to a clock input 870 of the counter 872. A Q output 844 of the D flip-flop 846 is coupled to an input 850 of the second XOR gate 854, to an input 904 of the single-bit, 2:1 multiplexer 902, and to a select input (S) 940 of the four-bit, 2:1- multiplexer 941. In Figure 5, the G signal on the line 620 is coupled to an input of the second XOR gate 654 and an input 906 of the single-bit, 2:1 multiplexer 902. The second XOR gate 654 has an output 856 that is coupled to an input 860 of the second AND gate 858. The WRAP BACK signal 818 is coupled to an inverted input 862 of the second AND gate 858 and to a selection input (S) 910 of the single-bit, 2:1 multiplexed 902. The second AND gate 858 has an output 864 that is coupled to a count enable (CNT ENAB) input 868 of the counter 872. The output 864 of the second AND gate 858 is also fed back to an input 826 of the first AND gate 822.

In Figure 5, the counter 872 generates Q3, 02, Q1 , QO counter output signals on four outputs 874, 876, 878, 880. The counter outputs are coupled to the A3, A2, Al , AO inputs 882, 884, 886, 888 of the comparator 890. The comparator 890 generates an " = " output 892, which is referred to herein as the MATCH signal. The MATCH signal is coupled to the input 824 of the first AND gate 822. The single-bit, 2:1 multiplexer 902 has an output 908 which provides the DEL_SEL1 signal (or the K signal) on the line 800. The output 908 is also coupled to an input 912 of an inverter 914, which has an output 916 which provides the DEL_SEL2 signal (or the J signal) on the line 802.

In Figure 5, the eight-bit register 922 has an eight-bit data input 918 coupled to the data bus 816 to receive the data bits D7-D0. The register 922 also has an edge-triggered clock input 920 coupled to the clock pulse LOAD DELAY signal 814. The register 922 has eight outputs Q7-Q0 which are coupled to the A3-A0 and B3-B0 inputs 938, 936, 934, 932, 930, 928, 926, 924 of the four-bit, 2:1 multiplexer 941. The four-bit, 2:1 multiplexer 941 generates Y3-Y0 signals on four outputs 942, 944, 946, 948. The four-bit, 2:1 multiplexer 941 is controlled by the CLAMP signal on the select input 940. When the CLAMP signal is inactive (i.e., low), the A3-A0 input signals are propagated to the Y3-Y0 outputs. When the CLAMP signal is active (i.e., high), the B3-B0 input signals are propagated to the Y3- YO outputs. The Y3-Y0 signals on the outputs 942, 944, 946, 948 are coupled to the B3-B0 inputs 894, 866, 898, 900 of the comparator 890. In Figure 5, the delay generator 622 is configured by loading the assertion delay (D7-D4) and the de-assertion delay (D3-D0) into the register 922 via the data bus 816. Specifically, the LOAD DELAYS signal on the line 814 is activated by the data source (not shown) to enable the register 922 to store the assertion delay and the de-assertion delay represented by the D7-D0 data on the data bus 816. The stored assertion delay bits on the Q7-Q4 outputs of the register 922 are provided as the A3-A0 inputs of the four-bit, 2:1 multiplexer 941 , and the stored de-assertion delay bits on the Q3-Q0 outputs of the register 922 are provided as the B3-B0 inputs of the four-bit, 2:1 multiplexer 941. As discussed above, the multiplexer 941 provides either the assertion delay bits or the de-assertion delay bits on the Y3-Y0 outputs in accordance with the state of the CLAMP signal on the select line 941.

The operation of the delay generator 622 is described with reference to Figures 4-8. Figures 8A-8I are exemplifying timing diagrams that illustrate the operation of the variable delay generator 622 of Figure 5. In Figures 8A-8I, the circuit 600 is in the second mode of operation, the assertion delay is set to three clock cycles, and the de- assertion delay is set to four clock cycles. Although an assertion delay of three and a de-assertion delay of four are used in this example, the assertion and de-assertion delays may be set to any number by a microprocessor (not shown). In Figure 7B, the INPUT signal 302 makes an initial low-to-high transition 340. As described above with reference to Figures 1 and 2A-2I, the synchronized G signal 316 makes a subsequent low-to-high transition 368 as shown in Figure 71. In Figure 8B, the G signal 700 makes a low-to-high transition 716 as a result of a low-to-high transition of the system clock SYSCLK 204. In Figure 8B, the low-to-high transition 716 of the G signal 700 combined with the initial low logic level of the other input 850 or CLAMP signal (Figure 5) causes the second XOR gate 854 to output a high logic level to the input of the second AND gate 858. In the second mode of operation, the WRAP BACK signal 818 is low and the inverted WRAP BACK signal 818 is high. Thus, with two high inputs, the second AND gate 858 outputs a high logic level, and the COUNT ENABLE signal 702 makes a low-to-high transition 722 (Figure 8C). When the COUNT ENABLE signal 702 becomes high, the counter 872 (Figure 5) begins to count the clock cycles of the SYSCLK 700 and begins to output four-bit binary values 728, 730, 732, 734, 736 (Figure 8D), denoted as Q3-Q0, to the comparator 890 (Figure 5). Specifically, the outputs Q3-Q0 of the counter 872 generates 0001 after the first clock cycle, 0010 after the second clock cycle and 001 1 after the third clock cycle.

In Figure 5, the CLAMP signal on the output 844 of the D flip-flop 846 is initially low. A low state on the select input 940 of the four-bit, 2:1 multiplexer 941 causes the four-bit, 2:1 multiplexer 941 to output the four-bit binary value of the assertion delay to the comparator 890 via the outputs 942, 944, 946, 948. As described above, the assertion delay is three clock cycles in the example shown in Figures 8A-8I. Thus, the four-bit, 2:1 multiplexer 941 outputs a binary value of 001 1 to the comparator 890.

In Figure 5, when the Q3-Q0 signals on the outputs 874, 876, 878, 880 of the counter 872 match the Y3-Y0 signals on the outputs 942-948 of the four-bit, 2:1 multiplexer 941 when the assertion delay is completed, the comparator 890 activates the "= " signal on the output 892 to cause MATCH signal provided to the first AND gate 822 to be activated. As shown in Figure 8E, the MATCH signal 706 has a one clock cycle pulse between a rising edge 748 and a falling edge 750 after the outputs Q3-Q0 704 counts to three. In Figure 5, the combination of the high COUNT ENABLE input 826 and the MATCH signal pulse input 824 causes the first AND gate 822 to output a pulse. Thus, in Figure 8F, the TOGGLE CLAMP signal line 708 experiences a pulse between a rising edge 752 and a falling edge 754. In Figure 5, the TOGGLE CLAMP pulse is input into the synchronous reset (SYNC RESET) input 866 of the counter 872. The synchronous reset applied to the counter 872 does not take effect until the next rising edge of the SYSCLK signal 204, at which time all the Q3-Q0 signals on the outputs 874, 876, 878, 880 are reset to zero.

In Figure 5, the CLAMP signal 844 is initially reset to a low state. A pulse on one input 832 and a low logic level on the other input 836 of the XOR gate 838 causes a low-to-high transition 764 (Figure 8G) on the PRE-CLAMP output 840 of the first XOR gate 838. In Figure 5, when the active PRE-CLAMP signal 840 is provided to the D-input 842 of the D flip-flop 846, the Q output 844 of the D flip-flop 848 makes a low-to-high transition. With a low WRAP BACK signal 818, the low-to-high transition input 904 into the single-bit, 2:1 multiplexer 902 causes a low-to-high transition at the output 908 (DEL_SEL1 ). As shown in Figures 8H-8I, the DEL_SEL1 signal 712 makes a low-to-high transition 768, and the DEL_SEL2 signal 714 (the inverse of the DEL_SEL1 signal 712) makes a high-to-low transition 774. As shown in Figure 6, zeros on the INPUT line 950 are now accepted, and ones on the INPUT line 950 are now ignored.

In addition, the low-to-high transition output 844 of the D flip-flip 846 causes the four-bit, 2:1 multiplexer 941 to now select the de-assertion delay and to output the de-assertion delay to the comparator 890. Moreover, the low-to-high transition on the output 844 of the D flip-flip 846 causes the COUNT ENABLE signal 702 (Figure 8C) to make a high-to-low transition 724. In Figure 7B, when the INPUT signal on the line 302 makes a high-to-low transition 532, the synchronized G signal on the line 312 makes a subsequent, corresponding high-to-low transition 534. In Figure 5, the high-to-low transition 718 of the G signal on the line 620 combined with the high level on the input 850 causes the PRE-COUNT ENABLE signal on the output 856 of the second XOR gate 854 to make a low-to-high transition. The high level on the output 856 of the second XOR gate 854 and the inverted (high) WRAP BACK signal 818 causes the COUNT ENABLE signal on the line 864 to make a corresponding low-to-high transition 726 (Figure 8C). As described above, the high COUNT ENABLE signal on the line 864 enables the counter 872 to begin counting and to sequentially output four-bit binary values 0001 , 0010, 001 1 and 0100 to the comparator 890.

When the comparator 890 detects a match between the output from the counter 872 and the four-bit de- assertion delay period input from the four-bit, 2:1 multiplexer 941 , which in this case is four (0100), the comparator 890 outputs a MATCH signal pulse between a rising edge 748 and a falling edge 750, as shown in Figure 8E. The MATCH signal pulse at the input 826 and the high COUNT ENABLE at the input 826 cause the first AND gate 822 to generate an active TOGGLE CLAMP pulse between a rising edge 752 and a falling edge 754 on the line 708, as shown in Figure 8F. As described above, the TOGGLE CLAMP pulse is input into the synchronous reset (SYNC RESET) input 866 of the counter 872, and, at the next rising edge of the SYSCLK signal 204, all the counter bits Q3-Q0 on the outputs 874-880 are reset to zero.

-IB- In Figure 5, as described above, the initial CLAMP signal 844 is low. A pulse on one input 832 and a low logic level on the other input (CLAMP) 836 causes a high-to-low transition 764 (Figure 8G) on the output 840 (PRE- CLAMP) of the first XOR gate 838. In Figure 5, when the PRE-CLAMP signal 840 is input into the D flip-flop 846, the output 844 of the D flip-flop 846 makes a high-to-low transition. With a low WRAP BACK signal 818, the high-to-low transition input 904 into the single-bit, 2:1 multiplexer 902 causes a high-to-low transition at the DEL_SEL1 signal on the output 908. As shown in Figures 8H-8I, the DEL_SEL1 signal 712 makes a high-to-low transition 768, and the inverted DEL_SEL2 signal 714 makes a low-to-high transition 774. As shown in Figure 6, now ones on the INPUT line 950 are accepted, and zeros on the INPUT line 950 are ignored.

It can be seen from the foregoing that the circuit 600 of Figure 4 provides programmable filtration of the INPUT signal 200 to preclude oscillations on the INPUT signal from causing corresponding oscillations on the synchronized G output signal 202.

In Figure 4, the fifth and sixth NAND gates 806, 810 provide a test mode wherein the FEEDBACK ENABLE signal is set to a low logic level. In the test mode, the circuit 600 synchronizes the INPUT signal 200, but does not block oscillations in the INPUT signal 200. For the circuit 600 of Figure 4, different periods can be set for an expected INPUT signal width and latency

(latency is defined as the time between the falling edge of a signal and the rising edge of the next signal). For example, in one protocol, INPUT pulses have a required minimum width of three system clock cycles and should be separated by at least six system clock cycles. For this protocol, the assertion delay should be set to zero. With this setting, a filtration period of at least 1 % system clock cycles following the rising edge is provided, and oscillations in the INPUT signal following the rising edge are reliably blocked for at least Vh system clock cycles. With this setting, the falling edge of the INPUT pulse can be reliably detected if it is at least k system clock cycles after the rising edge of the pulse. Since the INPUT pulse in the example is defined to be at least three system clock cycles wide, no valid falling edge is ignored.

For this exemplary protocol, the de-assertion delay should be set to three to provide a filtration period following the falling edge of an INPUT pulse. Oscillations in the INPUT signal following the falling edge are reliably filtered up to -Vk clock cycles. The rising edge of the next INPUT pulse can be reliably detected if it is at least Wk system clock cycles after the falling edge of the previous INPUT pulse. Since INPUT pulses are separated by at least six system clock cycles, no valid rising edge of the next pulse is ignored.

Although the foregoing was described in view of an INPUT signal which was normally low and which changed from the low logic level to the high logic level and back to the low logic level, it should be understood that the circuit 600 operates symmetrically. Thus, if the INPUT signal 200 is normally high and has pulses which change from the high logic level to the low logic level and back to the high logic level, the circuit 600 synchronizes the pulses in the manner described above.

It should be further understood that the circuit 600 operates to reproduce the state of the INPUT signal 200 on the G signal 202. The circuit 600 also reproduces the state of the INPUT signal on the J signal 802, but the J signal 802 is delayed. Thus, either the G signal 202 or the J signal 802 may be used as the synchronized output signal. For example, the INPUT signal 200 may be a signal that is asynchronous to the system clock, such as, for example, a SCSI REQ signal or a SCSI ACK signal. For such a signal, the circuit 600 operates to synchronize the signal to the system clock 204.

While preferred embodiments of this invention have been disclosed herein, those skilled in the art will appreciate that changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

WHAT IS CLAIMED IS:

1. An oscillation-blocking circuit that receives an input signal with oscillations and generates an output signal without oscillations, the circuit comprising: a detector adapted to detect a first logic level and a second logic level of the input signal; a delay generator coupled to the detector, the delay generator being adapted to generate an output signal corresponding to the input signal after the detector detects a transition from the first logic level to the second logic level of the input signal, the delay generator being adapted to disable the detector from detecting a subsequent transition in the logic level of the input signal during a first configurable delay period; a register within the delay generator, the register being adapted to store the first configurable delay period; and a counter within the delay generator, the counter being adapted to count a number of system clock cycles after the detector detects a transition from the first logic level to the second logic level of the input signal, wherein the delay generator enables the detector to detect a subsequent transition in the logic level of the input signal when the number of system clock cycles counted by the counter matches the delay period.

2. The circuit of Claim 1, wherein the first logic level is a low logic level, and the second logic level is a high logic level.

3. The circuit of Claim 1 , wherein the first logic level is a high logic level, and the second logic level is a low logic level.

4. The circuit of Claim 1, wherein the register stores a second configurable delay period during which the delay generator disables the detector from detecting a transition in the input signal from the second logic level to the first logic level of the input signal.

5. The circuit of Claim 4, further comprising a delay selector for selecting between the first and second configurable delay periods depending on the transition of the input signal detected by the detector.

6. The circuit of Claim 1, further comprising a synchronization circuit adapted to synchronize the input signal to a clock signal and to generate a synchronized output.

7. A method of blocking oscillations in an input signal comprising: detecting a transition between a first logic level and a second logic level of the input signal- generating an output signal corresponding to the input signal after detecting the transition from the first logic level to the second logic level of the input signal- disabling detection of a subsequent transition in the logic level of the input signal during a first configurable delay period; counting a number of clock cycles after detecting the transition from the first logic level to the second logic level of the input signal; and enabling detection of a subsequent transition in the logic level of the input signal when the number of clock cycles counted matches the delay period.

8. The method of Claim 7, further comprising: detecting a subsequent transition between the second logic level and the first logic level of the input signal- generating an output signal corresponding to the input signal after detecting the transition from the second logic level to the first logic level of the input signal; disabling detection of a subsequent transition in the logic level of the input signal during a second configurable delay period; counting a number of clock cycles after detecting the transition from the second logic level to the first logic level of the input signal; and enabling detection of a subsequent transition in the logic level of the input signal when the number of clock cycles counted matches the second delay period.

9. The method of Claim 7, further comprising loading a new first configurable delay period.

10. An oscillation filtering circuit that receives an input pulse having two logic levels and at least two transitions from one logic level to the other and generates an output pulse of a predefined minimum width that is free of oscillations, said circuit comprising: an edge selector adapted to select one of the edges of the input pulse to which to react by propagating a logic level following said edge, wherein said selection of said edge depends on a control signal; a latch adapted to receive and hold said propagated level such that said propagated level is available at an output; and a delay selector adapted to receive the propagated level, the delay selector outputting said propagated level and generating said control signal to said edge selector to select a second edge of said input pulse after a predetermined number of clock cycles.

1 1. A method of detecting an input pulse, the method comprising: detecting a leading edge of an input pulse; disabling the detection of a subsequent edge of said input pulse during a first predetermined time period after detecting said leading edge; counting a number of system clock cycles after detecting the leading edge; and enabling detection of a subsequent edge of said input pulse when the number of system clock cycles counted matches the time period.