JP4612235B2 - Asynchronous detection circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an asynchronous detection circuit, and more particularly, to an asynchronous detection circuit that detects asynchronous write / read clocks in a speed conversion circuit or a clock transfer circuit using a memory.
[0002]
[Prior art]
This type of asynchronous detection circuit is disclosed in, for example, “Memory Slip Detection Circuit and Memory Slip Detection Method” in JP-A-8-221331. Such an asynchronous detection circuit is widely used for detecting a shift in a write phase and a read phase of a memory.
[0003]
FIG. 4 is a block diagram showing a configuration of a conventional example of an asynchronous detection circuit. The asynchronous detection circuit includes a memory 20, a write address counter (WRITE COUNT) 21, a read address counter (READ COUNT) 22, and a memory slip detection circuit (SLIP CHK) 23. The memory 20 stores data and write phase information for detecting memory slip. The write address counter 21 outputs a write address when writing data to the memory and first frame phase information for detecting slip. The read address counter 22 outputs a read address when reading data from the memory 20 and second frame phase information for slip detection. The memory slip detection circuit 23 compares the first frame phase information and the second frame phase information to detect a memory slip.
[0004]
Next, the operation of the asynchronous detection circuit shown in FIG. 4 will be described. The write address counter 21 outputs write side frame phase information and a write address by a write frame pulse and a clock. The write side frame phase information is sequentially written in the memory 20 in the same manner as the data signal by controlling the write address. The read address counter 22 outputs read side frame phase information and a read address by a read frame pulse and a clock. The read side frame phase information is the same as the write side frame phase information generated by the write address counter 21. On the other hand, the data signal and the memory read frame phase information are read from the memory 20 by the read address from the read address counter 22. The memory slip detection circuit 23 compares the memory read frame phase information and the read side frame phase information, and detects a frame phase shift when passing through the memory 20. When no memory slip has occurred, the phase information of both coincides. On the other hand, if a memory slip has occurred, the phase information of the two does not match, so a slip (SLIP) alarm is output from the memory slip detection circuit 23 as shown in FIG.
[0005]
Further, as disclosed in “Clock Change Circuit” of Japanese Patent Laid-Open No. 7-30529, it is used to monitor the memory write phase and read phase difference of the clock change circuit.
[0006]
Next, FIG. 5 is a block diagram showing the configuration of another conventional example using an asynchronous detection circuit. This asynchronous detection circuit includes memories 30 and 31, delay circuits 32 and 33, a write pulse generation circuit 34, a read pulse generation circuit 35, a control circuit 36, and a selection circuit 37. The memories 30 and 31 write the data signal with the write clock from the write pulse generation circuit 34 and read out the data written with the read clock from the read pulse generation circuit 35. The delay circuits 32 and 33 delay by a predetermined delay amount. The write pulse generation circuit 34 outputs two types of write timing pulses for controlling writing in the memories 30 and 31. The read pulse generation circuit 35 outputs two types of read timing pulses that control reading of the memories 30 and 31. The control circuit 36 monitors the phase of the memory write timing pulse and the memory read timing pulse, and outputs a selection control signal for switching the selection circuit 37. The selection circuit 37 selects an output data signal according to the selection control signal.
[0007]
Next, the operation of the asynchronous detection circuit shown in FIG. 5 will be described. The write pulse generation circuit 34 generates a write address reset pulse for resetting the write address for each of the two memories independently using the transmission path clock. The read pulse generation circuit 35 generates a read address reset pulse for resetting the read address for each of the two memories independently every period using the in-device clock. The write address reset pulse and the read address reset pulse have the same period when they are normal, but the phases are different because they operate independently. On the other hand, at the time of asynchronous, since the respective clock frequencies are different, both the period and the phase are different.
[0008]
The control circuit 36 monitors the phases of the write reset pulse and the read reset pulse for the memory 30 and the phases of the write reset pulse and the read reset pulse for the memory 31, and detects the approach of the phases of the write and read reset pulses. . When the phase approach is detected, the selection circuit 37 outputs a selection signal so as to select the output of the memory that is not in phase approach. When the frequency of the write clock and the read clock is not synchronized, the control circuit 36 has a fixed phase difference between the two reset pulses. However, when a frequency variation occurs in one or both clocks, the phase difference between both reset pulses varies. By detecting this variation, asynchronous such as clock slip is detected.
[0009]
[Problems to be solved by the invention]
The above-described prior art has the following problems. First, asynchronous detection may not be performed reliably. The reason is that the conventional asynchronous detection circuit can detect only the occurrence of slipping even if memory reading / writing is mistaken once or ten times. That is, only the presence / absence of slip occurrence can be determined within a fixed monitoring period such as a reset period or a frame period.
[0010]
Second, in order to compare phase information on the writing side and phase information on the reading side, a memory for phase information is required, and the circuit configuration becomes large. The reason for this is that, as in the prior art shown in FIG. 4, a timing signal such as a write frame pulse is written to the memory in the same manner as the data signal, and after reading and synchronizing with the clock on the read side, Asynchronous is detected by comparing with a simple timing signal. For this reason, a memory for timing signals is required, and the circuit becomes large.
[0011]
OBJECT OF THE INVENTION
The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to provide an asynchronous detection circuit for monitoring the phase relationship between memory write and read clocks. It is another object of the present invention to provide an asynchronous detection circuit that eliminates the need for an asynchronous detection memory and reduces the circuit scale.
[0012]
[Means for Solving the Problems]
An asynchronous detection circuit of the present invention is a circuit for detecting the asynchronousness of a write clock signal and a read clock signal when writing input data to a memory by a write clock signal and reading the written data by a read clock signal. A counter for counting the number of phase slips in the monitoring section is provided, and an asynchronous state is detected based on the number of phase slips.
[0013]
Further, according to the preferred embodiment of the asynchronous detection circuit of the present invention, the determination threshold for the number of phase slips is set in a programmable manner. A programmable counter is used as the counter, and a determination circuit for determining the count value of the programmable counter based on the determination threshold value is provided. A ½ frequency divider and a flip-flop for dividing the write clock signal by ½ are provided in the preceding stage of the programmable counter. An interval counter that receives the read clock signal is provided to generate a monitoring interval that is input to the 1/2 frequency divider and the programmable counter and a determination interval that is input to the determination circuit. A phase comparator that compares phases with a write clock signal and a read clock signal, and a VCO (voltage controlled oscillator) that controls a read clock signal by inputting a comparison result of the phase comparator.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the configuration and operation of a preferred embodiment of an asynchronous detection circuit according to the present invention will be described in detail with reference to the accompanying drawings.
[0015]
First, FIG. 1 is a block diagram showing a configuration of a preferred embodiment of an asynchronous detection circuit according to the present invention. This asynchronous detection circuit includes an asynchronous detector 1, a memory 2, a write (write) counter 3, a read (read) counter 4, a VCO (voltage controlled oscillator) 5, and a phase comparator 6.
[0016]
Here, the write counter 3 generates a memory write signal from the input clock (write clock signal). The read counter 4 generates a memory read signal from the output clock (read clock signal). The memory 2 reads and writes input data (or data signal). The phase comparator 6 compares the phase difference between the write clock signal and the read clock signal. The VCO 5 controls the oscillation frequency according to the comparison result of the phase comparator 6. The asynchronous detector 1 detects the synchronization state between the memory write clock and the read clock.
[0017]
Next, FIG. 2 is a block diagram showing a detailed configuration of the asynchronous detector 1 in FIG. The asynchronous detector 1 includes a 1/2 frequency divider 10, a D-type flip-flop (hereinafter referred to as D-FF) 11, a programmable counter 12, a determination circuit 13, and an interval counter 14. The 1/2 frequency divider 10 receives the write clock and the monitoring interval signal from the interval counter 14, and inputs the output to the D-FF 11. A read clock is input to the clock terminal C and the interval counter 14 of the D-FF 11. The programmable counter 12 receives an output signal from the D-FF 11, a monitoring interval signal from the interval counter 14, and a count value setting signal from the outside. The determination circuit 13 receives the output signal of the programmable counter 12, the determination interval signal from the interval counter 14, and the determination threshold setting signal from the outside, and outputs an asynchronous detection signal. The interval counter 14 receives an interval setting signal from the outside.
[0018]
Here, the 1/2 frequency divider 10 divides the input write clock by 1/2 to generate a comparison signal for detecting slip information. The D-FF 11 converts the write clock divided by 1/2 into a signal synchronized with the read clock. The interval counter 14 generates a monitoring cycle interval signal and a determination interval signal. The programmable counter 12 counts phase information during the monitoring period. The determination circuit 13 recognizes the number of slip occurrences and performs an asynchronous determination according to the number of slips. The determination circuit 13 can be composed of a logic circuit or a software processing circuit such as a CPU (central processing unit).
[0019]
Next, the operation of the preferred embodiment of the asynchronous detection circuit according to the present invention shown in FIG. 1 will be described. Writing of input data to the memory 2 is performed by the write counter 3 using the write address signal and the write clock signal from the input clock signal. Data signal reading from the memory 2 is performed by the read counter 4 using the read address signal and the read clock signal from the output clock signal generated by the voltage controlled oscillator (VCO) 5. The phase relationship between the write clock and the read clock is detected by the phase comparator 6 and the comparison result is used for controlling the VCO 5 to synchronize the write clock and the read clock. In the asynchronous detector 1, an asynchronous detection determination is performed using a write clock signal and a read clock signal.
[0020]
Next, the operation of the asynchronous detection circuit according to the present invention will be described in detail with reference to FIGS. FIG. 3A is a timing chart in the synchronized state of the write clock signal and the read clock signal. In this specific example, the interval period is 200 clocks, the programmable count value is 100, and the determination threshold is 3. FIG. 3B is a timing chart in the asynchronous state of both clock signals described above. 3A and 3B, (a) is a monitoring interval, (b) is a determination interval, (c) is a write clock, (d) is a read clock, and (e) is a 1/2 frequency divider 10. (F) is the counter clock, and (g) is the count value of the programmable counter 12.
[0021]
In the case of FIG. 3A, the write clock signal (see FIG. 3C) and the read clock signal (see FIG. 3D) are synchronized, so that a constant phase relationship is always maintained. ing. The 1/2 divider 10 is initialized by the monitoring interval signal (see FIG. 3A), and divides the write clock (see FIG. 3C) by 1/2. Here, the initialization with the monitoring interval signal (see FIG. 3A) is to synchronize with the initialization of the programmable counter 12. The output signal of the 1/2 frequency divider 10 (see FIG. 3E) is changed to the read clock (see FIG. 3D) by passing through the D-FF 11. In the synchronized state, the output of the D-FF 11 has a pattern that repeats at the monitoring interval period.
[0022]
The programmable counter 12 becomes a count set value by the monitoring interval signal (see FIG. 3A), and counts down using the output signal of the D-FF 11 as a clock. When the write clock signal and the read clock signal are synchronized, the count starts from the set value and ends at zero. In the determination circuit 13, the count value “0” of the programmable counter 12 is captured by a determination interval signal (see FIG. 3B). Then, the captured count value is compared with the set threshold value. When the captured value is within the threshold range, a signal indicating the synchronization state is output.
[0023]
Next, FIG. 3B is a timing chart in an asynchronous state. The setting is the same as the synchronization state shown in FIG. Since the write clock signal (see FIG. 3C) and the read clock signal (see FIG. 3D) are not synchronized, they have a disparate phase relationship. The 1/2 divider 10 is initialized by the monitoring interval signal (see FIG. 3A) and divides the write clock (see FIG. 3C) by 1/2. Because of the asynchronous state, the frequency-divided output signal of the 1/2 frequency divider 10 (see FIG. 3E) does not become a periodic signal. The frequency-divided output signal of the 1/2 frequency divider 10 passes through the D-FF 11 and is changed over to the read clock (see FIG. 3D). The programmable counter 12 becomes a count set value by the monitoring interval signal (see FIG. 3A), and counts down using the output signal of the D-FF 11 as a clock. Since the write clock and read clock are asynchronous, they do not end at zero. In the determination circuit 13, the count value “4” of the programmable counter 12 is captured by the determination interval signal, and the captured count value is compared with the set threshold value. If the captured value is not within the threshold range, an asynchronous detection signal indicating asynchronous is output.
[0024]
The configuration and operation of the preferred embodiment of the asynchronous detection circuit according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.
[0025]
【The invention's effect】
As is apparent from the above description, the asynchronous detection circuit of the present invention provides the following remarkable effects in practical use. First, asynchronous detection can be reliably performed. The reason is that the determination threshold is set and controlled, and the asynchronous state is determined based on whether or not the number of slips exceeds the threshold. Therefore, the threshold value is adjusted according to the line quality, that is, when the line quality is deteriorated, the threshold value can be set large, so that fine asynchronous detection can be performed.
[0026]
Second, it is possible to reduce the circuit scale. This is because the circuit scale can be reduced as compared with a conventional asynchronous detection circuit using a memory because the state of the memory write clock and the read clock is monitored.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a preferred embodiment of an asynchronous detection circuit according to the present invention.
FIG. 2 is a detailed block diagram showing a configuration of an asynchronous detector in FIG. 1;
FIGS. 3A and 3B are timing charts for explaining the operation of the asynchronous detection circuit of the present invention shown in FIGS. 1 and 2, wherein FIG. 3A shows a synchronous state and FIG. 3B shows an asynchronous state.
FIG. 4 is a block diagram showing a configuration of a first conventional example of an asynchronous detection circuit.
FIG. 5 is a block diagram showing a configuration of a second conventional example of an asynchronous detection circuit.
[Explanation of symbols]
1 Asynchronous Detector 2 Memory 3 Write Counter 4 Read Counter 5 VCO (Voltage Controlled Oscillator)
6 Phase comparator 10 1/2 divider 11 D-type flip-flop (D-FF)
12 Programmable counter 13 Judgment circuit 14 Interval counter

Claims (6)

In the asynchronous detection circuit for detecting the asynchronous of the write clock signal and the read clock signal when writing the input data to the memory by the write clock signal and reading the written data by the read clock signal,
An asynchronous detection circuit comprising: a counter that counts the number of phase slips in the monitoring section of the memory, and detecting an asynchronous state based on the number of phase slips. The asynchronous detection circuit according to claim 1, wherein a determination threshold for the number of phase slips is set in a programmable manner. The asynchronous detection circuit according to claim 1, further comprising a determination circuit that uses a programmable counter as the counter and determines a count value of the programmable counter based on a determination threshold. 4. The asynchronous detection circuit according to claim 3, wherein a ½ divider and a flip-flop for dividing the write clock signal by ½ are provided in a preceding stage of the programmable counter. The interval counter which receives the said read-out clock signal is provided, The monitoring interval input into the said 1/2 frequency divider and the said programmable counter, and the determination interval input into the said determination circuit are produced | generated. Asynchronous detection circuit. A phase comparator for comparing phases of the write clock signal and the read clock signal, and a VCO (voltage controlled oscillator) for controlling the read clock signal by inputting a comparison result of the phase comparator. Item 6. The asynchronous detection circuit according to any one of Items 1 to 5.

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