JP2011141781A5 - - Google Patents

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Publication number
JP2011141781A5
JP2011141781A5 JP2010002540A JP2010002540A JP2011141781A5 JP 2011141781 A5 JP2011141781 A5 JP 2011141781A5 JP 2010002540 A JP2010002540 A JP 2010002540A JP 2010002540 A JP2010002540 A JP 2010002540A JP 2011141781 A5 JP2011141781 A5 JP 2011141781A5
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JP
Japan
Prior art keywords
level
mask
data strobe
strobe signal
delay value
Prior art date
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Application number
JP2010002540A
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English (en)
Japanese (ja)
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JP5450112B2 (ja
JP2011141781A (ja
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Priority to JP2010002540A priority Critical patent/JP5450112B2/ja
Priority claimed from JP2010002540A external-priority patent/JP5450112B2/ja
Publication of JP2011141781A publication Critical patent/JP2011141781A/ja
Publication of JP2011141781A5 publication Critical patent/JP2011141781A5/ja
Application granted granted Critical
Publication of JP5450112B2 publication Critical patent/JP5450112B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010002540A 2010-01-08 2010-01-08 メモリインターフェース回路 Expired - Fee Related JP5450112B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010002540A JP5450112B2 (ja) 2010-01-08 2010-01-08 メモリインターフェース回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010002540A JP5450112B2 (ja) 2010-01-08 2010-01-08 メモリインターフェース回路

Publications (3)

Publication Number Publication Date
JP2011141781A JP2011141781A (ja) 2011-07-21
JP2011141781A5 true JP2011141781A5 (enExample) 2012-04-12
JP5450112B2 JP5450112B2 (ja) 2014-03-26

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ID=44457568

Family Applications (1)

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JP2010002540A Expired - Fee Related JP5450112B2 (ja) 2010-01-08 2010-01-08 メモリインターフェース回路

Country Status (1)

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JP (1) JP5450112B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102235521B1 (ko) 2015-02-13 2021-04-05 삼성전자주식회사 특정 패턴을 갖는 저장 장치 및 그것의 동작 방법
CN111028873B (zh) * 2019-12-19 2022-03-01 西安紫光国芯半导体有限公司 一种用于dram物理接口的自适应读通路延迟计算方法及电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4284527B2 (ja) * 2004-03-26 2009-06-24 日本電気株式会社 メモリインターフェイス制御回路
JP4747621B2 (ja) * 2005-03-18 2011-08-17 日本電気株式会社 メモリインターフェイス制御回路
JP5061722B2 (ja) * 2007-05-24 2012-10-31 富士通セミコンダクター株式会社 信号マスキング回路、及び、その回路を搭載した半導体集積回路
JP4967850B2 (ja) * 2007-06-26 2012-07-04 ソニー株式会社 メモリインタフェース回路

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