JP2009528635A5 - - Google Patents

Download PDF

Info

Publication number
JP2009528635A5
JP2009528635A5 JP2008557438A JP2008557438A JP2009528635A5 JP 2009528635 A5 JP2009528635 A5 JP 2009528635A5 JP 2008557438 A JP2008557438 A JP 2008557438A JP 2008557438 A JP2008557438 A JP 2008557438A JP 2009528635 A5 JP2009528635 A5 JP 2009528635A5
Authority
JP
Japan
Prior art keywords
memory
speed
circuit
shift register
timing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008557438A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009528635A (ja
JP4932856B2 (ja
Filing date
Publication date
Priority claimed from US11/366,286 external-priority patent/US7483327B2/en
Application filed filed Critical
Publication of JP2009528635A publication Critical patent/JP2009528635A/ja
Publication of JP2009528635A5 publication Critical patent/JP2009528635A5/ja
Application granted granted Critical
Publication of JP4932856B2 publication Critical patent/JP4932856B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2008557438A 2006-03-02 2007-01-29 集積回路の動作パラメータを調整するための装置及び方法 Expired - Fee Related JP4932856B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/366,286 US7483327B2 (en) 2006-03-02 2006-03-02 Apparatus and method for adjusting an operating parameter of an integrated circuit
US11/366,286 2006-03-02
PCT/US2007/061189 WO2007117745A2 (en) 2006-03-02 2007-01-29 Apparatus and method for adjusting an operating parameter of an integrated circuit

Publications (3)

Publication Number Publication Date
JP2009528635A JP2009528635A (ja) 2009-08-06
JP2009528635A5 true JP2009528635A5 (enExample) 2010-03-18
JP4932856B2 JP4932856B2 (ja) 2012-05-16

Family

ID=38519422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008557438A Expired - Fee Related JP4932856B2 (ja) 2006-03-02 2007-01-29 集積回路の動作パラメータを調整するための装置及び方法

Country Status (6)

Country Link
US (1) US7483327B2 (enExample)
EP (1) EP1994420B1 (enExample)
JP (1) JP4932856B2 (enExample)
KR (1) KR101367063B1 (enExample)
TW (1) TWI459403B (enExample)
WO (1) WO2007117745A2 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7639531B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Dynamic cell bit resolution
US7551486B2 (en) * 2006-05-15 2009-06-23 Apple Inc. Iterative memory cell charging based on reference cell value
US7911834B2 (en) * 2006-05-15 2011-03-22 Apple Inc. Analog interface for a flash memory die
US7701797B2 (en) * 2006-05-15 2010-04-20 Apple Inc. Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
US7511646B2 (en) * 2006-05-15 2009-03-31 Apple Inc. Use of 8-bit or higher A/D for NAND cell value
US7568135B2 (en) * 2006-05-15 2009-07-28 Apple Inc. Use of alternative value in cell detection
US8000134B2 (en) 2006-05-15 2011-08-16 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7639542B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US7852690B2 (en) * 2006-05-15 2010-12-14 Apple Inc. Multi-chip package for a flash memory
US7613043B2 (en) * 2006-05-15 2009-11-03 Apple Inc. Shifting reference values to account for voltage sag
US7546410B2 (en) * 2006-07-26 2009-06-09 International Business Machines Corporation Self timed memory chip having an apportionable data bus
US8050781B2 (en) * 2007-06-29 2011-11-01 Emulex Design & Manufacturing Corporation Systems and methods for ASIC power consumption reduction
JP5228468B2 (ja) * 2007-12-17 2013-07-03 富士通セミコンダクター株式会社 システム装置およびシステム装置の動作方法
US7684263B2 (en) * 2008-01-17 2010-03-23 International Business Machines Corporation Method and circuit for implementing enhanced SRAM write and read performance ring oscillator
US7852692B2 (en) * 2008-06-30 2010-12-14 Freescale Semiconductor, Inc. Memory operation testing
US8909957B2 (en) * 2010-11-04 2014-12-09 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Dynamic voltage adjustment to computer system memory
KR20130021175A (ko) 2011-08-22 2013-03-05 삼성전자주식회사 메모리 장치 및 이를 포함하는 장치들
US8717831B2 (en) 2012-04-30 2014-05-06 Hewlett-Packard Development Company, L.P. Memory circuit
US9105328B2 (en) * 2012-07-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Tracking signals in memory write or read operation
EP2932506A4 (en) * 2012-12-11 2016-08-10 Hewlett Packard Entpr Dev Lp DATA OPERATION IN A SHIFT REGISTER CYCLE
EP2932505A4 (en) 2013-03-28 2016-08-10 Hewlett Packard Entpr Dev Lp DEVICE AND METHOD FOR READING A MEMORY DEVICE
KR20150043122A (ko) * 2013-10-14 2015-04-22 에스케이하이닉스 주식회사 반도체 장치
US9858217B1 (en) * 2016-06-29 2018-01-02 Qualcomm Incorporated Within-die special oscillator for tracking SRAM memory performance with global process variation, voltage and temperature
US11196574B2 (en) * 2017-08-17 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Physically unclonable function (PUF) generation
US11294678B2 (en) 2018-05-29 2022-04-05 Advanced Micro Devices, Inc. Scheduler queue assignment
US11334384B2 (en) * 2019-12-10 2022-05-17 Advanced Micro Devices, Inc. Scheduler queue assignment burst mode
KR20220022618A (ko) 2020-08-19 2022-02-28 에스케이하이닉스 주식회사 클록 모니터링 회로
US11948000B2 (en) 2020-10-27 2024-04-02 Advanced Micro Devices, Inc. Gang scheduling for low-latency task synchronization
CN114705973B (zh) * 2022-06-01 2022-11-11 北京航空航天大学杭州创新研究院 非侵入式的复杂环境集成电路老化监测方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4326269A (en) * 1980-06-09 1982-04-20 General Electric Company One bit memory for bipolar signals
JPH04190389A (ja) * 1990-11-26 1992-07-08 Hitachi Ltd 画像表示装置のルックアップテーブル書換え方式
JP3609868B2 (ja) 1995-05-30 2005-01-12 株式会社ルネサステクノロジ スタティック型半導体記憶装置
US5978929A (en) * 1997-03-20 1999-11-02 International Business Machines Corporation Computer unit responsive to difference between external clock period and circuit characteristic period
JP2001034530A (ja) * 1999-07-16 2001-02-09 Mitsubishi Electric Corp マイクロコンピュータおよびメモリアクセス制御方法
US6327224B1 (en) 2000-06-16 2001-12-04 International Business Machines Corporation On-chip method for measuring access time and data-pin spread
US6269043B1 (en) * 2000-07-31 2001-07-31 Cisco Technology, Inc. Power conservation system employing a snooze mode
JP2002244917A (ja) * 2001-02-15 2002-08-30 Matsushita Electric Ind Co Ltd アクセス管理装置、およびプログラム
US6483754B1 (en) 2001-05-16 2002-11-19 Lsi Logic Corporation Self-time scheme to reduce cycle time for memories
JP4894095B2 (ja) * 2001-06-15 2012-03-07 富士通セミコンダクター株式会社 半導体記憶装置
US6901027B2 (en) * 2002-04-30 2005-05-31 Sony Corporation Apparatus for processing data, memory bank used therefor, semiconductor device, and method for reading out pixel data
US6985375B2 (en) * 2003-06-11 2006-01-10 Micron Technology, Inc. Adjusting the frequency of an oscillator for use in a resistive sense amp
JP4025260B2 (ja) * 2003-08-14 2007-12-19 株式会社東芝 スケジューリング方法および情報処理システム
JP4198644B2 (ja) 2004-06-21 2008-12-17 富士通マイクロエレクトロニクス株式会社 半導体集積回路
US7409315B2 (en) 2004-06-28 2008-08-05 Broadcom Corporation On-board performance monitor and power control system
US7327185B2 (en) * 2004-11-02 2008-02-05 Texas Instruments Incorporated Selectable application of offset to dynamically controlled voltage supply

Similar Documents

Publication Publication Date Title
JP2009528635A5 (enExample)
TW200739604A (en) Apparatus and method for adjusting an operating parameter of an integrated circuit
US8766646B2 (en) Calibration method and apparatus for clock signal and electronic device
JP2011513812A5 (enExample)
JP2013140979A5 (ja) システムオンチップの温度管理方法
JP2009529296A5 (enExample)
JP2010044850A5 (enExample)
JP2015522800A5 (enExample)
TW200608394A (en) Integrated circuit device for providing selectively variable write latency and method thereof
JP2013064677A5 (enExample)
TW201633170A (zh) 選通訊號間隔檢測電路及包括其的記憶體系統
CN103217197B (zh) 流量计装置及操作方法
CN104798305B (zh) 用于处理由双向传感器供应的信号的方法和相应的装置
US20120304779A1 (en) Electronic flow meter
US7379383B2 (en) Methods of DDR receiver read re-synchronization
JP2004347975A (ja) データ処理装置及び論理演算装置
US9689724B2 (en) Resonant signal sensing circuit having a low power mode
CN106030543B (zh) 干扰测试
JP2020127184A5 (enExample)
TWI454900B (zh) 當使用外部時脈源時的電源最佳化
JP4352921B2 (ja) 回転位置検出装置
JP4924672B2 (ja) 回転検出装置の信号処理回路
US8271820B2 (en) Micro-processor
KR100863533B1 (ko) 반도체 장치 및 그 구동방법
JP2014526175A5 (enExample)